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AJvYcCWXkJSYd4khkyWvvyIc2qXFMaW7aMYKc4hI581qxz3VG+zj+Zatee5FwPMYPq2FqyogoCN5R7SYQnAh86LY/taCwVV6 X-Gm-Message-State: AOJu0YyHTG8C3Dg2lgJmIRLeK3+XtvEb1TNaxIXFC61qqOvZZIN1gyVs i9HUg9g+B6uj2B1Hi1ixv2s8QwGQrf0X0ly8EOxtgCb9dXv+TXsrLEpa8wUcZQ== X-Google-Smtp-Source: AGHT+IGoPWkNE6JIjVJz1XqdnjAP9lGvBAm0VujbexvNFkLOg4OzNepoOaOycaMqUlL+eVesMoK8lA== X-Received: by 2002:a17:902:db0e:b0:1dc:b77e:1973 with SMTP id m14-20020a170902db0e00b001dcb77e1973mr1593245plx.53.1709019941652; Mon, 26 Feb 2024 23:45:41 -0800 (PST) Received: from thinkpad ([117.213.97.177]) by smtp.gmail.com with ESMTPSA id l20-20020a170902e2d400b001d71729ec9csm884589plc.188.2024.02.26.23.45.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Feb 2024 23:45:41 -0800 (PST) Date: Tue, 27 Feb 2024 13:15:33 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Kishon Vijay Abraham I , Serge Semin , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, Siddharth Vadapalli Subject: Re: [PATCH v3 3/5] PCI: dwc: Pass the eDMA mapping format flag directly from glue drivers Message-ID: <20240227074533.GH2587@thinkpad> References: <20240226-dw-hdma-v3-0-cfcb8171fc24@linaro.org> <20240226-dw-hdma-v3-3-cfcb8171fc24@linaro.org> Precedence: bulk X-Mailing-List: mhi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Mon, Feb 26, 2024 at 11:30:13AM -0500, Frank Li wrote: > On Mon, Feb 26, 2024 at 05:07:28PM +0530, Manivannan Sadhasivam wrote: > > Instead of maintaining a separate capability for glue drivers that cannot > > support auto detection of the eDMA mapping format, let's pass the mapping > > format directly from them. > > Sorry, what's mapping? is it register address layout? > Memory map containing the register layout for iATU, DMA etc... - Mani > Frank > > > > > This will simplify the code and also allow adding HDMA support that also > > doesn't support auto detection of mapping format. > > > > Suggested-by: Serge Semin > > Reviewed-by: Siddharth Vadapalli > > Signed-off-by: Manivannan Sadhasivam > > --- > > drivers/pci/controller/dwc/pcie-designware.c | 16 +++++++++------- > > drivers/pci/controller/dwc/pcie-designware.h | 5 ++--- > > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- > > 3 files changed, 12 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > > index ce273c3c5421..3e90b9947a13 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > @@ -894,18 +894,20 @@ static int dw_pcie_edma_find_mf(struct dw_pcie *pci) > > { > > u32 val; > > > > + /* > > + * Bail out finding the mapping format if it is already set by the glue > > + * driver. Also ensure that the edma.reg_base is pointing to a valid > > + * memory region. > > + */ > > + if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) > > + return pci->edma.reg_base ? 0 : -ENODEV; > > + > > /* > > * Indirect eDMA CSRs access has been completely removed since v5.40a > > * thus no space is now reserved for the eDMA channels viewport and > > * former DMA CTRL register is no longer fixed to FFs. > > - * > > - * Note that Renesas R-Car S4-8's PCIe controllers for unknown reason > > - * have zeros in the eDMA CTRL register even though the HW-manual > > - * explicitly states there must FFs if the unrolled mapping is enabled. > > - * For such cases the low-level drivers are supposed to manually > > - * activate the unrolled mapping to bypass the auto-detection procedure. > > */ > > - if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL)) > > + if (dw_pcie_ver_is_ge(pci, 540A)) > > val = 0xFFFFFFFF; > > else > > val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > > index 26dae4837462..995805279021 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > @@ -51,9 +51,8 @@ > > > > /* DWC PCIe controller capabilities */ > > #define DW_PCIE_CAP_REQ_RES 0 > > -#define DW_PCIE_CAP_EDMA_UNROLL 1 > > -#define DW_PCIE_CAP_IATU_UNROLL 2 > > -#define DW_PCIE_CAP_CDM_CHECK 3 > > +#define DW_PCIE_CAP_IATU_UNROLL 1 > > +#define DW_PCIE_CAP_CDM_CHECK 2 > > > > #define dw_pcie_cap_is(_pci, _cap) \ > > test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) > > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c > > index e9166619b1f9..3c535ef5ea91 100644 > > --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c > > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c > > @@ -255,7 +255,7 @@ static struct rcar_gen4_pcie *rcar_gen4_pcie_alloc(struct platform_device *pdev) > > rcar->dw.ops = &dw_pcie_ops; > > rcar->dw.dev = dev; > > rcar->pdev = pdev; > > - dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL); > > + rcar->dw.edma.mf = EDMA_MF_EDMA_UNROLL; > > dw_pcie_cap_set(&rcar->dw, REQ_RES); > > platform_set_drvdata(pdev, rcar); > > > > > > -- > > 2.25.1 > > -- மணிவண்ணன் சதாசிவம்