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AJvYcCVMq94cIGWToScBJ5rnFx8E9cyvwpV744f9VKnVYvbloyC++WnV94HxbEHzxHJS9qa4LXuCqFIl3GaK5GVOcBUep+In X-Gm-Message-State: AOJu0Yx/SQgWK5NdLw34TeLfxawkW4BqaMqGWPhQr5tRRckwP+KXW4vg /BuJIUM31DhTFQFQRaAe1NE24qIpKmiaSqVo72PuUhWwN8Zqv0gpmoXkD8Ah5g== X-Google-Smtp-Source: AGHT+IEKMHb+7xvRCgR/g4XEp4tB9vwgi0BH58gTwM7mvpy1llF9PEEfvC2uPC2VQbcd7dshAsa6Mg== X-Received: by 2002:a17:903:22d1:b0:1e0:1a96:33d1 with SMTP id y17-20020a17090322d100b001e01a9633d1mr2858887plg.16.1710740082128; Sun, 17 Mar 2024 22:34:42 -0700 (PDT) Received: from thinkpad ([103.246.195.160]) by smtp.gmail.com with ESMTPSA id mp6-20020a170902fd0600b001dee3c1559dsm7127313plb.303.2024.03.17.22.34.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Mar 2024 22:34:41 -0700 (PDT) Date: Mon, 18 Mar 2024 11:04:36 +0530 From: Manivannan Sadhasivam To: Serge Semin Cc: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Kishon Vijay Abraham I , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, Siddharth Vadapalli , Frank Li Subject: Re: [PATCH v4 2/5] PCI: dwc: Skip finding eDMA channels count for HDMA platforms Message-ID: <20240318053436.GE2748@thinkpad> References: <20240306-dw-hdma-v4-0-9fed506e95be@linaro.org> <20240306-dw-hdma-v4-2-9fed506e95be@linaro.org> Precedence: bulk X-Mailing-List: mhi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Tue, Mar 12, 2024 at 12:17:48PM +0300, Serge Semin wrote: > On Wed, Mar 06, 2024 at 03:51:58PM +0530, Manivannan Sadhasivam wrote: > > In the case of Hyper DMA (HDMA) present in DWC controllers, there is no way > > the drivers can auto detect the number of read/write channels as like its > > predecessor embedded DMA (eDMA). So the glue drivers making use of HDMA > > have to pass the channels count during probe. > > > > To accommodate that, let's skip the existing auto detection of channels > > count procedure for HDMA based platforms. If the channels count passed by > > the glue drivers were wrong in any form, then the existing sanity check > > will catch it. > > > > Suggested-by: Serge Semin > > Reviewed-by: Siddharth Vadapalli > > Reviewed-by: Frank Li > > Signed-off-by: Manivannan Sadhasivam > > Reviewed-by: Serge Semin > > Please find a tiny nitpick further below. > > > --- > > drivers/pci/controller/dwc/pcie-designware.c | 15 ++++++++++----- > > 1 file changed, 10 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > > index 3a26dfc5368f..599991b7ffb2 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > @@ -927,13 +927,18 @@ static int dw_pcie_edma_find_channels(struct dw_pcie *pci) > > { > > u32 val; > > > > - if (pci->edma.mf == EDMA_MF_EDMA_LEGACY) > > - val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); > > - else > > > + /* > > + * Autodetect the read/write channels count only for non-HDMA platforms. > > + * HDMA platforms doesn't support autodetect, so the glue drivers should've > > + * passed the valid count already. If not, the below sanity check will > > + * catch it. > > + */ > > This is correct for the _native_ HDMA CSRs mapping. I suggest to emphasize > that in the note above. > Ack. - Mani -- மணிவண்ணன் சதாசிவம்