From: "Slark Xiao" <slark_xiao@163.com>
To: "Manivannan Sadhasivam" <mani@kernel.org>
Cc: mhi@lists.linux.dev
Subject: Re:Re: failed to power up MHI controller issue
Date: Mon, 8 Apr 2024 17:59:29 +0800 (CST) [thread overview]
Message-ID: <4d76dd24.edcc.18ebd2606cc.Coremail.slark_xiao@163.com> (raw)
In-Reply-To: <20240402045647.GG2933@thinkpad>
[-- Attachment #1.1: Type: text/plain, Size: 1252 bytes --]
Hi Mani,
Please see attached log files(both kernel log and IPC log).
At 2024-04-02 12:56:47, "Manivannan Sadhasivam" <mani@kernel.org> wrote:
>+ MHI list
>
>On Thu, Mar 28, 2024 at 08:02:20PM +0800, Slark Xiao wrote:
>> Hi Mani,
>> Hope you are doing well! I got a problem with our sdx65 device in some
>>
>> specific platform. MHI driver would report "failed to power up MHI controller"
>> when device bootup. Actually, I can reproduce this error when host doing a
>> reboot. It's Rockpro64 with SDX65, and kernel 6.6.3 or 6.7.10.
>>
>> So I add some logs and change dbg level log to info for more print. You can
>> see my attachments for reference.
>> It seems the host didn't receive the event of "MISSION MODE" and then
>> power down the device.
>> BTW, there are some extra log prints were added in function
>> mhi_sync_power_up(). You can find it with mask "##shawn##".
>> Do you have any idea to debug it?
>>
>
>Looks like something gone wrong with the device firmware. Is it possible to get
>the logs from the device?
>
>This could be due to the way the PCIe controller driver on the host handling
>reboot.
>
>But let's get the device logs first to debug further.
>
>- Mani
>
>--
>மணிவண்ணன் சதாசிவம்
[-- Attachment #1.2: Type: text/html, Size: 1693 bytes --]
[-- Attachment #2: board_putty.log --]
[-- Type: text/plain, Size: 740632 bytes --]
~ # dmesg
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 5.4.210-perf (oe-user@oe-host) (clang version 10.0.1 (https://github.com/llvm/llvm-project ef32c611aa214dea855364efd7ba451ec5ec3f74), GNU ld (GNU Binutils) 2.34.0.20200220) #1 PREEMPT Wed Mar 20 00:12:54 CST 2024
[ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c53c7d
[ 0.000000] CPU: div instructions available: patching division code
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] OF: fdt: Machine model: Qualcomm Technologies, Inc. SDXLEMUR MTP MBB M2 EP V2 512mb
[ 0.000000] Memory policy: Data cache writeback
[ 0.000000] Reserved memory: created CMA memory pool at 0x8f800000, size 4 MiB
[ 0.000000] OF: reserved mem: initialized node mem_dump_region, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created CMA memory pool at 0x8c000000, size 4 MiB
[ 0.000000] OF: reserved mem: initialized node qseecom_region, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created CMA memory pool at 0x8b400000, size 12 MiB
[ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created CMA memory pool at 0x8b000000, size 4 MiB
[ 0.000000] OF: reserved mem: initialized node qseecom_ta_region, compatible id shared-dma-pool
[ 0.000000] On node 0 totalpages: 52463
[ 0.000000] Normal zone: 528 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 52463 pages, LIFO batch:15
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.1 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] psci: SMC Calling Convention v1.1
[ 0.000000] psci: OSI mode supported.
[ 0.000000] psci: Switched to OSI mode.
[ 0.000000] CPU: All CPU(s) started in SVC mode.
[ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 51935
[ 0.000000] Kernel command line: reboot=w ro rootwait console=ttyMSM0,115200,n8 androidboot.hardware=qcom msm_rtb.filter=0x237 androidboot.console=ttyMSM0 lpm_levels.sleep_disabled=1 firmware_class.path=/lib/firmware/updates service_locator.enable=1 net.ifnames=0 atlantic_fwd.rx_ring_size=512 atlantic_fwd.rx_linear=1 pcie_ports=compat pci=pcie_bus_perf rootfstype=ubifs rootflags=bulk_read root=ubi0:rootfs ubi.mtd=40 androidboot.serialno=ea1054e8 androidboot.baseband=msm androidboot.force_normal_boot=1
[ 0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] Memory: 161188K/209852K available (12288K kernel code, 883K rwdata, 4172K rodata, 1024K init, 2107K bss, 24088K reserved, 24576K cma-reserved)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc80000 - 0xfff00000 (2560 kB)
[ 0.000000] vmalloc : 0xc0800000 - 0xff800000 (1008 MB)
[ 0.000000] lowmem : 0xc0600000 - 0xc0800000 ( 2 MB)
[ 0.000000] vmalloc : 0xbfe00000 - 0xc0600000 ( 8 MB)
[ 0.000000] lowmem : 0xbfdc0000 - 0xbfe00000 ( 0 MB)
[ 0.000000] vmalloc : 0xbfd00000 - 0xbfdc0000 ( 0 MB)
[ 0.000000] lowmem : 0xbfcfe000 - 0xbfd00000 ( 0 MB)
[ 0.000000] vmalloc : 0xbfcad000 - 0xbfcfe000 ( 0 MB)
[ 0.000000] lowmem : 0xbf600000 - 0xbfcad000 ( 6 MB)
[ 0.000000] vmalloc : 0xbc400000 - 0xbf600000 ( 50 MB)
[ 0.000000] lowmem : 0xb0000000 - 0xbc400000 ( 196 MB)
[ 0.000000] modules : 0xaf000000 - 0xb0000000 ( 16 MB)
[ 0.000000] .text : 0x(ptrval) - 0x(ptrval) (13280 kB)
[ 0.000000] .init : 0x(ptrval) - 0x(ptrval) (1024 kB)
[ 0.000000] .data : 0x(ptrval) - 0x(ptrval) ( 884 kB)
[ 0.000000] .bss : 0x(ptrval) - 0x(ptrval) (2108 kB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
[ 0.000000] Tasks RCU enabled.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] arch_sys_timer depends on broadcast, but no broadcast function available
[ 0.000000] arch_timer: cp15 and mmio timer(s) running at 19.20MHz (virt/virt).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x46d987e47, max_idle_ns: 440795202767 ns
[ 0.000004] sched_clock: 56 bits at 19MHz, resolution 52ns, wraps every 4398046511078ns
[ 0.000011] Switching to timer-based delay loop, resolution 52ns
[ 0.000025] clocksource: Switched to clocksource arch_sys_counter
[ 0.001008] Calibrating delay loop (skipped), value calculated using timer frequency.. 38.40 BogoMIPS (lpj=192000)
[ 0.001029] pid_max: default: 32768 minimum: 301
[ 0.001302] LSM: Security Framework initializing
[ 0.001403] SELinux: Initializing.
[ 0.001583] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.001591] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.002357] CPU: Testing write buffer coherency: ok
[ 0.003162] Setting up static identity map for 0x80100000 - 0x80100060
[ 0.003255] rcu: Hierarchical SRCU implementation.
[ 0.003456] scm_mem_protection_init_do: SCM call failed
[ 0.003854] devtmpfs: initialized
[ 0.028222] VFP support v0.3: implementor 41 architecture 2 part 30 variant 7 rev 5
[ 0.028600] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.028619] futex hash table entries: 256 (order: -1, 3072 bytes, linear)
[ 0.029343] pinctrl core: initialized pinctrl subsystem
[ 0.030743] NET: Registered protocol family 16
[ 0.031600] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.032083] DMA: preallocated 256 KiB pool for atomic allocations
[ 0.032106] audit: initializing netlink subsys (disabled)
[ 0.032958] cpuidle: using governor menu
[ 0.033072] NET: Registered protocol family 42
[ 0.033238] audit: type=2000 audit(0.029:1): state=initialized audit_enabled=0 res=1
[ 0.035100] msm-dcc 117f000.dcc_v2: DCC list passed 2
[ 0.035118] msm-dcc 117f000.dcc_v2: All values written to enable.
[ 0.035683] msm_watchdog 17817000.qcom,wdt: QCOM Apps Watchdog Initialized
[ 0.134832] hw-breakpoint: Failed to enable monitor mode on CPU 0.
[ 0.135516] gpiochip_find_base: found new base at 916
[ 0.135860] gpio gpiochip0: (f100000.pinctrl): added GPIO chardev (254:0)
[ 0.135958] gpiochip_setup_dev: registered GPIOs 916 to 1023 on device: gpiochip0 (f100000.pinctrl)
[ 0.135968] gpio gpiochip0: (f100000.pinctrl): created GPIO range 0->107 ==> f100000.pinctrl PIN 0->107
[ 0.138002] DMA: preallocated 256 KiB pool for atomic allocations
[ 0.139533] spmi spmi-0: PMIC arbiter version v5 (0x50020000)
[ 0.151449] msm_sps_probe: sps:sps is ready
[ 0.158917] (NULL device *): msm_gsi_probe:5894 No MSIs configured
[ 0.173593] qmp-aop-clk soc:clock-controller@0: Registered clocks with AOP
[ 0.174924] pil: failed to find qcom,msm-imem-pil-disable-timeout node
[ 0.175056] KPI: Bootloader start count = 77734
[ 0.175061] KPI: Bootloader end count = 112794
[ 0.175065] KPI: Bootloader display count = 342243172
[ 0.175068] KPI: Bootloader load kernel count = 24983
[ 0.175072] KPI: Kernel MPM timestamp = 126856
[ 0.175074] KPI: Kernel MPM Clock frequency = 32768
[ 0.175531] Minidump: Enabled with max number of regions 200
[ 0.175904] iommu: Default domain type: Translated
[ 0.176519] vgaarb: loaded
[ 0.176927] SCSI subsystem initialized
[ 0.177127] usbcore: registered new interface driver usbfs
[ 0.177160] usbcore: registered new interface driver hub
[ 0.177198] usbcore: registered new device driver usb
[ 0.177395] usb_phy_generic soc:usb_nop_phy: GPIO lookup for consumer reset
[ 0.177399] usb_phy_generic soc:usb_nop_phy: using device tree for GPIO lookup
[ 0.177414] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/soc/usb_nop_phy[0]'
[ 0.177423] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/soc/usb_nop_phy[0]'
[ 0.177430] usb_phy_generic soc:usb_nop_phy: using lookup tables for GPIO lookup
[ 0.177434] usb_phy_generic soc:usb_nop_phy: No GPIO consumer reset found
[ 0.177439] usb_phy_generic soc:usb_nop_phy: GPIO lookup for consumer vbus-detect
[ 0.177441] usb_phy_generic soc:usb_nop_phy: using device tree for GPIO lookup
[ 0.177450] of_get_named_gpiod_flags: can't parse 'vbus-detect-gpios' property of node '/soc/usb_nop_phy[0]'
[ 0.177458] of_get_named_gpiod_flags: can't parse 'vbus-detect-gpio' property of node '/soc/usb_nop_phy[0]'
[ 0.177462] usb_phy_generic soc:usb_nop_phy: using lookup tables for GPIO lookup
[ 0.177466] usb_phy_generic soc:usb_nop_phy: No GPIO consumer vbus-detect found
[ 0.177488] usb_phy_generic soc:usb_nop_phy: soc:usb_nop_phy supply vcc not found, using dummy regulator
[ 0.178178] qcom,qpnp-power-on c440000.qcom,spmi:qcom,pmk8350@0:pon_pbs@800: IRQ pmic-wd-bark not found
[ 0.178551] qcom,qpnp-power-on c440000.qcom,spmi:qcom,pmk8350@0:pon_hlos@1300: IRQ pmic-wd-bark not found
[ 0.178688] input: qpnp_pon as /devices/platform/c440000.qcom,spmi/spmi-0/spmi0-00/c440000.qcom,spmi:qcom,pmk8350@0:pon_hlos@1300/input/input0
[ 0.179302] thermal_sys: Registered thermal governor 'step_wise'
[ 0.179307] thermal_sys: Registered thermal governor 'user_space'
[ 0.187984] Failed to enable shmbridge, ret = 4
[ 0.188000] shmbridge is not supported by this target
[ 0.188405] IPA framework init
[ 0.193165] dev-cpufreq: No tables parsed from DT.
[ 0.193825] SDAM base=0x7100 size=128 registered successfully
[ 0.193979] SDAM base=0x7400 size=128 registered successfully
[ 0.194091] SDAM base=0x7c00 size=128 registered successfully
[ 0.194222] SDAM base=0x7d00 size=128 registered successfully
[ 0.194328] SDAM base=0x8400 size=128 registered successfully
[ 0.194455] SDAM base=0x8500 size=128 registered successfully
[ 0.194597] SDAM base=0x8600 size=128 registered successfully
[ 0.194699] SDAM base=0x9d00 size=128 registered successfully
[ 0.194826] Advanced Linux Sound Architecture Driver Initialized.
[ 0.195273] IPA clients manager init
[ 0.195278] ipa_usb driver init
[ 0.195517] ipa_usb registered successfully
[ 0.195526] exit: IPA_USB init success!
[ 0.195533] ipa_wdi3 registered successfully
[ 0.195537] ipa_gsb registered successfully
[ 0.195541] ipa_uc_offload registered successfully
[ 0.195545] ipa_mhi registered successfully
[ 0.195550] ipa_wigig registered successfully
[ 0.195554] ipa_eth registered successfully
[ 0.195558] ipa_qdss registered successfully
[ 0.196275] pcie:pcie_init.
[ 0.201284] platform soc:qcom,ion:qcom,ion-heap@27: assigned reserved memory node qseecom_region
[ 0.201911] platform soc:qcom,ion:qcom,ion-heap@19: assigned reserved memory node qseecom_ta_region
[ 0.201964] ION heap system created
[ 0.202188] ION heap qsecom created
[ 0.202240] ION heap qsecom_ta created
[ 0.202768] clocksource: Switched to clocksource arch_sys_counter
[ 0.247925] rmnet_ipa3 started initialization
[ 0.248337] NET: Registered protocol family 2
[ 0.248495] IP idents hash table entries: 4096 (order: 3, 32768 bytes, linear)
[ 0.248948] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
[ 0.248971] TCP established hash table entries: 2048 (order: 1, 8192 bytes, linear)
[ 0.248988] TCP bind hash table entries: 2048 (order: 1, 8192 bytes, linear)
[ 0.249001] TCP: Hash tables configured (established 2048 bind 2048)
[ 0.249100] UDP hash table entries: 256 (order: 0, 4096 bytes, linear)
[ 0.249113] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes, linear)
[ 0.249305] NET: Registered protocol family 1
[ 0.249851] PCI: CLS 0 bytes, default 64
[ 0.250767] hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available
[ 0.251248] [fx_oem_dev] oem_devices_init
[ 0.251255] fxinfo_init++
[ 0.251286] [Fox] pval->swinfo.smem_apps_ver= 060, APPS_VERSION= 060
[ 0.251290] [Fox] smem_p info is 49, smem_m info is 49
[ 0.251298] fxinfo_init--
[ 0.252361] Initialise system trusted keyrings
[ 0.252627] workingset: timestamp_bits=30 max_order=16 bucket_order=0
[ 0.257119] Key type asymmetric registered
[ 0.257133] Asymmetric key parser 'x509' registered
[ 0.257178] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
[ 0.257183] io scheduler mq-deadline registered
[ 0.257187] io scheduler kyber registered
[ 0.257384] io scheduler bfq registered
[ 0.259456] gpiochip_find_base: found new base at 912
[ 0.259753] gpio gpiochip1: (c440000.qcom,spmi:qcom,pmk8350@0:pinctrl@b000): added GPIO chardev (254:1)
[ 0.259848] gpiochip_setup_dev: registered GPIOs 912 to 915 on device: gpiochip1 (c440000.qcom,spmi:qcom,pmk8350@0:pinctrl@b000)
[ 0.259859] gpio gpiochip1: (c440000.qcom,spmi:qcom,pmk8350@0:pinctrl@b000): created GPIO range 0->3 ==> c440000.qcom,spmi:qcom,pmk8350@0:pinctrl@b000 PIN 0->3
[ 0.261567] gpiochip_find_base: found new base at 896
[ 0.261745] gpio gpiochip2: (c440000.qcom,spmi:qcom,pmx65@1:pinctrl@8800): added GPIO chardev (254:2)
[ 0.261822] gpiochip_setup_dev: registered GPIOs 896 to 911 on device: gpiochip2 (c440000.qcom,spmi:qcom,pmx65@1:pinctrl@8800)
[ 0.261832] gpio gpiochip2: (c440000.qcom,spmi:qcom,pmx65@1:pinctrl@8800): created GPIO range 0->15 ==> c440000.qcom,spmi:qcom,pmx65@1:pinctrl@8800 PIN 0->15
[ 0.264574] v0.15, id=509, ver=2.0, raw_id=409, raw_ver=1, hw_plat=8, hw_plat_ver=65536
[ 0.264574] accessory_chip=0, hw_plat_subtype=8, pmic_model=65583, pmic_die_revision=131072 foundry_id=7 serial_number=3926938856 num_pmics=2 chip_family=0x75 raw_device_family=0x6 raw_device_number=0x16 nproduct_id=0x427 num_clusters=0x1 ncluster_array_offset=0xb0 num_defective_parts=0xf ndefective_parts_array_offset=0xb4 nmodem_supported=0xffffffff
[ 0.265113] sdxlemur-llcc 9200000.cache-controller: IRQ index 0 not found
[ 0.265628] msm_mem_dump soc:mem_dump: assigned reserved memory node mem_dump_region
[ 0.268387] MSM Memory Dump base table set up
[ 0.268404] MSM Memory Dump apps data table set up
[ 0.272329] ff0000.qcom,msm-eud: ttyEUD0 at MMIO 0x0 (irq = 25, base_baud = 0) is a EUD UART
[ 0.273255] msm_serial: driver initialized
[ 0.282284] brd: module loaded
[ 0.287648] loop: module loaded
[ 0.288085] zram: Added device: zram0
[ 0.288587] SCSI Media Changer driver v0.25
[ 0.289521] mdio_bus fixed-0: GPIO lookup for consumer reset
[ 0.289528] mdio_bus fixed-0: using lookup tables for GPIO lookup
[ 0.289532] mdio_bus fixed-0: No GPIO consumer reset found
[ 0.289550] tun: Universal TUN/TAP device driver, 1.6
[ 0.289985] PPP generic driver version 2.4.2
[ 0.290512] usbcore: registered new interface driver asix
[ 0.290572] usbcore: registered new interface driver ax88179_178a
[ 0.290595] usbcore: registered new interface driver cdc_ether
[ 0.290648] usbcore: registered new interface driver smsc75xx
[ 0.290680] usbcore: registered new interface driver smsc95xx
[ 0.290701] usbcore: registered new interface driver net1080
[ 0.290722] usbcore: registered new interface driver cdc_subset
[ 0.290741] usbcore: registered new interface driver zaurus
[ 0.290782] usbcore: registered new interface driver cdc_ncm
[ 0.294298] msm_sharedmem: msm_sharedmem_probe: Device created for client 'rmtfs'
[ 0.295761] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 0.295771] ehci-pci: EHCI PCI platform driver
[ 0.296347] usbcore: registered new interface driver cdc_acm
[ 0.296355] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters
[ 0.296396] usbcore: registered new interface driver usb-storage
[ 0.296416] usbcore: registered new interface driver ums-alauda
[ 0.296436] usbcore: registered new interface driver ums-cypress
[ 0.296454] usbcore: registered new interface driver ums-datafab
[ 0.296472] usbcore: registered new interface driver ums-freecom
[ 0.296490] usbcore: registered new interface driver ums-isd200
[ 0.296507] usbcore: registered new interface driver ums-jumpshot
[ 0.296524] usbcore: registered new interface driver ums-karma
[ 0.296542] usbcore: registered new interface driver ums-onetouch
[ 0.296583] usbcore: registered new interface driver ums-sddr09
[ 0.296603] usbcore: registered new interface driver ums-sddr55
[ 0.296622] usbcore: registered new interface driver ums-usbat
[ 0.296646] usbcore: registered new interface driver usb_ehset_test
[ 0.296667] usbcore: registered new interface driver lvs
[ 0.297401] qti_usb_gadget: probe of qcom_gadget failed with error -22
[ 0.299166] rtc-pm8xxx c440000.qcom,spmi:qcom,pmk8350@0:rtc@6100: registered as rtc0
[ 0.299243] rtc-pm8xxx c440000.qcom,spmi:qcom,pmk8350@0:rtc@6100: setting system clock to 1970-01-01T00:00:31 UTC (31)
[ 0.299434] i2c /dev entries driver
[ 0.302031] cpuidle: using governor qcom
[ 0.303292] sdhci: Secure Digital Host Controller Interface driver
[ 0.303304] sdhci: Copyright(c) Pierre Ossman
[ 0.303308] sdhci-pltfm: SDHCI platform and OF driver helper
[ 0.303620] of_get_named_gpiod_flags: parsed 'gpios' property of node '/soc/leds/led-wwan[0]' - status (0)
[ 0.303639] no flags found for gpios
[ 0.304170] tz diag version is 0
[ 0.304210] tz_log 1468f720.tz-log: Hyp log service not support
[ 0.304234] encrypted qseelog enabled is 0
[ 0.306451] usbcore: registered new interface driver usbhid
[ 0.306464] usbhid: USB HID core driver
[ 0.308596] extcon-pm8941-misc c440000.qcom,spmi:qcom,pmx65@1:qcom,pmd-vbus-det@1500: IRQ usb_id not found
[ 0.309038] [FOX] force vbus state true for m.2 module
[ 0.313477] coresight-stm 6002000.stm: coresight-stm : stm_register_device failed, probing deferred
[ 0.323925] coresight-dummy soc:dummy_sink: Dummy device initialized
[ 0.324112] coresight-dummy soc:dummy_source: Dummy device initialized
[ 0.324749] coresight-remote-etm soc:modem2_etm0: Remote ETM initialized
[ 0.325079] coresight-remote-etm soc:modem_etm0: Remote ETM initialized
[ 0.325495] coresight-csr 6001000.csr: CSR initialized: coresight-csr
[ 0.325698] coresight-csr 6b0f000.csr: CSR initialized: coresight-swao-csr
[ 0.327790] [logevent]: create netlink (28) socket ok
[ 0.328555] ipip: IPv4 and MPLS over IPv4 tunneling driver
[ 0.328991] gre: GRE over IPv4 demultiplexor driver
[ 0.328998] ip_gre: GRE over IPv4 tunneling driver
[ 0.330792] NET: Registered protocol family 10
[ 0.332170] Segment Routing with IPv6
[ 0.332377] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[ 0.333362] ip6_gre: GRE over IPv6 tunneling driver
[ 0.333803] NET: Registered protocol family 17
[ 0.333874] Bridge firewalling registered
[ 0.333947] 8021q: 802.1Q VLAN Support v1.8
[ 0.335199] Loading compiled-in X.509 certificates
[ 0.339599] Loaded X.509 cert 'Build time autogenerated kernel key: 10b7e3ecae62717005658514098a4724816f8a75'
[ 0.345188] Unable to find DT property: qcom,msm-imem-dload-type
[ 0.345218] Unable to map memory for DT property: dload_mode
[ 0.356392] pmx65_s5_level: supplied by pmx65_l19_level
[ 0.356870] pmx65_s5_level_ao: supplied by pmx65_l19_level_ao
[ 0.367112] gpio-regulator 17830000.rsc:vddpx2-gpio-regulator: GPIO lookup for consumer (null)
[ 0.367122] gpio-regulator 17830000.rsc:vddpx2-gpio-regulator: using device tree for GPIO lookup
[ 0.367144] of_get_named_gpiod_flags: parsed 'gpios' property of node '/soc/rsc@17830000/vddpx2-gpio-regulator[0]' - status (0)
[ 0.367178] gpio-regulator 17830000.rsc:vddpx2-gpio-regulator: GPIO lookup for consumer enable
[ 0.367182] gpio-regulator 17830000.rsc:vddpx2-gpio-regulator: using device tree for GPIO lookup
[ 0.367191] of_get_named_gpiod_flags: can't parse 'enable-gpios' property of node '/soc/rsc@17830000/vddpx2-gpio-regulator[0]'
[ 0.367204] of_get_named_gpiod_flags: parsed 'enable-gpio' property of node '/soc/rsc@17830000/vddpx2-gpio-regulator[0]' - status (0)
[ 0.367791] sd_vdd: supplied by vddpx_2
[ 0.370384] sps_register_bam_device: sps:BAM 0x06064000 is registered
[ 0.371652] coresight-stm 6002000.stm: STM32 initialized
[ 0.381795] gcc-sdxlemur 100000.clock-controller: Registered GCC clocks
[ 0.383312] sdxlemur-debugcc soc:qcom,cc-debug: Registered debug measure clocks
[ 0.396667] msm_serial 831000.serial: msm_serial: detected port #0
[ 0.396708] msm_serial 831000.serial: uartclk = 19200000
[ 0.396763] 831000.serial: ttyMSM0 at MMIO 0x831000 (irq = 26, base_baud = 1200000) is a MSM
[ 0.396780] msm_serial: console setup on port #0
[ 1.944576] printk: console [ttyMSM0] enabled
[ 1.950436] pcie-ep 40002000.qcom,pcie: 40002000.qcom,pcie supply vreg-cx not found, using dummy regulator
[ 1.954064] of_get_named_gpiod_flags: parsed 'perst-gpio' property of node '/soc/qcom,pcie@40002000[0]' - status (0)
[ 1.954081] of_get_named_gpiod_flags: parsed 'wake-gpio' property of node '/soc/qcom,pcie@40002000[0]' - status (0)
[ 1.954093] of_get_named_gpiod_flags: parsed 'clkreq-gpio' property of node '/soc/qcom,pcie@40002000[0]' - status (0)
[ 1.954104] of_get_named_gpiod_flags: can't parse 'mdm2apstatus-gpio' property of node '/soc/qcom,pcie@40002000[0]'
[ 1.954531] gpio gpiochip0: (f100000.pinctrl): allocate IRQ 97, hwirq 57
[ 1.962993] gpio gpiochip0: (f100000.pinctrl): found parent hwirq 52
[ 1.969803] gpio gpiochip0: (f100000.pinctrl): alloc_irqs_parent for 97 parent hwirq 52
[ 1.977150] ep_pcie_core_enable_endpoint: PCIe V1711211: link initialized by bootloader for LE PCIe endpoint; skip link training in HLOS.
[ 1.983982] ep_pcie_enumeration: PCIe V1711211: PCIe link training is successful with host side. Waiting for enumeration to complete
[ 2.002174] qcom-cpu-sdxlemur 17810008.clock-controller: No speed/PVS binning available. Defaulting to 0!
[ 2.008731] apcs_cpu_pll PLL is already enabled
[ 2.018160] Clock_cpu:(cpu 0) OPP voltage for 576000000: 128
[ 2.022202] Clock_cpu:(cpu 0) OPP voltage for 1804800000: 384
[ 2.028043] qcom-cpu-sdxlemur 17810008.clock-controller: CPU clock Driver probed successfully
[ 2.035160] arm-smmu 15000000.apps-smmu: non-coherent table walk
[ 2.042261] arm-smmu 15000000.apps-smmu: (IDR0.CTTW overridden by FW configuration)
[ 2.048272] arm-smmu 15000000.apps-smmu: stream matching with 57 register groups
[ 2.058812] qcom-sps-dma 804000.qcom,sps-dma: Adding to iommu group 0
[ 2.063661] qcom-sps-dma 804000.qcom,sps-dma: dma_async_device_register: device has no channels!
[ 2.070970] minidump-id not found for modem
[ 2.078920] subsys-pil-tz 4080000.qcom,mss: for modem segments only will be dumped.
[ 2.082843] subsys-pil-tz 4080000.qcom,mss: for md_modem segments only will be dumped.
[ 2.091073] minidump-id not found for ipa_fws
[ 2.098334] subsys-pil-tz soc:qcom,ipa_fws: for ipa_fws segments only will be dumped.
[ 2.102899] subsys-pil-tz soc:qcom,ipa_fws: for md_ipa_fws segments only will be dumped.
[ 2.111810] qseecom 90000000.qseecom: assigned reserved memory node qseecom_region
[ 2.118730] QSEECOM: qseecom_init_control: qseecom.qsee_version = 0x1402000
[ 2.126289] random: crng init done
[ 2.132946] QSEECOM: qseecom_retrieve_ce_data: Device does not support PFE/FDE
[ 2.136376] QSEECOM: qseecom_send_app_region: secure app region addr=0x90000000 size=0x500000
[ 2.145812] sps_phy2h: sps: BAM device 0x01b04000 is not registered yet
[ 2.152431] sps_register_bam_device: sps:BAM 0x01b04000 is registered
[ 2.158599] msm_nand_bam_init: msm_nand_bam_init: BAM device registered: bam_handle 0xb937f200
[ 2.165510] sps_bam_enable: sps:BAM 0x01b04000 (va:0x59609b6c) enabled: ver:0x19, number of pipes:9
[ 2.174267] msm_nand_version_check: nand_major:2, nand_minor:1, qpic_major:2, qpic_minor:1
[ 2.182843] msm_nand_parse_smem_ptable: Parsing partition table info from SMEM
[ 2.191217] msm_nand_parse_smem_ptable: SMEM partition table found: ver: 4 len: 41
[ 2.198226] msm_nand_version_check: nand_major:2, nand_minor:1, qpic_major:2, qpic_minor:1
[ 2.206014] msm_nand_flash_onfi_probe: Found an ONFI compliant device H27S4G8F2EKPB4
[ 2.213991] msm_nand_scan: NAND Id: 0x1680acad Buswidth: 8Bits Density: 512 MByte
[ 2.222233] msm_nand_scan: pagesize: 4096 Erasesize: 262144 oobsize: 256 (in Bytes)
[ 2.229862] msm_nand_scan: BCH ECC: 4 Bit
[ 2.237335] msm_nand_scan: CFG0: 0x2a0409c0, CFG1: 0x0804645c
[ 2.237335] RAWCFG0: 0x2c8401c0, RAWCFG1: 0x0005055d
[ 2.237335] ECCBUFCFG: 0x00000203, ECCBCHCFG: 0x42040700
[ 2.237335] RAWECCCFG: 0x42000701, BAD BLOCK BYTE: 0x00000191
[ 2.245494] Creating 41 MTD partitions on "1b00000.nand":
[ 2.267721] 0x000000000000-0x000000280000 : "sbl"
[ 2.280488] 0x000000280000-0x000000500000 : "mibib"
[ 2.281159] 0x000000500000-0x000001000000 : "efs2"
[ 2.290374] 0x000001000000-0x000001480000 : "manudata"
[ 2.291014] 0x000001480000-0x000001880000 : "foxdata"
[ 2.300463] 0x000001880000-0x000001a40000 : "tz"
[ 2.301106] 0x000001a40000-0x000001c00000 : "tzbak"
[ 2.310368] 0x000001c00000-0x000001d00000 : "tz_devcfg"
[ 2.311016] 0x000001d00000-0x000001e00000 : "tz_devcfgbak"
[ 2.320370] 0x000001e00000-0x000001f80000 : "ddr"
[ 2.321000] 0x000001f80000-0x000002080000 : "apdp"
[ 2.330369] 0x000002080000-0x000002180000 : "xbl_config"
[ 2.331032] 0x000002180000-0x000002280000 : "xbl_configbak"
[ 2.340379] 0x000002280000-0x000002380000 : "xbl_ramdump"
[ 2.341023] 0x000002380000-0x000002480000 : "xbl_ramdumpbak"
[ 2.350374] 0x000002480000-0x000002580000 : "multi_image"
[ 2.352057] 0x000002580000-0x000002680000 : "multi_imagebak"
[ 2.370365] 0x000002680000-0x000002780000 : "multi_image_qti"
[ 2.371021] 0x000002780000-0x000002880000 : "aop"
[ 2.380386] 0x000002880000-0x000002980000 : "aopbak"
[ 2.381028] 0x000002980000-0x000002a80000 : "qhee"
[ 2.390463] 0x000002a80000-0x000002b80000 : "qheebak"
[ 2.391124] 0x000002b80000-0x000002c80000 : "abl"
[ 2.400368] 0x000002c80000-0x000002d80000 : "ablbak"
[ 2.401037] 0x000002d80000-0x000003000000 : "uefi"
[ 2.410476] 0x000003000000-0x000003280000 : "uefibak"
[ 2.411117] 0x000003280000-0x000003400000 : "loader_sti"
[ 2.420530] 0x000003400000-0x000003f80000 : "boot"
[ 2.421205] 0x000003f80000-0x000004080000 : "scrub"
[ 2.430395] 0x000004080000-0x00000abc0000 : "modem"
[ 2.431063] 0x00000abc0000-0x00000ad80000 : "misc"
[ 2.440374] 0x00000ad80000-0x00000af00000 : "devinfo"
[ 2.441011] 0x00000af00000-0x00000ba80000 : "recovery"
[ 2.450376] 0x00000ba80000-0x000014b80000 : "foxusr"
[ 2.451033] 0x000014b80000-0x000017b80000 : "recoveryfs"
[ 2.460377] 0x000017b80000-0x000017c80000 : "sec"
[ 2.461056] 0x000017c80000-0x000017d80000 : "vendor"
[ 2.470377] 0x000017d80000-0x000017e80000 : "fwinfo"
[ 2.471022] 0x000017e80000-0x000017f80000 : "ipa_fw"
[ 2.480387] 0x000017f80000-0x000018080000 : "usb_qti"
[ 2.481031] 0x000018080000-0x000020000000 : "system"
[ 2.490370] msm_nand_probe: NANDc phys addr 0x1b00000, BAM phys addr 0x1b04000, BAM IRQ 28
[ 2.490399] msm_nand_probe: Allocated DMA buffer at virt_addr 0x8bcda3e6, phys_addr 0x8b4c2000
[ 2.497515] msm_nand_probe: Host capabilities:0x00000001
[ 2.506828] qce 1de0000.qcedev: Adding to iommu group 1
[ 2.512291] QCE50: __qce_get_device_tree_data: CE operating frequency is not defined, setting to default 100MHZ
[ 2.516831] qce 1de0000.qcedev: QTI Crypto 5.6.0 device found @0x1de0000
[ 2.526964] sps_register_bam_device: sps:BAM 0x01dc4000 is registered
[ 2.533962] sps_bam_enable: sps:BAM 0x01dc4000 (va:0x96234ff0) enabled: ver:0x27, number of pipes:16
[ 2.540106] QCE50: qce_sps_init: QTI MSM CE-BAM at 0x0000000001dc4000 irq 38
[ 2.549981] qcrypto 1de0000.qcrypto: Adding to iommu group 2
[ 2.556393] QCE50: __qce_get_device_tree_data: CE operating frequency is not defined, setting to default 100MHZ
[ 2.562158] qcrypto 1de0000.qcrypto: QTI Crypto 5.6.0 device found @0x1de0000
[ 2.571768] sps_bam_pipe_connect: sps:BAM 0x01dc4000 pipe 5 sharing violation
[ 2.578941] sps_rm_state_change: sps:Failed to connect BAM 0x760445e6 pipe 5
[ 2.586081] QCE50: qce_sps_init_ep_conn: sps_connect() fail pipe_handle=0xb8a59a00, rc = -1
[ 2.593220] sps_client_de_init: sps:De-init client in connected state: 0x1535053
[ 2.601892] i2c-msm-v2 837000.i2c: Adding to iommu group 0
[ 2.610170] ipa 3e00000.qcom,ipa:ipa_smmu_ap: Adding to iommu group 3
[ 2.614608] ipa 3e00000.qcom,ipa:ipa_smmu_wlan: Adding to iommu group 4
[ 2.621220] ipa 3e00000.qcom,ipa:ipa_smmu_uc: Adding to iommu group 5
[ 2.627866] ipa 3e00000.qcom,ipa:ipa_smmu_eth: Adding to iommu group 6
[ 2.634253] ipa 3e00000.qcom,ipa:ipa_smmu_eth1: Adding to iommu group 7
[ 2.640678] ipa 3e00000.qcom,ipa:ipa_smmu_wlan1: Adding to iommu group 8
[ 2.646895] ipa ipa_smmu_update_fw_loader:11162 Using XBL boot load for IPA FW
[ 2.653793] ipa ipa_smmu_11ad_cb_probe:10993 11AD SMMU is disabled
[ 2.655620] gsi soc:qcom,msm_gsi: gsi_register_device:1554 GSI irq is wake enabled 36
[ 2.670496] ipa ipa3_setup_tput_pipe:1321 Invalid client.
[ 2.674686] ipa ipa3_post_init:7886 :Failed configuring throughput moniter ep
[ 2.680860] rmnet_ipa3 started initialization
[ 2.687184] IPA SSR support = True
[ 2.691555] IPA driver is now in ready state
[ 2.694849] IPA SG support = False
[ 2.699244] IPA Napi Enable = False
[ 2.702472] using default for wan-rx-desc-size = 256
[ 2.706238] ipa-lnx-stats ipa_spearhead_stats_ioctl_init:1915 IPA ipa_lnx_stats_ioctl major(502) initial ok :>>>>
[ 2.711710] ipa-wan ipa3_wwan_register_netdev_pm_client:3476 rmnet_ipa%d register done
[ 2.721255] ipa-lnx-stats ipa_spearhead_stats_init:1943 IPA_LNX_STATS_IOCTL init success
[ 2.729029] IPA driver initialization was successful.
[ 2.737822] ipa-wan ipa3_wwan_probe:3671 rmnet_ipa completed initialization
[ 2.743925] msm-dwc3 a600000.ssusb: Adding to iommu group 9
[ 2.750531] dwc3 a600000.dwc3: changing max_speed on rev 00000000
[ 2.758303] usb_bam_init: setting SPS_BAM_SMMU_EN flag with (a704000.qcom,usbbam)
[ 2.761206] sps_register_bam_device: sps:BAM 0x0a704000 is registered
[ 2.768714] msm-dwc3 a600000.ssusb: Nominal values not found.
[ 2.774749] msm-dwc3 a600000.ssusb: Dynamic voting failed
[ 2.780508] msm-dwc3 a600000.ssusb: IRQ hs_phy_irq not found
[ 2.786202] msm-dwc3 a600000.ssusb: IRQ dp_hs_phy_irq1 not found
[ 2.791570] msm-dwc3 a600000.ssusb: IRQ dm_hs_phy_irq1 not found
[ 2.797526] msm-dwc3 a600000.ssusb: IRQ ss_phy_irq1 not found
[ 2.803650] msm-dwc3 a600000.ssusb: Could not get usb psy
[ 2.809654] ubi0: attaching mtd40
[ 2.850180] msm-dwc3 a600000.ssusb: DWC3 exited from low power mode
[ 2.850663] msm-dwc3 a600000.ssusb: DWC3 in low power mode
[ 2.860089] msm-dwc3 a600000.ssusb: Could not get usb psy
[ 2.900171] msm-dwc3 a600000.ssusb: DWC3 exited from low power mode
[ 3.070783] ubi0: scanning is finished
[ 3.076944] ubi0: attached mtd40 (name "system", size 127 MiB)
[ 3.076966] ubi0: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes
[ 3.081693] ubi0: min./max. I/O unit sizes: 4096/4096, sub-page size 4096
[ 3.088514] ubi0: VID header offset: 4096 (aligned 4096), data offset: 8192
[ 3.095465] ubi0: good PEBs: 510, bad PEBs: 0, corrupted PEBs: 0
[ 3.102328] ubi0: user volume: 5, internal volumes: 1, max. volumes count: 128
[ 3.108424] ubi0: max/mean erase counter: 6/1, WL threshold: 4096, image sequence number: 50462085
[ 3.115439] ubi0: available PEBs: 0, total reserved PEBs: 510, PEBs reserved for bad PEB handling: 40
[ 3.124381] ubi0: background thread "ubi_bgt0d" started, PID 105
[ 3.135957] RNDIS_IPA module is loaded.
[ 3.139727] ecm driver init
[ 3.143503] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[ 3.147196] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[ 3.154219] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[ 3.160703] gcc-sdxlemur 100000.clock-controller: sync-state
[ 3.169062] ALSA device list:
[ 3.174854] cfg80211: failed to load regulatory.db
[ 3.177706] No soundcards found.
[ 3.183507] UBIFS (ubi0:0): Mounting in unauthenticated mode
[ 3.281758] UBIFS (ubi0:0): UBIFS: mounted UBI device 0, volume 0, name "rootfs", R/O mode
[ 3.281786] UBIFS (ubi0:0): LEB size: 253952 bytes (248 KiB), min./max. I/O unit sizes: 4096 bytes/4096 bytes
[ 3.288909] UBIFS (ubi0:0): FS size: 86597632 bytes (82 MiB, 341 LEBs), journal size 9404416 bytes (8 MiB, 38 LEBs)
[ 3.299019] UBIFS (ubi0:0): reserved for root: 0 bytes (0 KiB)
[ 3.309319] UBIFS (ubi0:0): media format: w4/r0 (latest is w5/r0), UUID 89A62DA8-2374-477F-889D-DFB29569AB48, small LPT model
[ 3.317606] VFS: Mounted root (ubifs filesystem) readonly on device 0:18.
[ 3.329048] devtmpfs: mounted
[ 3.334290] Freeing unused kernel memory: 1024K
[ 3.337430] Run /sbin/init as init process
[ 3.689593] audit: type=1404 audit(34.879:2): enforcing=1 old_enforcing=0 auid=4294967295 ses=4294967295 enabled=1 old-enabled=1 lsm=selinux res=1
[ 3.847462] SELinux: Permission watch in class filesystem not defined in policy.
[ 3.847506] SELinux: Permission watch in class file not defined in policy.
[ 3.853967] SELinux: Permission watch_mount in class file not defined in policy.
[ 3.860814] SELinux: Permission watch_sb in class file not defined in policy.
[ 3.868512] SELinux: Permission watch_with_perm in class file not defined in policy.
[ 3.875547] SELinux: Permission watch_reads in class file not defined in policy.
[ 3.883521] SELinux: Permission watch in class dir not defined in policy.
[ 3.890839] SELinux: Permission watch_mount in class dir not defined in policy.
[ 3.897581] SELinux: Permission watch_sb in class dir not defined in policy.
[ 3.905178] SELinux: Permission watch_with_perm in class dir not defined in policy.
[ 3.912176] SELinux: Permission watch_reads in class dir not defined in policy.
[ 3.919991] SELinux: Permission watch in class lnk_file not defined in policy.
[ 3.927363] SELinux: Permission watch_mount in class lnk_file not defined in policy.
[ 3.934392] SELinux: Permission watch_sb in class lnk_file not defined in policy.
[ 3.942379] SELinux: Permission watch_with_perm in class lnk_file not defined in policy.
[ 3.949838] SELinux: Permission watch_reads in class lnk_file not defined in policy.
[ 3.958097] SELinux: Permission watch in class chr_file not defined in policy.
[ 3.965903] SELinux: Permission watch_mount in class chr_file not defined in policy.
[ 3.973021] SELinux: Permission watch_sb in class chr_file not defined in policy.
[ 3.981066] SELinux: Permission watch_with_perm in class chr_file not defined in policy.
[ 3.988619] SELinux: Permission watch_reads in class chr_file not defined in policy.
[ 3.996748] SELinux: Permission watch in class blk_file not defined in policy.
[ 4.004585] SELinux: Permission watch_mount in class blk_file not defined in policy.
[ 4.011820] SELinux: Permission watch_sb in class blk_file not defined in policy.
[ 4.019652] SELinux: Permission watch_with_perm in class blk_file not defined in policy.
[ 4.027105] SELinux: Permission watch_reads in class blk_file not defined in policy.
[ 4.035519] SELinux: Permission watch in class sock_file not defined in policy.
[ 4.043169] SELinux: Permission watch_mount in class sock_file not defined in policy.
[ 4.050627] SELinux: Permission watch_sb in class sock_file not defined in policy.
[ 4.058345] SELinux: Permission watch_with_perm in class sock_file not defined in policy.
[ 4.065905] SELinux: Permission watch_reads in class sock_file not defined in policy.
[ 4.074244] SELinux: Permission watch in class fifo_file not defined in policy.
[ 4.082136] SELinux: Permission watch_mount in class fifo_file not defined in policy.
[ 4.089682] SELinux: Permission watch_sb in class fifo_file not defined in policy.
[ 4.097413] SELinux: Permission watch_with_perm in class fifo_file not defined in policy.
[ 4.105029] SELinux: Permission watch_reads in class fifo_file not defined in policy.
[ 4.113554] SELinux: Permission nlmsg_readpriv in class netlink_route_socket not defined in policy.
[ 4.121301] SELinux: Permission nlmsg_getneigh in class netlink_route_socket not defined in policy.
[ 4.130994] SELinux: Class perf_event not defined in policy.
[ 4.139593] SELinux: the above unknown classes and permissions will be allowed
[ 4.145881] SELinux: policy capability network_peer_controls=1
[ 4.152368] SELinux: policy capability open_perms=1
[ 4.158167] SELinux: policy capability extended_socket_class=1
[ 4.163384] SELinux: policy capability always_check_network=0
[ 4.169018] SELinux: policy capability cgroup_seclabel=1
[ 4.174928] SELinux: policy capability nnp_nosuid_transition=1
[ 4.306794] audit: type=1403 audit(35.499:3): auid=4294967295 ses=4294967295 lsm=selinux res=1
[ 4.320197] systemd[1]: Successfully loaded SELinux policy in 642.068ms.
[ 4.576471] systemd[1]: Relabelled /dev, /dev/shm, /run, /sys/fs/cgroup in 140.878ms.
[ 6.279763] UBIFS (ubi0:3): Mounting in unauthenticated mode
[ 6.285459] UBIFS (ubi0:1): Mounting in unauthenticated mode
[ 6.334292] UBIFS (ubi0:3): recovery needed
[ 6.463190] UBIFS (ubi0:3): recovery completed
[ 6.463341] UBIFS (ubi0:3): UBIFS: mounted UBI device 0, volume 3, name "systemrw"
[ 6.466521] UBIFS (ubi0:3): LEB size: 253952 bytes (248 KiB), min./max. I/O unit sizes: 4096 bytes/4096 bytes
[ 6.475504] UBIFS (ubi0:3): FS size: 4063232 bytes (3 MiB, 16 LEBs), journal size 1777665 bytes (1 MiB, 5 LEBs)
[ 6.484099] UBIFS (ubi0:3): reserved for root: 191915 bytes (187 KiB)
[ 6.493962] UBIFS (ubi0:3): media format: w5/r0 (latest is w5/r0), UUID BA64ABE7-53C1-46EE-8944-2769667D23D7, small LPT model
[ 6.500592] UBIFS (ubi0:3): background thread "ubifs_bgt0_3" started, PID 111
[ 6.517420] UBIFS (ubi0:1): background thread "ubifs_bgt0_1" started, PID 112
[ 6.557147] UBIFS (ubi0:4): Mounting in unauthenticated mode
[ 6.560205] UBIFS (ubi0:4): background thread "ubifs_bgt0_4" started, PID 114
[ 6.795107] rmnet:start/load
[ 6.811275] UBIFS (ubi0:1): recovery needed
[ 7.436014] UBIFS (ubi0:4): recovery needed
[ 7.692098] systemd-sysctl[118]: Couldn't write 'fq_codel' to 'net/core/default_qdisc', ignoring: No such file or directory
[ 7.723904] rmnet_core: loading out-of-tree module taints kernel.
[ 7.731971] ipa ipa3_register_rmnet_ll_cb:294 low lat data pipes are not supported
[ 7.731983] rmnet_ll_ipa_ready(): Registering IPA LL callback failed with rc -6
[ 7.739171] done loading rmnet core modules
[ 7.791708] zram0: detected capacity change from 0 to 95637504
[ 7.983557] ubi1: attaching mtd29
[ 8.204292] ubi1: scanning is finished
[ 8.209483] ubi1 warning: ubi_eba_init: cannot reserve enough PEBs for bad PEB handling, reserved 12, need 40
[ 8.220161] ubi1: attached mtd29 (name "modem", size 107 MiB)
[ 8.220185] ubi1: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes
[ 8.224875] ubi1: min./max. I/O unit sizes: 4096/4096, sub-page size 4096
[ 8.231671] ubi1: VID header offset: 4096 (aligned 4096), data offset: 8192
[ 8.238504] ubi1: good PEBs: 429, bad PEBs: 0, corrupted PEBs: 0
[ 8.245285] ubi1: user volume: 1, internal volumes: 1, max. volumes count: 128
[ 8.251536] ubi1: max/mean erase counter: 4/0, WL threshold: 4096, image sequence number: 1868093409
[ 8.258559] ubi1: available PEBs: 0, total reserved PEBs: 429, PEBs reserved for bad PEB handling: 12
[ 8.267899] ubi1: background thread "ubi_bgt1d" started, PID 148
[ 8.433371] UBIFS (ubi1:0): Mounting in unauthenticated mode
[ 8.474942] UBIFS (ubi1:0): background thread "ubifs_bgt1_0" started, PID 152
[ 8.492172] Adding 93392k swap on /dev/zram0. Priority:10 extents:1 across:93392k SS
[ 8.559693] UBIFS (ubi1:0): recovery needed
[ 8.717444] UBIFS (ubi1:0): recovery completed
[ 8.717570] UBIFS (ubi1:0): UBIFS: mounted UBI device 1, volume 0, name "modem"
[ 8.723992] UBIFS (ubi1:0): LEB size: 253952 bytes (248 KiB), min./max. I/O unit sizes: 4096 bytes/4096 bytes
[ 8.727984] UBIFS (ubi1:0): FS size: 102342656 bytes (97 MiB, 403 LEBs), journal size 9404416 bytes (8 MiB, 38 LEBs)
[ 8.740041] UBIFS (ubi1:0): reserved for root: 0 bytes (0 KiB)
[ 8.748638] UBIFS (ubi1:0): media format: w4/r0 (latest is w5/r0), UUID 290D6347-E757-426E-8662-559143EDFF2F, small LPT model
[ 8.984592] systemd-tmpfiles[146]: /etc/tmpfiles.d/platform.conf:38: Line references path below legacy directory /var/run/, updating /var/run/resolv.conf → /run/resolv.conf; please update the tmpfiles.d/ drop-in file accordingly.
[ 9.001982] UBIFS (ubi0:1): recovery completed
[ 9.003994] UBIFS (ubi0:1): UBIFS: mounted UBI device 0, volume 1, name "usrfs"
[ 9.008409] UBIFS (ubi0:1): LEB size: 253952 bytes (248 KiB), min./max. I/O unit sizes: 4096 bytes/4096 bytes
[ 9.060197] UBIFS (ubi0:1): FS size: 11681792 bytes (11 MiB, 46 LEBs), journal size 9404416 bytes (8 MiB, 38 LEBs)
[ 9.060226] UBIFS (ubi0:1): reserved for root: 0 bytes (0 KiB)
[ 9.069427] UBIFS (ubi0:1): media format: w4/r0 (latest is w5/r0), UUID 3F3925A9-84FE-49FB-B486-B267FEBAE204, small LPT model
[ 9.230229] UBIFS (ubi0:4): recovery completed
[ 9.230359] UBIFS (ubi0:4): UBIFS: mounted UBI device 0, volume 4, name "persist"
[ 9.233559] UBIFS (ubi0:4): LEB size: 253952 bytes (248 KiB), min./max. I/O unit sizes: 4096 bytes/4096 bytes
[ 9.293849] UBIFS (ubi0:4): FS size: 4063232 bytes (3 MiB, 16 LEBs), journal size 1777665 bytes (1 MiB, 5 LEBs)
[ 9.293878] UBIFS (ubi0:4): reserved for root: 191915 bytes (187 KiB)
[ 9.352492] UBIFS (ubi0:4): media format: w5/r0 (latest is w5/r0), UUID 03FABB9D-ACD8-4485-8E9F-C3A7D217FF0B, small LPT model
[ 9.363265] IPA is loading with MHI configuration
[ 9.456498] ubi2: attaching mtd33
[ 9.671585] start_pcie: PCIe support enabled
[ 9.750096] ADC channel pmx65_ambient_therm EOC took 21 ms
[ 9.762485] start_pcie: setting usb composition to none for SDXLEMUR-LITE on PCIe mode
[ 9.762536] start_pcie: Debug transport mode is set to pcie. Update /data/debug_transport.conf to usb and reboot to switch
[ 10.225096] systemd-udevd[177]: Network interface NamePolicy= disabled on kernel command line, ignoring.
[ 10.497557] audit: type=1400 audit(41.119:4): avc: granted { module_request } for pid=228 comm="mkdir" kmod="usbfunc:acm" scontext=system_u:system_r:usb_t:s0-s15:c0.c1023 tcontext=system_u:system_r:kernel_t:s15:c0.c1023 tclass=system
[ 10.531175] Mass Storage Function, version: 2009/09/11
[ 10.531202] LUN: removable file: (no medium)
[ 10.539512] Mass Storage Function, version: 2009/09/11
[ 10.539638] LUN: removable file: (no medium)
[ 10.548976] file system registered
[ 10.555862] systemd-udevd[177]: /lib/udev/rules.d/50-udev-default.rules:39 Unknown group 'render', ignoring
[ 10.556040] systemd-udevd[177]: /lib/udev/rules.d/50-udev-default.rules:40 Unknown group 'render', ignoring
[ 10.593687] f_cdev_alloc: port_name:at_usb0 (00000000) portno:(0)
[ 10.598528] f_cdev_alloc: port_name:at_usb1 (00000000) portno:(1)
[ 10.607884] audit: type=1400 audit(41.229:5): avc: granted { module_request } for pid=240 comm="mkdir" kmod="usbfunc:rmnet_bam" scontext=system_u:system_r:usb_t:s0-s15:c0.c1023 tcontext=system_u:system_r:kernel_t:s15:c0.c1023 tclass=system
[ 10.710829] gsi_set_inst_name: prot_id = 2, prev inst do not freed yet
[ 10.754248] audit: type=1400 audit(41.379:6): avc: granted { module_request } for pid=254 comm="mkdir" kmod="usbfunc:ncm" scontext=system_u:system_r:usb_t:s0-s15:c0.c1023 tcontext=system_u:system_r:kernel_t:s15:c0.c1023 tclass=system
[ 10.812732] ubi2: scanning is finished
[ 10.824001] audit: type=1400 audit(41.449:7): avc: granted { module_request } for pid=262 comm="mkdir" kmod="usbfunc:uvc" scontext=system_u:system_r:usb_t:s0-s15:c0.c1023 tcontext=system_u:system_r:kernel_t:s15:c0.c1023 tclass=system
[ 10.837299] audit: type=1400 audit(41.459:8): avc: granted { module_request } for pid=264 comm="mkdir" kmod="usbfunc:rndis" scontext=system_u:system_r:usb_t:s0-s15:c0.c1023 tcontext=system_u:system_r:kernel_t:s15:c0.c1023 tclass=system
[ 10.857571] systemd-udevd[177]: Configuration file /etc/udev/rules.d/automountsdcard.rules is marked executable. Please remove executable permission bits. Proceeding anyway.
[ 10.868096] ubi2: attached mtd33 (name "foxusr", size 145 MiB)
[ 10.884876] audit: type=1400 audit(41.509:9): avc: granted { module_request } for pid=267 comm="mkdir" kmod="usbfunc:ipc" scontext=system_u:system_r:usb_t:s0-s15:c0.c1023 tcontext=system_u:system_r:kernel_t:s15:c0.c1023 tclass=system
[ 10.903037] audit: type=1400 audit(41.529:10): avc: granted { module_request } for pid=269 comm="mkdir" kmod="usbfunc:ecm" scontext=system_u:system_r:usb_t:s0-s15:c0.c1023 tcontext=system_u:system_r:kernel_t:s15:c0.c1023 tclass=system
[ 10.916797] ubi2: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes
[ 10.990268] ubi2: min./max. I/O unit sizes: 4096/4096, sub-page size 4096
[ 10.990293] ubi2: VID header offset: 4096 (aligned 4096), data offset: 8192
[ 11.000309] systemd-udevd[177]: Configuration file /etc/udev/rules.d/ipacm.rules is marked executable. Please remove executable permission bits. Proceeding anyway.
[ 11.009180] audit: type=1400 audit(41.629:11): avc: denied { map } for pid=277 comm="mount" path="/etc/passwd" dev="ubifs" ino=532 scontext=system_u:system_r:mount_t:s0-s15:c0.c1023 tcontext=system_u:object_r:etc_t:s0 tclass=file permissive=0
[ 11.017587] systemd-udevd[177]: Configuration file /etc/udev/rules.d/ipacm.rules is marked world-writable. Please remove world writability permission bits. Proceeding anyway.
[ 11.059437] ubi2: good PEBs: 580, bad PEBs: 0, corrupted PEBs: 0
[ 11.059460] ubi2: user volume: 1, internal volumes: 1, max. volumes count: 128
[ 11.064604] audit: type=1400 audit(41.669:12): avc: denied { map } for pid=277 comm="mount" path="/etc/group" dev="ubifs" ino=158 scontext=system_u:system_r:mount_t:s0-s15:c0.c1023 tcontext=system_u:object_r:etc_t:s0 tclass=file permissive=0
[ 11.071686] ubi2: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 3066373033
[ 11.140774] start_usb: PCIE Mode
[ 11.144461] msm-dwc3 a600000.ssusb: DWC3 in low power mode
[ 11.144511] msm-dwc3 a600000.ssusb: Could not get usb psy
[ 11.148851] msm-dwc3 a600000.ssusb: Could not get usb psy
[ 11.172600] systemd-udevd[177]: Configuration file /etc/udev/rules.d/mbim_udev_rules.rules is marked executable. Please remove executable permission bits. Proceeding anyway.
[ 11.172653] systemd-udevd[177]: Configuration file /etc/udev/rules.d/mbim_udev_rules.rules is marked world-writable. Please remove world writability permission bits. Proceeding anyway.
[ 11.210451] ubi2: available PEBs: 0, total reserved PEBs: 580, PEBs reserved for bad PEB handling: 10
[ 11.213810] ubi2: background thread "ubi_bgt2d" started, PID 266
[ 11.245706] systemd-udevd[177]: Configuration file /etc/udev/rules.d/mountpartitions.rules is marked executable. Please remove executable permission bits. Proceeding anyway.
[ 11.362500] read descriptors
[ 11.362588] read strings
[ 11.371484] Launch adb is starting adbd...
[ 11.410717] UBIFS (ubi2:0): Mounting in unauthenticated mode
[ 11.460223] UBIFS (ubi2:0): background thread "ubifs_bgt2_0" started, PID 306
[ 11.791424] UBIFS (ubi2:0): recovery needed
[ 11.932247] UBIFS (ubi2:0): recovery completed
[ 11.932375] UBIFS (ubi2:0): UBIFS: mounted UBI device 2, volume 0, name "fox_vol"
[ 11.935576] UBIFS (ubi2:0): LEB size: 253952 bytes (248 KiB), min./max. I/O unit sizes: 4096 bytes/4096 bytes
[ 11.943154] UBIFS (ubi2:0): FS size: 141197312 bytes (134 MiB, 556 LEBs), journal size 9404416 bytes (8 MiB, 38 LEBs)
[ 11.953085] UBIFS (ubi2:0): reserved for root: 0 bytes (0 KiB)
[ 11.963628] UBIFS (ubi2:0): media format: w4/r0 (latest is w5/r0), UUID 1EB98330-A0CC-4E55-8F2F-8AC226586567, small LPT model
[ 12.028433] UBIFS (ubi2:0): un-mount UBI device 2
[ 12.028466] UBIFS (ubi2:0): background thread "ubifs_bgt2_0" stops
[ 12.037054] kathy:mount as rw
[ 12.061092] UBIFS (ubi2:0): Mounting in unauthenticated mode
[ 12.070099] UBIFS (ubi2:0): background thread "ubifs_bgt2_0" started, PID 331
[ 12.185104] UBIFS (ubi2:0): UBIFS: mounted UBI device 2, volume 0, name "fox_vol"
[ 12.185132] UBIFS (ubi2:0): LEB size: 253952 bytes (248 KiB), min./max. I/O unit sizes: 4096 bytes/4096 bytes
[ 12.191598] UBIFS (ubi2:0): FS size: 141197312 bytes (134 MiB, 556 LEBs), journal size 9404416 bytes (8 MiB, 38 LEBs)
[ 12.201467] UBIFS (ubi2:0): reserved for root: 0 bytes (0 KiB)
[ 12.212050] UBIFS (ubi2:0): media format: w4/r0 (latest is w5/r0), UUID 1EB98330-A0CC-4E55-8F2F-8AC226586567, small LPT model
[ 12.236278] audit: type=1400 audit(42.859:13): avc: denied { getattr } for pid=333 comm="chmod" path="/foxusr/fxfota/anti_rollback_enable" dev="ubifs" ino=87 scontext=system_u:system_r:initrc_t:s0-s15:c0.c1023 tcontext=system_u:object_r:atfwd_data_t:s0 tclass=file permissive=0
[ 12.312587] systemd-tmpfiles[335]: /etc/tmpfiles.d/platform.conf:38: Line references path below legacy directory /var/run/, updating /var/run/resolv.conf → /run/resolv.conf; please update the tmpfiles.d/ drop-in file accordingly.
[ 12.416702] systemd-tmpfiles[335]: symlink(/etc/machine-id, /var/lib/dbus/machine-id) failed: Read-only file system
[ 12.451771] systemd-tmpfiles[335]: Failed to open directory 'coredump': No such file or directory
[ 12.452657] systemd-tmpfiles[335]: Failed to open directory 'private': No such file or directory
[ 12.463884] systemd-tmpfiles[335]: Failed to open directory 'private': No such file or directory
[ 13.105576] Config c/1 of g1 needs at least one function.
[ 13.105616] udc a600000.dwc3: failed to start g1: -22
[ 13.120521] Started adbd.
[ 13.236655] subsys-restart: __subsystem_get(): Changing subsys fw_name to modem
[ 13.238261] ipa-wan ipa3_lcl_mdm_ssr_notifier_cb:4016 IPA received MPSS BEFORE_POWERUP
[ 13.266408] ipa-wan ipa3_lcl_mdm_ssr_notifier_cb:4025 IPA BEFORE_POWERUP handling is complete
[ 13.309653] subsys-pil-tz 4080000.qcom,mss: modem: loading from 0x90800000 to 0xa0000000
[ 13.600778] ADC channel pmx65_ambient_therm EOC took 71 ms
[ 13.750969] ADC channel pmx65_mdm_case_therm EOC took 61 ms
[ 13.920123] ADC channel pmx65_ambient_therm EOC took 31 ms
[ 14.700138] ADC channel pmx65_ambient_therm EOC took 21 ms
[ 15.140929] ADC channel pmx65_ambient_therm EOC took 31 ms
[ 15.540103] ADC channel pmx65_ambient_therm EOC took 31 ms
[ 15.820475] [0x0 mhi_dev_resume_mmio_mhi_init] Registering with IPA
[ 16.840542] logd.auditd: start
[ 16.975912] session id:0x0 state:2
[ 16.975934] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_M0_STATE
[ 16.978215] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_M0_STATE event, current states: READY & D0_STATE
[ 17.080299] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 17.090223] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 17.110675] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 17.111993] [mhi_uci_chan_state_notify] Invalid ch_id:100
[ 17.117065] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 17.123954] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 17.140427] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 17.141694] [mhi_uci_chan_state_notify] Invalid ch_id:101
[ 17.955741] logd.klogd: 17955657440
[ 19.640099] session id:0x0 state:5
[ 19.640122] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_M3_STATE
[ 19.642403] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_M3_STATE event, current states: M0 & D0_STATE
[ 19.750890] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 19.760499] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 19.761729] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 19.767778] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 19.775048] ipa_dma ipa3_dma_disable:491 There is pending work, can't disable.
[ 19.777891] [0x0 mhi_sm_prepare_suspend] IPA disable fail cnt:0
[ 19.820076] [0x0 mhi_sm_prepare_suspend] IPA DMA successfully disabled
[ 19.820129] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D3_HOT_EVENT event, current states: M3 and D0_STATE
[ 22.202994] qbi:MBIM Process Started
[ 22.314523] qbi: Wakelock support is enabled
[ 22.380665] subsys-pil-tz 4080000.qcom,mss: modem: Brought out of reset
[ 22.384039] subsys-pil-tz: subsys_powerup(): pil_boot is successful from modem and waiting for error ready
[ 22.392933] subsys-pil-tz 4080000.qcom,mss: modem: Power/Clock ready interrupt received
[ 22.400257] subsys-pil-tz: subsys_err_ready_intr_handler(): Subsystem error monitoring/handling services are up frommodem
[ 22.420719] ipa-wan ipa3_lcl_mdm_ssr_notifier_cb:4035 IPA received MPSS AFTER_POWERUP
[ 22.420748] ipa ipa3_odl_pipe_open:371 adpl pipe not configured
[ 22.427515] ipa-wan ipa3_lcl_mdm_ssr_notifier_cb:4040 IPA AFTER_POWERUP handling is complete
[ 22.436947] qcom_smd_qrtr_probe:Entered
[ 22.444958] qcom_smd_qrtr_probe:SMD QRTR driver probed
[ 22.445573] qrtr: Modem QMI Readiness RX cmd:0x2 node[0x3]
[ 22.450830] qrtr: Modem QMI Readiness TX cmd:0x2 node[0x2]
[ 22.472257] sysmon-qmi: ssctl_new_server: Connection established between QMI handle and modem's SSCTL service
[ 22.508571] gpio gpiochip2: (c440000.qcom,spmi:qcom,pmx65@1:pinctrl@8800): allocate IRQ 107, hwirq 10
[ 22.508601] gpio gpiochip2: (c440000.qcom,spmi:qcom,pmx65@1:pinctrl@8800): found parent hwirq 146
[ 22.520758] coresight-remote-etm soc:modem2_etm0: Connection established between QMI handle and 11 service
[ 22.525663] coresight-remote-etm soc:modem_etm0: Connection established between QMI handle and 2 service
[ 22.610129] gpio gpiochip2: (c440000.qcom,spmi:qcom,pmx65@1:pinctrl@8800): alloc_irqs_parent for 107 parent hwirq 146
[ 22.624629] gpio gpiochip2: (c440000.qcom,spmi:qcom,pmx65@1:pinctrl@8800): allocate IRQ 108, hwirq 8
[ 22.624659] gpio gpiochip2: (c440000.qcom,spmi:qcom,pmx65@1:pinctrl@8800): found parent hwirq 144
[ 22.660486] gpio gpiochip2: (c440000.qcom,spmi:qcom,pmx65@1:pinctrl@8800): alloc_irqs_parent for 108 parent hwirq 144
[ 22.662204] gpio gpiochip2: (c440000.qcom,spmi:qcom,pmx65@1:pinctrl@8800): allocate IRQ 109, hwirq 14
[ 22.672960] gpio gpiochip2: (c440000.qcom,spmi:qcom,pmx65@1:pinctrl@8800): found parent hwirq 150
[ 22.690130] gpio gpiochip2: (c440000.qcom,spmi:qcom,pmx65@1:pinctrl@8800): alloc_irqs_parent for 109 parent hwirq 150
[ 23.281788] Sending QMI_IPA_INIT_MODEM_DRIVER_REQ_V01
[ 23.296405] ipa ipa3_uc_wdi_event_log_info_handler:371 WDI protocol missing 0x1
[ 23.296434] ipa ipa3_uc_ntn_event_log_info_handler:19 NTN protocol missing 0x1
[ 23.304604] QMI_IPA_INIT_MODEM_DRIVER_REQ_V01 response received
[ 24.741962] ipa ipa3_set_aggr_limit:4813 get close-by 8192
[ 24.741986] ipa ipa3_set_aggr_limit:4815 set default rx_buff_sz 7808
[ 24.775364] ipa-wan ipa3_wwan_ioctl:2893 dev(rmnet_data10) register to IPA
[ 27.759836] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D0_EVENT event, current states: M3 and D3_HOT_STATE
[ 27.771663] session id:0x0 state:2
[ 27.771681] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_M0_STATE
[ 27.773960] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_M0_STATE event, current states: M3 & D0_STATE
[ 27.781693] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 27.793092] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 29.390866] type=1400 audit(315964805.849:14): avc: denied { search } for pid=486 comm="mount-copybind" name="lib" dev="ubifs" ino=924 scontext=system_u:system_r:mount_copybind_t:s0-s15:c0.c1023 tcontext=system_u:object_r:var_lib_t:s0 tclass=dir permissive=0
[ 29.599787] type=1400 audit(315964806.049:15): avc: denied { search } for pid=486 comm="mount-copybind" name="lib" dev="ubifs" ino=924 scontext=system_u:system_r:mount_copybind_t:s0-s15:c0.c1023 tcontext=system_u:object_r:var_lib_t:s0 tclass=dir permissive=0
[ 30.965533] session id:0x0 state:5
[ 30.965557] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_M3_STATE
[ 30.967839] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_M3_STATE event, current states: M0 & D0_STATE
[ 30.983284] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 30.985903] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 30.992223] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 30.998094] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 31.006470] ipa_dma ipa3_dma_disable:491 There is pending work, can't disable.
[ 31.009198] [0x0 mhi_sm_prepare_suspend] IPA disable fail cnt:0
[ 31.040125] [0x0 mhi_sm_prepare_suspend] IPA DMA successfully disabled
[ 31.040178] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D3_HOT_EVENT event, current states: M3 and D0_STATE
[ 32.628706] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 32.628736] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 32.651958] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 32.652001] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 32.970245] UBIFS error (ubi0:2 pid 926): ubifs_mount: too few LEBs (9), min. is 17
[ 33.760180] vddpx_2: disabling
[ 33.829334] MAIN_MGR: hvdcp_opti Version: 3:0:0
[ 33.854170] MAIN_MGR: capset failed: Permission denied
[ 33.984195] CHG_POLICY_PATH: Failed to get IIO path for MAIN_PSY
[ 33.984360] MAIN_MGR: Failed to setup PSY and IIO path
[ 34.010119] ADC channel pmx65_ambient_therm EOC took 21 ms
[ 34.232389] FX_ERR: fx_modem_cfg_daemon: init success!
[ 34.243349] type=1400 audit(315964810.689:16): avc: denied { search } for pid=936 comm="fx_set_band" name="fx" dev="ubifs" ino=134 scontext=system_u:system_r:initrc_t:s0-s15:c0.c1023 tcontext=system_u:object_r:atfwd_data_t:s0 tclass=dir permissive=0
[ 34.627468] [logevent]: Got log agent port id 100, log agent register
[ 34.704612] gpio gpiochip0: (f100000.pinctrl): allocate IRQ 110, hwirq 63
[ 34.704640] gpio gpiochip0: (f100000.pinctrl): found parent hwirq 4294967295
[ 34.815316] gpio gpiochip0: (f100000.pinctrl): alloc_irqs_parent for 110 parent hwirq -1
[ 35.070481] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 35.070581] qrtr_mhi_dev soc:qcom,mhi_dev_qrtr: send failed rc:-19 len:52
[ 35.110100] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 35.110130] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 35.114492] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 35.122100] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 35.264552] Starting securemsm qseecomd daemon ....:
[ 35.858882] done
[ 35.892279] Creating QWES LICENSE STORE : /persist/data/pfm/licenses/
[ 36.150110] ++++ /etc/initscripts/power_config -> ENABLE-DCC START
[ 36.159700] msm-dcc 117f000.dcc_v2: DCC list passed 2
[ 36.159741] msm-dcc 117f000.dcc_v2: All values written to enable.
[ 36.353569] SFS configuration started.
[ 36.422230] ++++ /etc/initscripts/power_config -> ENABLE-DCC END
[ 36.422348] ++++ /etc/initscripts/power_config -> ENABLE-FTRACE START
[ 36.465415] type=1400 audit(315964812.919:17): avc: denied { fsetid } for pid=1047 comm="chmod" capability=4 scontext=system_u:system_r:sfs_config_initrc_t:s0-s15:c0.c1023 tcontext=system_u:system_r:sfs_config_initrc_t:s0-s15:c0.c1023 tclass=capability permissive=0
[ 36.466187] type=1400 audit(315964812.919:18): avc: denied { fsetid } for pid=1047 comm="chmod" capability=4 scontext=system_u:system_r:sfs_config_initrc_t:s0-s15:c0.c1023 tcontext=system_u:system_r:sfs_config_initrc_t:s0-s15:c0.c1023 tclass=capability permissive=0
[ 37.522972] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 37.523012] qrtr_mhi_dev soc:qcom,mhi_dev_qrtr: send failed rc:-19 len:52
[ 37.600292] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 37.600322] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 37.640916] pcie-diag is invoked
[ 37.661737] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 37.664042] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 38.030417] pcie-diag: Debug transport for Diag is pcie
[ 38.030501] pcie-diag: test_diag is running in pcie mode
[ 40.080120] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 40.084502] qrtr_mhi_dev soc:qcom,mhi_dev_qrtr: send failed rc:-19 len:52
[ 40.210957] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 40.210988] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 40.264396] [open_client_mhi_channels] Channels are not connected
[ 40.306198] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 40.306242] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 40.601746] QSEECOM: qseecom_load_app: App (cmnlib) does'nt exist, loading apps for first time
[ 40.800613] [Fox] get pdflag 48, smem_type 135
[ 40.818996] [Fox] set sdc 4949, smem_type 135
[ 40.938477] QSEECOM: qseecom_load_app: scm_call to load app failed
[ 40.938603] QSEECOM: qseecom_ioctl: failed load_app request: -22
[ 41.053058] FX_ERR: Current Time is: [1980-01-06 00:00:17.498]
[ 41.083813] MAIN_MGR: hvdcp_opti Version: 3:0:0
[ 41.087650] MAIN_MGR: capset failed: Permission denied
[ 41.171085] CHG_POLICY_PATH: Failed to get IIO path for MAIN_PSY
[ 41.171248] MAIN_MGR: Failed to setup PSY and IIO path
[ 41.264746] [open_client_mhi_channels] Channels are not connected
[ 41.588588] MAIN_MGR: hvdcp_opti Version: 3:0:0
[ 41.588925] MAIN_MGR: capset failed: Permission denied
[ 41.652197] CHG_POLICY_PATH: Failed to get IIO path for MAIN_PSY
[ 41.652360] MAIN_MGR: Failed to setup PSY and IIO path
[ 42.057773] MAIN_MGR: hvdcp_opti Version: 3:0:0
[ 42.058097] MAIN_MGR: capset failed: Permission denied
[ 42.080485] CHG_POLICY_PATH: Failed to get IIO path for MAIN_PSY
[ 42.080641] MAIN_MGR: Failed to setup PSY and IIO path
[ 42.264963] [open_client_mhi_channels] Channels are not connected
[ 42.328991] MAIN_MGR: hvdcp_opti Version: 3:0:0
[ 42.329308] MAIN_MGR: capset failed: Permission denied
[ 42.342872] QSEECOM: qseecom_load_app: App (cmnlib) does'nt exist, loading apps for first time
[ 42.380544] CHG_POLICY_PATH: Failed to get IIO path for MAIN_PSY
[ 42.380700] MAIN_MGR: Failed to setup PSY and IIO path
[ 42.492307] QSEECOM: qseecom_load_app: scm_call to load app failed
[ 42.493582] QSEECOM: qseecom_load_app: App (qwes) does'nt exist, loading apps for first time
[ 42.498841] QSEECOM: qseecom_ioctl: failed load_app request: -22
[ 42.720226] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 42.720265] qrtr_mhi_dev soc:qcom,mhi_dev_qrtr: send failed rc:-19 len:52
[ 42.724962] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 42.740177] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 42.740228] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 42.746299] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 42.980487] QSEECOM: qseecom_load_app: App with id 3 (qwes) now loaded
[ 43.265222] [open_client_mhi_channels] Channels are not connected
[ 44.257423] QSEECOM: __qseecom_reentrancy_process_incomplete_cmd: get cback req app_id = 1, resp->data = 0
[ 44.265438] [open_client_mhi_channels] Channels are not connected
[ 45.150929] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 45.151015] qrtr_mhi_dev soc:qcom,mhi_dev_qrtr: send failed rc:-19 len:52
[ 45.155728] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 45.172121] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 45.172204] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 45.178275] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 45.267091] [open_client_mhi_channels] Channels are not connected
[ 46.267489] [open_client_mhi_channels] Channels are not connected
[ 47.268694] [open_client_mhi_channels] Channels are not connected
[ 47.580939] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 47.581025] qrtr_mhi_dev soc:qcom,mhi_dev_qrtr: send failed rc:-19 len:52
[ 47.585724] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 47.593815] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 47.598278] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 47.605632] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 48.269896] [open_client_mhi_channels] Channels are not connected
[ 49.271208] [open_client_mhi_channels] Channels are not connected
[ 50.010945] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 50.011032] qrtr_mhi_dev soc:qcom,mhi_dev_qrtr: send failed rc:-19 len:52
[ 50.015742] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 50.039585] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 50.039713] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 50.046293] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 52.450930] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 52.451016] qrtr_mhi_dev soc:qcom,mhi_dev_qrtr: send failed rc:-19 len:52
[ 52.458297] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 52.463617] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 52.468153] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 52.475521] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 54.880986] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 54.881073] qrtr_mhi_dev soc:qcom,mhi_dev_qrtr: send failed rc:-19 len:52
[ 54.888560] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 54.893539] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 54.898228] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 54.905700] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 57.310943] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 57.311029] qrtr_mhi_dev soc:qcom,mhi_dev_qrtr: send failed rc:-19 len:52
[ 57.318276] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 57.323948] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 57.328255] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 57.335669] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 59.740933] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 59.741020] qrtr_mhi_dev soc:qcom,mhi_dev_qrtr: send failed rc:-19 len:52
[ 90.129747] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D0_EVENT event, current states: M3 and D3_HOT_STATE
[ 90.142739] session id:0x0 state:2
[ 90.142791] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_M0_STATE
[ 90.145112] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_M0_STATE event, current states: M3 & D0_STATE
[ 90.155351] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 90.163292] ipa_dma ipa3_dma_enable:420 Already enabled refcnt=1
[ 90.192467] [0x0 mhi_dev_close_channel] Failed to flush read completions to host
[ 90.192503] [0x0 mhi_dev_close_channel] 0 pending flush for ch_id:20
[ 90.214247] [0x0 mhi_dev_close_channel] Failed to flush read completions to host
[ 90.214282] [0x0 mhi_dev_close_channel] 0 pending flush for ch_id:21
[ 90.250206] [0x0 mhi_dev_close_channel] Failed to flush read completions to host
[ 90.250237] [0x0 mhi_dev_close_channel] 0 pending flush for ch_id:46
[ 90.256667] [0x0 mhi_dev_close_channel] Failed to flush read completions to host
[ 90.272963] [0x0 mhi_dev_close_channel] 0 pending flush for ch_id:47
[ 90.273052] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:12
[ 90.293721] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:13
[ 90.296209] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:4
[ 90.313240] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:5
[ 90.318832] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:14
[ 90.322121] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:15
[ 90.335617] qti_rmnet_peripheral.c:qti_rmnet_ph_mhi_ch_14_parse_uevents[1077] QTI:MHI CH 14 and/or 15 DOWN
[ 90.344015] qti_rmnet_peripheral.c:qti_rmnet_ph_mhi_ch_14_parse_uevents[1077] QTI:MHI CH 14 and/or 15 DOWN
[ 90.347138] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:20
[ 90.415971] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:21
[ 90.418516] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:32
[ 90.423521] qti_rmnet_peripheral.c:qti_rmnet_ph_mhi_ch_14_parse_uevents[1077] QTI:MHI CH 14 and/or 15 DOWN
[ 90.444710] qti_rmnet_peripheral.c:qti_rmnet_ph_mhi_ch_14_parse_uevents[1077] QTI:MHI CH 14 and/or 15 DOWN
[ 90.450892] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:33
[ 90.456690] qti_rmnet_peripheral.c:qti_rmnet_ph_mhi_ch_20_parse_uevents[1168] QTI:MHI CH 20 and/or 21 DOWN
[ 90.477218] qti_rmnet_peripheral.c:qti_rmnet_ph_mhi_ch_20_parse_uevents[1168] QTI:MHI CH 20 and/or 21 DOWN
[ 90.488225] qti_rmnet_peripheral.c:qti_rmnet_ph_mhi_ch_20_parse_uevents[1168] QTI:MHI CH 20 and/or 21 DOWN
[ 90.491320] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:36
[ 90.523887] qti_rmnet_peripheral.c:qti_rmnet_ph_mhi_ch_20_parse_uevents[1168] QTI:MHI CH 20 and/or 21 DOWN
[ 90.563513] QTI:Processing MHI Channel 20 LINK_DOWN
[ 90.574079] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:37
[ 90.598569] ------------[ cut here ]------------
[ 90.598605] WARNING: CPU: 0 PID: 151 at kernel/workqueue.c:3063 __flush_work+0x24c/0x260
[ 90.618816] Modules linked in: rmnet_core(O)
[ 90.618851] CPU: 0 PID: 151 Comm: kworker/0:3 Tainted: G U O 5.4.210-perf #1
[ 90.643265] Hardware name: Qualcomm Technologies, Inc. SDXLEMUR (Flattened Device Tree)
[ 90.648222] Workqueue: events mhi_dev_scheduler
[ 90.740209] [<b010e920>] (unwind_backtrace) from [<b010bc48>] (show_stack+0x10/0x14)
[ 90.740241] [<b010bc48>] (show_stack) from [<b011d918>] (__warn+0xc4/0xdc)
[ 90.800191] [<b011d918>] (__warn) from [<b011d9ac>] (warn_slowpath_fmt+0x7c/0x94)
[ 90.800221] [<b011d9ac>] (warn_slowpath_fmt) from [<b01368c0>] (__flush_work+0x24c/0x260)
[ 90.806649] [<b01368c0>] (__flush_work) from [<b0136a10>] (__cancel_work_timer+0x134/0x1e0)
[ 90.818814] Launch adb is starting adbd...
[ 90.853894] read descriptors
[ 90.856943] read strings
[ 90.913244] [<b0136a10>] (__cancel_work_timer) from [<b09474cc>] (ipa3_teardown_sys_pipe+0x3bc/0x1054)
[ 90.913280] [<b09474cc>] (ipa3_teardown_sys_pipe) from [<b099932c>] (ipa3_dma_destroy+0x17c/0x57c)
[ 91.014744] [<b099932c>] (ipa3_dma_destroy) from [<b0868d5c>] (mhi_dev_sm_exit+0xf4/0x124)
[ 91.014777] [<b0868d5c>] (mhi_dev_sm_exit) from [<b085c5e8>] (mhi_dev_scheduler+0x998/0x1128)
[ 91.090139] [<b085c5e8>] (mhi_dev_scheduler) from [<b013a058>] (process_one_work+0x20c/0x4c4)
[ 91.090172] [<b013a058>] (process_one_work) from [<b013ae20>] (worker_thread+0x31c/0x644)
[ 91.097639] [<b013ae20>] (worker_thread) from [<b013f078>] (kthread+0x194/0x198)
[ 91.170096] [<b013f078>] (kthread) from [<b01010e8>] (ret_from_fork+0x14/0x2c)
[ 91.170122] Exception stack(0xb723bfb0 to 0xb723bff8)
[ 91.176201] bfa0: 00000000 00000000 00000000 00000000
[ 91.218772] bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 91.218798] bfe0: 00000000 00000000 00000000 00000000 00000013 00000000
[ 91.240108] ---[ end trace 900a5bc39c194438 ]---
[ 91.248040] ------------[ cut here ]------------
[ 91.248072] WARNING: CPU: 0 PID: 151 at kernel/workqueue.c:3063 __flush_work+0x24c/0x260
[ 91.260108] Modules linked in: rmnet_core(O)
[ 91.260138] CPU: 0 PID: 151 Comm: kworker/0:3 Tainted: G U W O 5.4.210-perf #1
[ 91.264040] Hardware name: Qualcomm Technologies, Inc. SDXLEMUR (Flattened Device Tree)
[ 91.276401] Workqueue: events mhi_dev_scheduler
[ 91.279935] [<b010e920>] (unwind_backtrace) from [<b010bc48>] (show_stack+0x10/0x14)
[ 91.284672] [<b010bc48>] (show_stack) from [<b011d918>] (__warn+0xc4/0xdc)
[ 91.292553] [<b011d918>] (__warn) from [<b011d9ac>] (warn_slowpath_fmt+0x7c/0x94)
[ 91.299114] [<b011d9ac>] (warn_slowpath_fmt) from [<b01368c0>] (__flush_work+0x24c/0x260)
[ 91.306815] [<b01368c0>] (__flush_work) from [<b0136a10>] (__cancel_work_timer+0x134/0x1e0)
[ 91.314922] [<b0136a10>] (__cancel_work_timer) from [<b09474cc>] (ipa3_teardown_sys_pipe+0x3bc/0x1054)
[ 91.323152] [<b09474cc>] (ipa3_teardown_sys_pipe) from [<b0999348>] (ipa3_dma_destroy+0x198/0x57c)
[ 91.332480] [<b0999348>] (ipa3_dma_destroy) from [<b0868d5c>] (mhi_dev_sm_exit+0xf4/0x124)
[ 91.341419] [<b0868d5c>] (mhi_dev_sm_exit) from [<b085c5e8>] (mhi_dev_scheduler+0x998/0x1128)
[ 91.349551] [<b085c5e8>] (mhi_dev_scheduler) from [<b013a058>] (process_one_work+0x20c/0x4c4)
[ 91.358269] [<b013a058>] (process_one_work) from [<b013ae20>] (worker_thread+0x31c/0x644)
[ 91.366753] [<b013ae20>] (worker_thread) from [<b013f078>] (kthread+0x194/0x198)
[ 91.374896] [<b013f078>] (kthread) from [<b01010e8>] (ret_from_fork+0x14/0x2c)
[ 91.382372] Exception stack(0xb723bfb0 to 0xb723bff8)
[ 91.389299] bfa0: 00000000 00000000 00000000 00000000
[ 91.394536] bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 91.402718] bfe0: 00000000 00000000 00000000 00000000 00000013 00000000
[ 91.410834] ---[ end trace 900a5bc39c194439 ]---
[ 91.474061] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D3_HOT_EVENT event, current states: READY and D0_STATE
[ 91.747996] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D3_COLD_EVENT event, current states: READY and D3_HOT_STATE
[ 91.749197] PM: suspend entry (deep)
[ 91.759075] Filesystems sync: 0.000 seconds
[ 91.761966] ipa ipa_pm_notify:507 Entry
[ 91.765659] ipa ipa_pm_notify:519 Exit
[ 91.775684] Freezing user space processes ... (elapsed 0.003 seconds) done.
[ 91.779151] OOM killer disabled.
[ 91.784973] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
[ 91.788359] printk: Suspending console(s) (use no_console_suspend to debug)
[ 91.834337] qcom_glink_native_intr: 106 triggered glink-native-modem
[ 91.838172] OOM killer enabled.
[ 91.843631] Restarting tasks ...
[ 91.843734] msm-dwc3 a600000.ssusb: Could not get usb psy
[ 91.854351] smcinvoke: process_accept_req: process_accept_req txn 4 either invalid or removed from Q
[ 91.855279] smcinvoke: process_accept_req: accept thread returning with ret: -11
[ 91.864601] smcinvoke: process_accept_req: process_accept_req txn 3 either invalid or removed from Q
[ 91.873279] done.
[ 91.881076] smcinvoke: process_accept_req: accept thread returning with ret: -11
[ 91.886842] ipa ipa_pm_notify:507 Entry
[ 91.890620] ipa ipa_pm_notify:519 Exit
[ 91.893817] Resume cause unknown
[ 91.897631] PM: suspend exit
[ 92.029674] Config c/1 of g1 needs at least one function.
[ 92.029715] udc a600000.dwc3: failed to start g1: -22
[ 92.034545] Started adbd.
[ 92.410926] PM: suspend entry (deep)
[ 92.412970] Filesystems sync: 0.000 seconds
[ 92.416275] ipa ipa_pm_notify:507 Entry
[ 92.421249] ipa ipa_pm_notify:519 Exit
[ 92.424536] Freezing user space processes ... (elapsed 0.003 seconds) done.
[ 92.428504] OOM killer disabled.
[ 92.434785] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
[ 92.438143] printk: Suspending console(s) (use no_console_suspend to debug)
[ 92.475302] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_RST_DEAST_EVENT event, current states: READY and D3_COLD_STATE
[ 92.476079] ep_pcie_reset_init: After Reset assert pcie_core_reset
[ 92.477141] ep_pcie_reset_init: After Reset de-assert pcie_core_reset
[ 92.477156] ep_pcie_reset_init: After Reset assert pcie_phy_reset
[ 92.478208] ep_pcie_reset_init: After Reset de-assert pcie_phy_reset
[ 92.503629] ep_pcie_phy_init: PCIe V1711211: Unexpected phy version 8 is caught
[ 92.509648] ep_pcie_core_enable_endpoint: PCIe V1711211: PCIe PHY is ready
[ 92.523102] OOM killer enabled.
[ 92.530125] Restarting tasks ...
[ 92.530237] msm-dwc3 a600000.ssusb: Could not get usb psy
[ 92.536663] ep_pcie_core_enable_endpoint: PCIe V1711211: link initialized for LE PCIe endpoint
[ 92.542094] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_RST_DEAST_EVENT event, current states: READY and D0_STATE
[ 92.550607] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D3_COLD_EVENT event, current states: READY and D0_STATE
[ 92.561626] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D0_EVENT event, current states: READY and D3_COLD_STATE
[ 92.572162] [0x0 mhi_sm_pcie_event_manager] EP_PCIE_PM_D0_EVENT: illegal in current MHI state: READY and D3_COLD_STATE
[ 92.582949] [0x0 mhi_sm_handle_syserr] Start handling SYSERR, MHI state: READY and D3_COLD_STATE
[ 92.583108] ep_pcie_core_get_msi_config: PCIe V1711211: MSI is not enabled yet
[ 92.602700] [0x0 mhi_dev_schedule_msi_ipa] Error retrieving pcie msi logic
[ 92.609642] [0x0 mhi_dev_send_multiple_tr_events] error sending in msi
[ 92.616531] [0x0 mhi_dev_flush_cmd_completion_events] failed to send compl evts
[ 92.623042] [0x0 mhi_sm_handle_syserr] Failed to send SYSTEM ERROR state change event to host
[ 92.630239] [0x0 mhi_sm_handle_syserr] /n/n/nError ON DEVICE !!!!/n/n/n
[ 92.630246] ------------[ cut here ]------------
[ 92.645347] WARNING: CPU: 0 PID: 380 at drivers/platform/msm/mhi_dev/mhi_sm.c:851 mhi_sm_handle_syserr+0x670/0x908
[ 92.650191] Modules linked in: rmnet_core(O)
[ 92.660414] CPU: 0 PID: 380 Comm: kworker/u3:20 Tainted: G U W O 5.4.210-perf #1
[ 92.664747] Hardware name: Qualcomm Technologies, Inc. SDXLEMUR (Flattened Device Tree)
[ 92.672849] Workqueue: mhi_sm_wq mhi_sm_pcie_event_manager
[ 92.680862] [<b010e920>] (unwind_backtrace) from [<b010bc48>] (show_stack+0x10/0x14)
[ 92.686370] [<b010bc48>] (show_stack) from [<b011d918>] (__warn+0xc4/0xdc)
[ 92.694286] [<b011d918>] (__warn) from [<b011d9ac>] (warn_slowpath_fmt+0x7c/0x94)
[ 92.700993] [<b011d9ac>] (warn_slowpath_fmt) from [<b086f6ec>] (mhi_sm_handle_syserr+0x670/0x908)
[ 92.708508] [<b086f6ec>] (mhi_sm_handle_syserr) from [<b086e71c>] (mhi_sm_pcie_event_manager+0x1a08/0x206c)
[ 92.717380] [<b086e71c>] (mhi_sm_pcie_event_manager) from [<b013a058>] (process_one_work+0x20c/0x4c4)
[ 92.726963] [<b013a058>] (process_one_work) from [<b013ae20>] (worker_thread+0x31c/0x644)
[ 92.736304] [<b013ae20>] (worker_thread) from [<b013f078>] (kthread+0x194/0x198)
[ 92.744471] [<b013f078>] (kthread) from [<b01010e8>] (ret_from_fork+0x14/0x2c)
[ 92.751962] Exception stack(0xb6c8bfb0 to 0xb6c8bff8)
[ 92.758931] bfa0: 00000000 00000000 00000000 00000000
[ 92.764095] bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 92.772233] bfe0: 00000000 00000000 00000000 00000000 00000013 00000000
[ 92.780409] ---[ end trace 900a5bc39c19443a ]---
[ 92.786798] [0x0 mhi_sm_pcie_event_manager] Failed switching to SYSERR state
[ 92.796906] done.
[ 92.802702] ipa ipa_pm_notify:507 Entry
[ 92.802733] ipa ipa_pm_notify:519 Exit
[ 92.805339] Resume cause unknown
[ 92.809156] PM: suspend exit
[ 111.848699] session id:0x0 state:2
[ 111.848736] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_M0_STATE
[ 111.857533] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_M0_STATE event, current states: SYSTEM ERROR & D3_COLD_STATE
~ #
~ # cat /sys/kernel/debug/ipc_logging/ep-pcie-short/log
[ 0.188878073/ 0x46ba3fd] ep_pcie_init: PCIe V0: IPC[ 317.104767] debug_log: buffer size 975 < 1020
[ 317.108923] debug_log: buffer size 975 < 1020
detailed logging is enable for ep-pcie-short
[ 0.189050625/ 0x46bb0d9] ep_pcie_init: PCIe V0: IPC dump logging is enable for ep-pcie-dump
[ 0.189067395/ 0x46bb21d] DBG2:ep_pcie_debugfs_init: PCIe V0: debugfs is enabled
[ 0.189367760/ 0x46bc8ac] ep_pcie_init: PCIe V0: platform driver is registered
[ 0.191607760/ 0x46c70ac] ep_pcie_core_register_event: PCIe V0: Event 0x20 is registered
[ 1.949768078/ 0x66f86b4] ep_pcie_probe: PCIe V0: pcie-link-speed:3
[ 1.949777036/ 0x66f8753] ep_pcie_probe: PCIe V0: pcie-vendor-id:6091.
[ 1.949781620/ 0x66f87ab] ep_pcie_probe: PCIe V0: pcie-device-id:776.
[ 1.949824120/ 0x66f8ae0] ep_pcie_probe: [FOX] pcie-vendor-id:0x105b,pcie-device-id:0xe0d9
[ 1.949827870/ 0x66f8b23] ep_pcie_probe: PCIe V0: dbi-base-reg does not exist
[ 1.949830734/ 0x66f8b5a] ep_pcie_probe: PCIe V0: slv-space-reg does not exist
[ 1.949833599/ 0x66f8b91] ep_pcie_probe: PCIe V0: phy-status-reg does not exist
[ 1.949836255/ 0x66f8bc4] ep_pcie_probe: PCIe V0: phy-status-reg2:0x1214
[ 1.949839068/ 0x66f8bfa] ep_pcie_probe: PCIe V0: pcie-phy-ver:8
[ 1.949841880/ 0x66f8c30] ep_pcie_probe: PCIe V0: pcie edma is not enabled
[ 1.949844588/ 0x66f8c64] ep_pcie_probe: PCIe V0: active config is enabled
[ 1.949847297/ 0x66f8c98] ep_pcie_probe: PCIe V0: aggregated IRQ is enabled
[ 1.949850057/ 0x66f8ccd] ep_pcie_probe: PCIe V0: Mhi a7 IRQ is enabled
[ 1.949852870/ 0x66f8d03] ep_pcie_probe: PCIe V0: enum by PERST is not enabled
[ 1.949855578/ 0x66f8d37] ep_pcie_probe: PCIe V0: tcsr pcie perst is supported
[ 1.949857974/ 0x66f8d65] ep_pcie_probe: PCIe V0: AOSS reset for perst needed
[ 1.949860422/ 0x66f8d94] ep_pcie_probe: PCIe V1711211: MHI M2 autonomous is not enabled
[ 1.949863130/ 0x66f8dc8] ep_pcie_probe: PCIe V1711211: PME during reboot/panic (in D3hot) is needed
[ 1.949866099/ 0x66f8e01] ep_pcie_probe: PCIe V1711211: soc-reset-offset:0xb01b8
[ 1.949869276/ 0x66f8e3e] ep_pcie_probe: PCIe V1711211: Gen4 using aux_clk = 16.6 MHz
[ 1.949873651/ 0x66f8e92] ep_pcie_get_resources: PCIe V1711211
[ 1.949878599/ 0x66f8ef2] ep_pcie_get_resources: PCIe V1711211: phy init length is 0x8b
[ 1.949891359/ 0x66f8fe6] DBG2:ep_pcie_get_resources: PCIe V1711211: cannot get max-clock-frequency-hz property from DT:-22
[ 1.953829484/ 0x670b74e] ep_pcie_get_resources: no qcom,vreg-cx-voltage-level property
[ 1.954068963/ 0x670c93c] ep_pcie_get_resources: GPIO num for perst-gpio is 973
[ 1.954082870/ 0x670ca44] ep_pcie_get_resources: GPIO num for wake-gpio is 969
[ 1.954094328/ 0x670cb20] ep_pcie_get_resources: GPIO num for clkreq-gpio is 972
[ 1.954105213/ 0x670cbf1] ep_pcie_get_resources: GPIO mdm2apstatus-gpio is not supported in this configuration
[ 1.954149432/ 0x670cf42] ep_pcie_get_resources: Freq of Clock pcie_cfg_ahb_clk is:0
[ 1.954155265/ 0x670cfb1] ep_pcie_get_resources: Freq of Clock pcie_mstr_axi_clk is:0
[ 1.954161203/ 0x670d023] ep_pcie_get_resources: Freq of Clock pcie_slv_axi_clk is:0
[ 1.954167765/ 0x670d0a1] ep_pcie_get_resources: Freq of Clock pcie_aux_clk is:0
[ 1.954174588/ 0x670d124] ep_pcie_get_resources: Freq of Clock pcie_ldo is:0
[ 1.954181776/ 0x670d1ae] ep_pcie_get_resources: Freq of Clock pcie_sleep_clk is:0
[ 1.954189588/ 0x670d244] ep_pcie_get_resources: Freq of Clock pcie_slv_q2a_axi_clk is:0
[ 1.954196359/ 0x670d2c6] ep_pcie_get_resources: Freq of Clock pcie_pipe_clk_mux is:0
[ 1.954204484/ 0x670d362] ep_pcie_get_resources: Freq of Clock pcie_pipe_clk_ext_src is:0
[ 1.954212140/ 0x670d3f6] ep_pcie_get_resources: Freq of Clock pcie_0_ref_clk_src is:0
[ 1.954217818/ 0x670d462] ep_pcie_get_resources: Freq of Clock pcie_pipe_clk is:0
[ 1.954255995/ 0x670d741] ep_pcie_get_resources: start addr for parf is 0x01c00000
[ 1.954282297/ 0x670d939] ep_pcie_get_resources: start addr for phy is 0x01c06000
[ 1.954288338/ 0x670d9ad] ep_pcie_get_resources: start addr for mmio is 0x01c03000
[ 1.954293495/ 0x670da10] ep_pcie_get_resources: start addr for msi is 0x40002000
[ 1.954297713/ 0x670da60] ep_pcie_get_resources: start addr for dm_core is 0x40000000
[ 1.954301620/ 0x670daac] ep_pcie_get_resources: start addr for elbi is 0x40000f20
[ 1.954305422/ 0x670daf4] ep_pcie_get_resources: start addr for iatu is 0x40001000
[ 1.954314588/ 0x670dba3] ep_pcie_get_resources: start addr for edma is 0x40002000
[ 1.954319745/ 0x670dc08] ep_pcie_get_resources: start addr for tcsr_pcie_perst_en is 0x01fcb000
[ 1.954323547/ 0x670dc50] ep_pcie_get_resources: start addr for aoss_cc_reset is 0x0c2f1000
[ 1.954331463/ 0x670dceb] DBG2:ep_pcie_get_resources: PCIe V1711211: can't find IRQ # for int_pm_turnoff
[ 1.954335422/ 0x670dd34] DBG2:ep_pcie_get_resources: PCIe V1711211: can't find IRQ # for int_dstate_change
[ 1.954338807/ 0x670dd75] DBG2:ep_pcie_get_resources: PCIe V1711211: can't find IRQ # for int_l1sub_timeout
[ 1.954342140/ 0x670ddb5] DBG2:ep_pcie_get_resources: PCIe V1711211: can't find IRQ # for int_link_up
[ 1.954345630/ 0x670ddf8] DBG2:ep_pcie_get_resources: PCIe V1711211: can't find IRQ # for int_link_down
[ 1.954348963/ 0x670de38] DBG2:ep_pcie_get_resources: PCIe V1711211: can't find IRQ # for int_bridge_flush_n
[ 1.954352349/ 0x670de79] DBG2:ep_pcie_get_resources: PCIe V1711211: can't find IRQ # for int_bme
[ 1.954355578/ 0x670deb7] DBG2:ep_pcie_get_resources: IRQ # for int_global is 33
[ 1.954358703/ 0x670def3] ep_pcie_gpio_init: PCIe V1711211
[ 1.954386099/ 0x670e102] ep_pcie_irq_init: PCIe V1711211
[ 1.954427713/ 0x670e422] ep_pcie_irq_init: PCIe V1711211: request global interrupt 33
[ 1.976519120/ 0x6775cff] ep_pcie_probe: PCIe V1711211: 40002000.qcom,pcie got resources successfully; start turning on the link
[ 1.976523807/ 0x6775d55] ep_pcie_enumeration: PCIe V1711211: start PCIe link enumeration per host side
[ 1.976526411/ 0x6775d87] ep_pcie_core_enable_endpoint: PCIe V1711211: options input are 0xffffffff
[ 1.976529588/ 0x6775dc4] ep_pcie_vreg_init: PCIe V1711211
[ 1.976531255/ 0x6775de5] ep_pcie_vreg_init: PCIe V1711211: Vreg vreg-1p8 is being enabled
[ 1.976669328/ 0x6776840] ep_pcie_vreg_init: PCIe V1711211: Vreg vreg-0p9 is being enabled
[ 1.976747349/ 0x6776e1a] ep_pcie_vreg_init: PCIe V1711211: Vreg vreg-cx is being enabled
[ 1.976750318/ 0x6776e52] ep_pcie_vreg_init: PCIe V1711211: Vreg vreg-mx is being enabled
[ 1.976760838/ 0x6776f1d] ep_pcie_clk_init: PCIe V1711211
[ 1.977091463/ 0x67787ea] ep_pcie_clk_init: PCIe V1711211: set bus bandwidth
[ 1.977097245/ 0x6778857] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_cfg_ahb_clk
[ 1.977100005/ 0x677888c] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_mstr_axi_clk
[ 1.977102297/ 0x67788b8] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_slv_axi_clk
[ 1.977104484/ 0x67788e2] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_aux_clk
[ 1.977122193/ 0x6778a36] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_ldo
[ 1.977124224/ 0x6778a5d] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_sleep_clk
[ 1.977126203/ 0x6778a83] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_slv_q2a_axi_clk
[ 1.977128130/ 0x6778aa8] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_pipe_clk_mux
[ 1.977130161/ 0x6778acf] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_pipe_clk_ext_src
[ 1.977132297/ 0x6778af8] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_0_ref_clk_src
[ 1.977135005/ 0x6778b2b] ep_pcie_core_enable_endpoint: TCSR PERST_EN value before configure:0x0
[ 1.977137141/ 0x6778b55] ep_pcie_core_enable_endpoint: TCSR PERST_EN value after configure:0x0
[ 1.977139120/ 0x6778b7b] ep_pcie_core_enable_endpoint: PCIe V1711211: Link status is 0x40000000.
[ 1.977143443/ 0x6778bce] ep_pcie_core_enable_endpoint: PCIe V1711211: link initialized by bootloader for LE PCIe endpoint; skip link training in HLOS.
[ 1.983918182/ 0x67987ef] ep_pcie_core_enable_endpoint: [FOX] ep_pcie vid is 0xe0d9105b, subsys id is e0d9105b.
[ 1.983921984/ 0x6798832] ep_pcie_core_init: PCIe V1711211
[ 1.983923495/ 0x679884f] ep_pcie_core_init: PCIe V1711211: WRITING TO BDF TO SID
[ 1.983925734/ 0x679887a] ep_pcie_core_init: PCIe V1711211: FINISHED WRITING BDF TO SID
[ 1.983928182/ 0x67988a9] ep_pcie_core_init: PCIe V1711211: Updating SOC reset offset with val:0xb01b8
[ 1.983930734/ 0x67988da] ep_pcie_core_init: PCIe V1711211:SOC reset offset val:0xb01b8
[ 1.983934120/ 0x679891b] DBG2:ep_pcie_core_init: PCIe V1711211: Clear L23 READY after enumeration
[ 1.983938547/ 0x6798970] ep_pcie_core_init: PCIe V1711211: DBI base:0x40000000
[ 1.983940526/ 0x6798995] ep_pcie_core_init: PCIe V1711211: configure MSB of ATU base for flipping and LSB as 0x40001000
[ 1.983943338/ 0x67989cc] ep_pcie_core_init: PCIe V1711211: LSB of ATU base:0x40001000
[ 1.983949953/ 0x6798a4b] ep_pcie_core_init: Initial: CLASS_CODE_REVISION_ID:0xd400000; HDR_TYPE:0x0
[ 1.983953130/ 0x6798a88] ep_pcie_core_init: PCIe V1711211: PCIE20_PARF_INT_ALL_MASK:0x210e
[ 1.983957036/ 0x6798ad3] ep_pcie_pipe_clk_init: PCIe V1711211
[ 1.983960057/ 0x6798b0d] ep_pcie_pipe_clk_init: PCIe V1711211: enabled pipe clk pcie_pipe_clk
[ 1.983962401/ 0x6798b3a] ep_pcie_core_toggle_wake_gpio: PCIe V1711211: deassert PCIe WAKE# after PERST# is deasserted
[ 1.983967922/ 0x6798ba5] ep_pcie_core_toggle_wake_gpio: PCIe V1711211: No. 0 to de-assert PCIe WAKE#; perst is de-asserted; D3hot is not received, WAKE GPIO state:1
[ 1.983971932/ 0x6798bf2] ep_pcie_core_enable_endpoint: PCIe V1711211: EP_PCIE_OPT_ENUM_ASYNC is true
[ 1.983973859/ 0x6798c16] ep_pcie_core_enable_endpoint: PCIe V1711211: PCIe link is up but BME is disabled; current SW link status:1
[ 1.983978703/ 0x6798c73] ep_pcie_enumeration: PCIe V1711211: PCIe link training is successful with host side. Waiting for enumeration to complete
[ 1.996390109/ 0x67d2f4f] ep_pcie_handle_linkup_irq: PCIe V1711211: No. 1 linkup IRQ
[ 15.433947650/ 0x15ddf81f] ep_pcie_handle_bme_irq: PCIe V1711211: No. 1 BME IRQ
[ 15.433950567/ 0x15ddf856] ep_pcie_handle_bme_irq: PCIe V1711211:BME is set. Enumeration is complete
[ 15.433959369/ 0x15ddf8ff] DBG2:ep_pcie_handle_bme_irq: PCIe V1711211: Allow L1 after BME is set
[ 15.471715932/ 0x15e908cb] ep_pcie_enumeration_complete: PCIe V1711211: register driver for device 0xe0d9105b
[ 15.471730463/ 0x15e909d4] ep_pcie_notify_event: PCIe V1711211: Callback client for event 32
[ 15.820454266/ 0x164f3438] ep_pcie_core_register_event: PCIe V1711211: Event 0x31f is registered
[ 15.820748224/ 0x164f4a30] ep_pcie_core_get_linkstatus: PCIe V1711211: PCIe link is up and BME is enabled; current SW link status:2
[ 16.972744999/ 0x17a0c9eb] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 16.972749374/ 0x17a0ca3f] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 16.972752290/ 0x17a0ca77] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 16.972758749/ 0x17a0caf3] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 16.972760572/ 0x17a0cb16] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 16.972762238/ 0x17a0cb36] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 16.972764009/ 0x17a0cb58] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 16.972765676/ 0x17a0cb78] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 16.972767447/ 0x17a0cb99] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 16.972769113/ 0x17a0cbba] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 16.972770728/ 0x17a0cbd9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 16.972772447/ 0x17a0cbfc] ep_pcie_core_get_msi_config: PCIe V1711211: MSI config has been changed by host side for 1 time(s)
[ 16.972774634/ 0x17a0cc24] ep_pcie_core_get_msi_config: PCIe V1711211: old MSI cfg: lower:0x0; upper:0x0; data:0x0; msg_num:0x0
[ 16.972777499/ 0x17a0cc5b] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:4; lower:0xfee30040; limit:0xfee3103f; target_lower:0xfee30040; target_upper:0x0
[ 16.972783645/ 0x17a0ccd1] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 16.972785728/ 0x17a0ccf9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 16.972787395/ 0x17a0cd19] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0xfee30000
[ 16.972788957/ 0x17a0cd37] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x0
[ 16.972790572/ 0x17a0cd56] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0xfee31fff
[ 16.972792447/ 0x17a0cd79] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 16.972793957/ 0x17a0cd97] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 16.972795415/ 0x17a0cdb3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 16.972796718/ 0x17a0cdcc] ep_pcie_core_get_msi_config: PCIe V1711211: Conf iATU for IPA MSI info: lower:0xfee30040; upper:0x0
[ 16.972804478/ 0x17a0ce61] ep_pcie_core_config_db_routing: PCIe V1711211: DB routing info: chdb_cfg.base:0x64; chdb_cfg.end:0x6e; erdb_cfg.base:0x4; erdb_cfg.end:0x5; chdb_cfg.tgt_addr:0x3e28000; erdb_cfg.tgt_addr:0x3e28848
[ 16.985782655/ 0x17a49bbe] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 16.985787655/ 0x17a49c1e] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 16.985790572/ 0x17a49c56] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 16.985797291/ 0x17a49cd7] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 16.985799270/ 0x17a49cfd] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 16.985800936/ 0x17a49d1d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 16.985802811/ 0x17a49d41] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 16.985804478/ 0x17a49d61] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 16.985806197/ 0x17a49d82] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 16.985807863/ 0x17a49da2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 16.985809686/ 0x17a49dc4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 16.985815832/ 0x17a49e3b] DBG2:ep_pcie_core_config_outbound_iatu: PCIe V1711211: No outbound iATU config is needed since active config is enabled
[ 16.985817968/ 0x17a49e64] ep_pcie_core_config_outbound_iatu: PCIe V1711211: data_start:0x0; data_end:0xfffffffe; data_tgt_lower:0x0; data_tgt_upper:0x0; ctrl_start:0x0; ctrl_end:0xfffffffe; ctrl_tgt_lower:0x0; ctrl_tgt_upper:0x0
[ 16.985822707/ 0x17a49ebf] ep_pcie_core_config_outbound_iatu: PCIe V1711211: iATU configuration case No. 2: included
[ 16.985824218/ 0x17a49edc] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:3; lower:0x0; limit:0xfffffffe; target_lower:0x0; target_upper:0x0
[ 16.985830363/ 0x17a49f52] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 16.985832082/ 0x17a49f73] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 16.985833593/ 0x17a49f90] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x0
[ 16.985835103/ 0x17a49fad] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 16.985836666/ 0x17a49fcb] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0xffffffff
[ 16.985838280/ 0x17a49fe9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0x0
[ 16.985839738/ 0x17a4a006] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 16.985841145/ 0x17a4a021] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 16.985848072/ 0x17a4a0a6] ep_pcie_core_config_db_routing: PCIe V1711211: DB routing info: chdb_cfg.base:0x64; chdb_cfg.end:0x6e; erdb_cfg.base:0x4; erdb_cfg.end:0x5; chdb_cfg.tgt_addr:0x3e28000; erdb_cfg.tgt_addr:0x3e28848
[ 16.986304530/ 0x17a4c2e5] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 16.986308541/ 0x17a4c32f] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 16.986311197/ 0x17a4c362] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 16.986317499/ 0x17a4c3db] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 16.986319270/ 0x17a4c3fd] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 16.986320780/ 0x17a4c41a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 16.986322551/ 0x17a4c43c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 16.986324218/ 0x17a4c45c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 16.986326093/ 0x17a4c47f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 16.986327759/ 0x17a4c4a0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 16.986329218/ 0x17a4c4bc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 16.986378020/ 0x17a4c865] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 16.986381197/ 0x17a4c8a1] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 16.986383436/ 0x17a4c8cd] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 16.986389374/ 0x17a4c93f] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 16.986391145/ 0x17a4c961] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 16.986392707/ 0x17a4c97f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 16.986394322/ 0x17a4c99e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 16.986395884/ 0x17a4c9bc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 16.986397447/ 0x17a4c9da] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 16.986399009/ 0x17a4c9f7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 16.986400468/ 0x17a4ca14] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 17.011298228/ 0x17ac1569] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 17.011302186/ 0x17ac15b5] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 17.011305103/ 0x17ac15ed] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 17.011311509/ 0x17ac1668] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 17.011313541/ 0x17ac168f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 17.011315207/ 0x17ac16af] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 17.011317082/ 0x17ac16d3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 17.011318749/ 0x17ac16f3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 17.011320520/ 0x17ac1715] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 17.011322186/ 0x17ac1735] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 17.011323801/ 0x17ac1754] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 17.061625884/ 0x17bad3fc] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 17.061629634/ 0x17bad444] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 17.061632551/ 0x17bad47c] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 17.061639530/ 0x17bad502] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 17.061641405/ 0x17bad526] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 17.061643072/ 0x17bad546] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 17.061644843/ 0x17bad567] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 17.061646509/ 0x17bad587] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 17.061648176/ 0x17bad5a8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 17.061649843/ 0x17bad5c8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 17.061651509/ 0x17bad5e7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 17.111948333/ 0x17c9922b] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 17.111952291/ 0x17c99277] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 17.111955208/ 0x17c992ae] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 17.111961770/ 0x17c9932d] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 17.111963905/ 0x17c99356] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 17.111965572/ 0x17c99376] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 17.111967343/ 0x17c99397] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 17.111968958/ 0x17c993b7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 17.111970676/ 0x17c993d8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 17.111972343/ 0x17c993f8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 17.111973958/ 0x17c99416] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 17.141651145/ 0x17d245e1] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 17.141654895/ 0x17d24629] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 17.141657812/ 0x17d24661] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 17.141664270/ 0x17d246dd] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 17.141666145/ 0x17d24701] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 17.141667812/ 0x17d24721] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 17.141669583/ 0x17d24742] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 17.141671249/ 0x17d24763] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 17.141672968/ 0x17d24784] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 17.141674635/ 0x17d247a4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 17.141676249/ 0x17d247c3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 19.775000945/ 0x1ad5c31d] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 19.775004747/ 0x1ad5c366] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 19.775007664/ 0x1ad5c39e] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 19.775014122/ 0x1ad5c41a] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 19.775015997/ 0x1ad5c43e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 19.775017716/ 0x1ad5c45f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 19.775019434/ 0x1ad5c480] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 19.775021153/ 0x1ad5c4a1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 19.775022872/ 0x1ad5c4c2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 19.775024591/ 0x1ad5c4e3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 19.775026205/ 0x1ad5c502] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 19.777551362/ 0x1ad68265] ep_pcie_handle_dstate_change_irq: PCIe V1711211: No. 1 change to D3 state
[ 19.777554487/ 0x1ad682a1] ep_pcie_notify_event: PCIe V1711211: Callback client for event 2
[ 27.759789511/ 0x23f90e41] ep_pcie_handle_dstate_change_irq: PCIe V1711211: No. 1 change to D0 state, clearing wake pending:0
[ 27.759794511/ 0x23f90ea1] ep_pcie_handle_dstate_change_irq: PCIe V1711211: Acquired wakelock in D0
[ 27.759796750/ 0x23f90ecc] ep_pcie_notify_event: PCIe V1711211: Callback client for event 1
[ 27.771616438/ 0x23fc8548] ep_pcie_handle_bme_irq: PCIe V1711211: No. 2 BME IRQ
[ 27.771619042/ 0x23fc8578] ep_pcie_handle_bme_irq: PCIe V1711211:BME is set again after the enumeration has completed; callback client for link ready
[ 27.771621021/ 0x23fc859e] ep_pcie_notify_event: PCIe V1711211: Client does not register for event 32
[ 27.771624823/ 0x23fc85e7] DBG2:ep_pcie_handle_bme_irq: PCIe V1711211: Allow L1 after BME is set
[ 27.780840188/ 0x23ff390e] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.780843834/ 0x23ff3954] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.780846907/ 0x23ff398f] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.780853573/ 0x23ff3a0f] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.780855448/ 0x23ff3a33] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.780857115/ 0x23ff3a53] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.780858886/ 0x23ff3a75] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.780860553/ 0x23ff3a95] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.780862271/ 0x23ff3ab5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.780863938/ 0x23ff3ad5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.780865501/ 0x23ff3af4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.780871282/ 0x23ff3b63] DBG2:ep_pcie_core_config_outbound_iatu: PCIe V1711211: No outbound iATU config is needed since active config is enabled
[ 27.780873417/ 0x23ff3b8c] ep_pcie_core_config_outbound_iatu: PCIe V1711211: data_start:0x0; data_end:0xfffffffe; data_tgt_lower:0x0; data_tgt_upper:0x0; ctrl_start:0x0; ctrl_end:0xfffffffe; ctrl_tgt_lower:0x0; ctrl_tgt_upper:0x0
[ 27.780878313/ 0x23ff3bea] ep_pcie_core_config_outbound_iatu: PCIe V1711211: iATU configuration case No. 2: included
[ 27.780879876/ 0x23ff3c08] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:3; lower:0x0; limit:0xfffffffe; target_lower:0x0; target_upper:0x0
[ 27.780885709/ 0x23ff3c78] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.780887428/ 0x23ff3c99] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.780888990/ 0x23ff3cb7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x0
[ 27.780890501/ 0x23ff3cd4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.780892011/ 0x23ff3cf1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0xffffffff
[ 27.780893626/ 0x23ff3d10] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0x0
[ 27.780895084/ 0x23ff3d2c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.780896542/ 0x23ff3d48] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.780903209/ 0x23ff3dc8] ep_pcie_core_config_db_routing: PCIe V1711211: DB routing info: chdb_cfg.base:0x64; chdb_cfg.end:0x6e; erdb_cfg.base:0x4; erdb_cfg.end:0x5; chdb_cfg.tgt_addr:0x3e28000; erdb_cfg.tgt_addr:0x3e28848
[ 27.799286803/ 0x2404a08d] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.799290605/ 0x2404a0d6] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.799293521/ 0x2404a10e] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.799299824/ 0x2404a187] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.799301855/ 0x2404a1ae] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.799303626/ 0x2404a1d0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.799305396/ 0x2404a1f1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.799307063/ 0x2404a212] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.799308782/ 0x2404a232] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.799310449/ 0x2404a253] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.799312063/ 0x2404a271] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.807106074/ 0x2406eaff] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.807109511/ 0x2406eb41] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.807112324/ 0x2406eb77] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.807118574/ 0x2406ebef] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.807120501/ 0x2406ec14] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.807122167/ 0x2406ec34] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.807124042/ 0x2406ec58] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.807125709/ 0x2406ec78] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.807127428/ 0x2406ec99] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.807129094/ 0x2406ecb9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.807130709/ 0x2406ecd8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.811733469/ 0x2408460d] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.811737271/ 0x24084656] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.811740292/ 0x24084690] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.811746646/ 0x2408470a] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.811748730/ 0x24084732] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.811750396/ 0x24084752] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.811752271/ 0x24084776] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.811753938/ 0x24084796] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.811755657/ 0x240847b7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.811757324/ 0x240847d7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.811758938/ 0x240847f5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.817494667/ 0x2409f625] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.817499876/ 0x2409f688] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.817503469/ 0x2409f6d0] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.817510084/ 0x2409f74c] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.817512167/ 0x2409f774] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.817513886/ 0x2409f795] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.817515657/ 0x2409f7b7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.817517324/ 0x2409f7d7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.817519146/ 0x2409f7fa] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.817520813/ 0x2409f81a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.817522428/ 0x2409f839] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.821826230/ 0x240b3b02] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 27.821830865/ 0x240b3b5b] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 27.824322324/ 0x240bf637] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.824325969/ 0x240bf67d] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.824328782/ 0x240bf6b3] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.824334719/ 0x240bf725] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.824336594/ 0x240bf749] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.824338261/ 0x240bf769] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.824340032/ 0x240bf78b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.824341646/ 0x240bf7aa] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.824343261/ 0x240bf7c9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.824344824/ 0x240bf7e7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.824346282/ 0x240bf803] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.826708365/ 0x240ca92c] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.826713157/ 0x240ca987] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.826715865/ 0x240ca9bb] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.826721803/ 0x240caa2e] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.826723626/ 0x240caa50] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.826725292/ 0x240caa70] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.826726907/ 0x240caa8f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.826728469/ 0x240caaad] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.826730032/ 0x240caacb] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.826731594/ 0x240caae9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.826733053/ 0x240cab05] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.831031699/ 0x240ded6b] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 27.833193678/ 0x240e8f95] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.833198782/ 0x240e8ff3] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.833201594/ 0x240e9029] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.833207740/ 0x240e90a0] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.833209563/ 0x240e90c2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.833211126/ 0x240e90e0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.833212740/ 0x240e90ff] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.833214459/ 0x240e911f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.833216022/ 0x240e913e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.833217688/ 0x240e915e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.833219147/ 0x240e917a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.837506282/ 0x240fd303] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 27.837510188/ 0x240fd34e] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 27.839663157/ 0x241074c9] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.839667584/ 0x2410751c] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.839670136/ 0x2410754d] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.839676074/ 0x241075bf] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.839677844/ 0x241075e1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.839679459/ 0x24107600] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.839681074/ 0x2410761f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.839682584/ 0x2410763c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.839684199/ 0x2410765a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.839685761/ 0x24107678] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.839687219/ 0x24107695] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.843976594/ 0x2411b849] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 27.846221907/ 0x241260b0] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.846226126/ 0x24126100] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.846228782/ 0x24126133] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.846234928/ 0x241261a9] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.846236855/ 0x241261ce] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.846238522/ 0x241261ee] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.846240188/ 0x2412620d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.846241855/ 0x2412622d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.846243417/ 0x2412624c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.846244980/ 0x2412626a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.846246438/ 0x24126286] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.850536907/ 0x2413a450] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 27.850540709/ 0x2413a498] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 27.852791699/ 0x24144d6e] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.852797272/ 0x24144dd5] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.852799928/ 0x24144e09] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.852806074/ 0x24144e80] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.852807897/ 0x24144ea2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.852809459/ 0x24144ec0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.852811074/ 0x24144edf] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.852812636/ 0x24144efc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.852814199/ 0x24144f1b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.852815709/ 0x24144f38] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.852817219/ 0x24144f54] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.857103522/ 0x241590cf] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 27.859353990/ 0x24163998] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.859358053/ 0x241639e5] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.859360605/ 0x24163a16] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.859366542/ 0x24163a88] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.859368313/ 0x24163aab] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.859369928/ 0x24163ac9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.859371542/ 0x24163ae8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.859373105/ 0x24163b05] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.859374667/ 0x24163b24] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.859376230/ 0x24163b42] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.859377740/ 0x24163b5f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.863683834/ 0x24177e54] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 27.863687949/ 0x24177ea3] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 27.865954772/ 0x241828a8] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.865959095/ 0x241828f9] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.865961855/ 0x24182930] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.865968209/ 0x241829a8] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.865970084/ 0x241829cc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.865971803/ 0x241829ed] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.865973417/ 0x24182a0c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.865975240/ 0x24182a2e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.865976855/ 0x24182a4d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.865978522/ 0x24182a6e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.865980292/ 0x24182a90] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.870266751/ 0x24196c0c] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 27.872579615/ 0x241a1985] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.872583365/ 0x241a19cb] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.872586022/ 0x241a19fe] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.872592011/ 0x241a1a71] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.872593938/ 0x241a1a96] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.872595501/ 0x241a1ab4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.872597272/ 0x241a1ad6] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.872598782/ 0x241a1af3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.872600501/ 0x241a1b14] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.872602063/ 0x241a1b32] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.872603574/ 0x241a1b4f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.876884667/ 0x241b5c64] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 27.876888782/ 0x241b5cb3] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 27.879041386/ 0x241bfe27] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.879045657/ 0x241bfe77] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.879048313/ 0x241bfeaa] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.879054407/ 0x241bff1f] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.879056178/ 0x241bff41] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.879057688/ 0x241bff5e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.879059303/ 0x241bff7d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.879060865/ 0x241bff9b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.879062480/ 0x241bffba] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.879064042/ 0x241bffd8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.879065501/ 0x241bfff4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.883352376/ 0x241d4178] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 27.885639511/ 0x241ded03] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.885643470/ 0x241ded4d] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.885646178/ 0x241ded81] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.885652168/ 0x241dedf4] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.885653938/ 0x241dee16] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.885655657/ 0x241dee37] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.885657324/ 0x241dee56] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.885658834/ 0x241dee74] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.885660605/ 0x241dee96] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.885662115/ 0x241deeb3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.885663626/ 0x241deed0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.889951074/ 0x241f305f] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 27.889954928/ 0x241f30a9] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 27.892110188/ 0x241fd24f] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.892114459/ 0x241fd2a0] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.892117011/ 0x241fd2d1] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.892122897/ 0x241fd342] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.892124668/ 0x241fd364] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.892126282/ 0x241fd383] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.892127897/ 0x241fd3a2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.892129459/ 0x241fd3c0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.892131074/ 0x241fd3df] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.892132636/ 0x241fd3fc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.892134095/ 0x241fd419] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.896416699/ 0x2421154c] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 27.898698886/ 0x2421c077] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.898702688/ 0x2421c0be] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.898705293/ 0x2421c0f0] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.898711282/ 0x2421c163] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.898713001/ 0x2421c184] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.898714563/ 0x2421c1a2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.898716230/ 0x2421c1c1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.898717740/ 0x2421c1df] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.898719355/ 0x2421c1fe] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.898721022/ 0x2421c21e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.898722480/ 0x2421c23a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.903009720/ 0x242303c5] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 27.903013626/ 0x24230410] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 27.905165605/ 0x2423a578] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.905169615/ 0x2423a5c3] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.905172376/ 0x2423a5f8] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.905178418/ 0x2423a66c] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.905180240/ 0x2423a68f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.905181751/ 0x2423a6ac] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.905183418/ 0x2423a6cc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.905184980/ 0x2423a6ea] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.905186543/ 0x2423a708] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.905188053/ 0x2423a725] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.905189563/ 0x2423a741] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.909468418/ 0x2424e82d] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 27.911689616/ 0x24258ec8] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.911693886/ 0x24258f15] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.911696595/ 0x24258f4b] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.911702688/ 0x24258fbe] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.911704459/ 0x24258fe0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.911706178/ 0x24259001] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.911707793/ 0x24259020] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.911709355/ 0x2425903e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.911710970/ 0x2425905c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.911712480/ 0x2425907a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.911713991/ 0x24259097] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.915999616/ 0x2426d204] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 27.916003574/ 0x2426d24f] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 27.918285501/ 0x24277d76] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.918289459/ 0x24277dc0] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.918291959/ 0x24277df0] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.918298001/ 0x24277e64] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.918299772/ 0x24277e86] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.918301438/ 0x24277ea6] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.918303209/ 0x24277ec7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.918304876/ 0x24277ee8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.918306491/ 0x24277f07] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.918308105/ 0x24277f25] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.918309720/ 0x24277f45] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.922597793/ 0x2428c0e1] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 27.924751334/ 0x24296266] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.924755345/ 0x242962b1] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.924757949/ 0x242962e3] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.924764251/ 0x2429635c] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.924766334/ 0x24296384] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.924767897/ 0x242963a2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.924769511/ 0x242963c1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.924771126/ 0x242963df] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.924772688/ 0x242963fe] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.924774199/ 0x2429641b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.924775709/ 0x24296437] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.929058678/ 0x242aa571] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 27.929062428/ 0x242aa5b9] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 27.931340553/ 0x242b5097] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.931344511/ 0x242b50e1] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.931347324/ 0x242b5117] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.931353261/ 0x242b518a] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.931355188/ 0x242b51ae] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.931356699/ 0x242b51cb] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.931358366/ 0x242b51eb] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.931360032/ 0x242b520b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.931361595/ 0x242b5229] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.931363209/ 0x242b5248] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.931364668/ 0x242b5264] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.935648366/ 0x242c93ac] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 27.937803678/ 0x242d3553] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.937807741/ 0x242d359f] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.937810241/ 0x242d35cf] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.937816386/ 0x242d3645] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.937818157/ 0x242d3667] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.937819720/ 0x242d3685] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.937821334/ 0x242d36a4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.937822897/ 0x242d36c2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.937824511/ 0x242d36e1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.937826074/ 0x242d36ff] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.937827532/ 0x242d371b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.942114668/ 0x242e78a5] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 27.942118418/ 0x242e78ec] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 27.944394980/ 0x242f23ab] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.944398886/ 0x242f23f5] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.944401386/ 0x242f2425] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.944407428/ 0x242f249a] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.944409251/ 0x242f24bc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.944410866/ 0x242f24db] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.944412480/ 0x242f24fa] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.944414147/ 0x242f2519] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.944415866/ 0x242f253a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.944417428/ 0x242f2558] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.944418886/ 0x242f2575] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.948702324/ 0x243066b7] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 27.950860449/ 0x24310895] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.950864459/ 0x243108e0] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.950866959/ 0x24310910] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.950873105/ 0x24310986] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.950874824/ 0x243109a7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.950876386/ 0x243109c5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.950878001/ 0x243109e4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.950879564/ 0x24310a02] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.950881282/ 0x24310a23] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.950882845/ 0x24310a40] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.950884303/ 0x24310a5d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.955167064/ 0x24324b92] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 27.955170970/ 0x24324bdd] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 27.957453574/ 0x2432f711] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.957457584/ 0x2432f75c] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.957460293/ 0x2432f790] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.957466282/ 0x2432f804] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.957468053/ 0x2432f825] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.957469616/ 0x2432f843] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.957471230/ 0x2432f862] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.957472793/ 0x2432f880] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.957474511/ 0x2432f8a1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.957476074/ 0x2432f8bf] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.957477584/ 0x2432f8db] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.961764407/ 0x24343a5f] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 27.963918314/ 0x2434dbec] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.963922689/ 0x2434dc3e] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.963925345/ 0x2434dc71] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.963931282/ 0x2434dce3] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.963933001/ 0x2434dd04] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.963934616/ 0x2434dd23] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.963936230/ 0x2434dd42] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.963937793/ 0x2434dd5f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.963939407/ 0x2434dd7e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.963940918/ 0x2434dd9c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.963942376/ 0x2434ddb8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.968225189/ 0x24361eef] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 27.968228939/ 0x24361f36] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 27.970504407/ 0x2436c9e0] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.970508314/ 0x2436ca2a] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.970510918/ 0x2436ca5f] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.970517220/ 0x2436cad5] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.970518991/ 0x2436caf7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.970520553/ 0x2436cb15] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.970522168/ 0x2436cb34] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.970523834/ 0x2436cb54] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.970525605/ 0x2436cb75] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.970527168/ 0x2436cb94] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.970528626/ 0x2436cbb0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.974813626/ 0x24380d10] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 27.976969720/ 0x2438aec7] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.976973678/ 0x2438af11] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.976976230/ 0x2438af42] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.976982220/ 0x2438afb5] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.976984043/ 0x2438afd8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.976985605/ 0x2438aff6] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.976987272/ 0x2438b015] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.976988834/ 0x2438b033] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.976990397/ 0x2438b052] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.976991959/ 0x2438b06f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.976993418/ 0x2438b08c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.981278209/ 0x2439f1e8] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 27.981282012/ 0x2439f231] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 27.983555762/ 0x243a9cbb] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.983559772/ 0x243a9d06] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.983562428/ 0x243a9d39] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.983568418/ 0x243a9dac] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.983570189/ 0x243a9dce] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.983571699/ 0x243a9deb] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.983573314/ 0x243a9e0a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.983574876/ 0x243a9e28] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.983576491/ 0x243a9e47] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.983578053/ 0x243a9e65] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.983579512/ 0x243a9e81] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.987863939/ 0x243bdfd6] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 27.990142480/ 0x243c8ac0] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.990148782/ 0x243c8b33] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.990151439/ 0x243c8b66] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.990157637/ 0x243c8bdd] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.990159407/ 0x243c8c00] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.990161022/ 0x243c8c1e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.990162637/ 0x243c8c3d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.990164199/ 0x243c8c5a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.990165762/ 0x243c8c79] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.990167324/ 0x243c8c97] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.990168782/ 0x243c8cb3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 27.994684928/ 0x243ddf69] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 27.994688887/ 0x243ddfb5] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 27.996993262/ 0x243e8c8b] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 27.996997480/ 0x243e8cda] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 27.997000241/ 0x243e8d0f] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 27.997006282/ 0x243e8d83] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 27.997008157/ 0x243e8da8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 27.997009876/ 0x243e8dc8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 27.997011543/ 0x243e8de8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 27.997013210/ 0x243e8e08] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 27.997014824/ 0x243e8e26] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 27.997016491/ 0x243e8e47] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 27.997017949/ 0x243e8e63] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.001314043/ 0x243fd098] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.003470970/ 0x24407260] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.003475449/ 0x244072b3] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.003478157/ 0x244072e7] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.003484147/ 0x2440735a] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.003485918/ 0x2440737c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.003487585/ 0x2440739c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.003489199/ 0x244073bb] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.003490918/ 0x244073dc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.003492480/ 0x244073fa] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.003494147/ 0x2440741a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.003495762/ 0x24407439] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.007780137/ 0x2441b58d] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.007783939/ 0x2441b5d6] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.010034616/ 0x24425ea4] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.010039199/ 0x24425efb] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.010041855/ 0x24425f2f] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.010047897/ 0x24425fa3] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.010049824/ 0x24425fc7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.010051387/ 0x24425fe5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.010053053/ 0x24426004] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.010054616/ 0x24426023] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.010056178/ 0x24426041] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.010057689/ 0x2442605e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.010059199/ 0x2442607b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.014339980/ 0x2443a18a] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.016582897/ 0x244449c4] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.016586803/ 0x24444a0d] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.016589303/ 0x24444a3d] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.016595241/ 0x24444ab2] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.016597272/ 0x24444ad7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.016598991/ 0x24444af8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.016600762/ 0x24444b19] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.016602324/ 0x24444b36] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.016603887/ 0x24444b55] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.016605553/ 0x24444b75] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.016607064/ 0x24444b92] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.020889928/ 0x24458cc9] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.020893730/ 0x24458d12] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.023167897/ 0x244637a4] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.023171803/ 0x244637ed] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.023174251/ 0x2446381c] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.023180189/ 0x2446388f] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.023181960/ 0x244638b0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.023183574/ 0x244638cf] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.023185189/ 0x244638ee] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.023187012/ 0x24463911] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.023188626/ 0x24463930] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.023190189/ 0x2446394e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.023191699/ 0x2446396a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.027475189/ 0x24477aae] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.029628678/ 0x24481c33] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.029632897/ 0x24481c82] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.029635345/ 0x24481cb1] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.029641387/ 0x24481d25] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.029643158/ 0x24481d47] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.029644720/ 0x24481d65] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.029646335/ 0x24481d84] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.029648001/ 0x24481da4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.029649616/ 0x24481dc3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.029651230/ 0x24481de2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.029652741/ 0x24481dff] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.033938418/ 0x24495f6c] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.033942428/ 0x24495fb9] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.036217689/ 0x244a0a60] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.036221960/ 0x244a0ab0] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.036224355/ 0x244a0ade] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.036230397/ 0x244a0b53] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.036232168/ 0x244a0b74] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.036233678/ 0x244a0b91] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.036235449/ 0x244a0bb3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.036237220/ 0x244a0bd5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.036238835/ 0x244a0bf4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.036240397/ 0x244a0c12] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.036241855/ 0x244a0c2e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.040526699/ 0x244b4d8c] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.042679460/ 0x244bef03] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.042683470/ 0x244bef4d] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.042685970/ 0x244bef7e] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.042692012/ 0x244beff1] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.042693835/ 0x244bf014] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.042695345/ 0x244bf031] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.042697012/ 0x244bf051] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.042698522/ 0x244bf06e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.042700137/ 0x244bf08d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.042701699/ 0x244bf0ab] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.042703158/ 0x244bf0c7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.046985293/ 0x244d31f0] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.046989043/ 0x244d3238] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.049192376/ 0x244dd77a] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.049196439/ 0x244dd7c6] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.049198835/ 0x244dd7f4] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.049204876/ 0x244dd868] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.049206647/ 0x244dd88a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.049208210/ 0x244dd8a8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.049209824/ 0x244dd8c7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.049211387/ 0x244dd8e5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.049213001/ 0x244dd904] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.049214564/ 0x244dd922] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.049216022/ 0x244dd93e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.053501803/ 0x244f1aae] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.055776647/ 0x244fc54c] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.055780449/ 0x244fc593] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.055783106/ 0x244fc5c7] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.055789251/ 0x244fc63c] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.055790970/ 0x244fc65e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.055792533/ 0x244fc67b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.055794199/ 0x244fc69b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.055795866/ 0x244fc6bb] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.055797428/ 0x244fc6d9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.055799095/ 0x244fc6f9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.055800710/ 0x244fc718] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.060087116/ 0x24510893] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.060090918/ 0x245108dc] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.062244512/ 0x2451aa64] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.062248783/ 0x2451aab3] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.062251439/ 0x2451aae7] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.062257481/ 0x2451ab5a] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.062259303/ 0x2451ab7d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.062260918/ 0x2451ab9c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.062262585/ 0x2451abbc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.062264147/ 0x2451abda] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.062265710/ 0x2451abf8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.062267272/ 0x2451ac15] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.062268731/ 0x2451ac32] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.066549772/ 0x2452ed47] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.068751335/ 0x24539266] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.068755397/ 0x245392b2] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.068758001/ 0x245392e4] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.068763939/ 0x24539356] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.068765762/ 0x24539379] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.068767376/ 0x24539398] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.068768991/ 0x245393b7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.068770553/ 0x245393d4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.068772116/ 0x245393f3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.068773678/ 0x24539411] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.068775137/ 0x2453942d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.073061179/ 0x2454d5a1] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.073064981/ 0x2454d5ea] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.075266699/ 0x24557b0d] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.075270606/ 0x24557b55] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.075273106/ 0x24557b86] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.075279095/ 0x24557bfa] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.075280866/ 0x24557c1e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.075282585/ 0x24557c3c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.075284199/ 0x24557c5b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.075285762/ 0x24557c79] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.075287376/ 0x24557c98] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.075288939/ 0x24557cb6] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.075290449/ 0x24557cd2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.079573939/ 0x2456be16] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.081775762/ 0x2457633b] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.081779981/ 0x2457638a] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.081782481/ 0x245763ba] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.081788470/ 0x2457642e] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.081790293/ 0x24576450] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.081791804/ 0x2457646d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.081793470/ 0x2457648d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.081794981/ 0x245764aa] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.081796595/ 0x245764c9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.081798158/ 0x245764e7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.081799616/ 0x24576503] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.086082220/ 0x2458a636] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.086086283/ 0x2458a683] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.088329304/ 0x24594ebf] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.088333522/ 0x24594f0e] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.088336231/ 0x24594f42] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.088342272/ 0x24594fb6] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.088343991/ 0x24594fd8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.088345554/ 0x24594ff5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.088347220/ 0x24595015] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.088348783/ 0x24595033] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.088350397/ 0x24595052] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.088351960/ 0x24595070] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.088353418/ 0x2459508c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.092640710/ 0x245a9218] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.094839981/ 0x245b370c] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.094843887/ 0x245b3755] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.094846543/ 0x245b3788] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.094852585/ 0x245b37fc] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.094854356/ 0x245b381e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.094855918/ 0x245b383c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.094857533/ 0x245b385b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.094859251/ 0x245b387b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.094860866/ 0x245b389a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.094862429/ 0x245b38b9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.094863887/ 0x245b38d5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.099147272/ 0x245c7a17] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.099151074/ 0x245c7a60] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.101421856/ 0x245d24b0] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.101425866/ 0x245d24fb] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.101428366/ 0x245d252b] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.101434408/ 0x245d259f] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.101436179/ 0x245d25c1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.101437793/ 0x245d25e0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.101439408/ 0x245d25ff] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.101440970/ 0x245d261d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.101442533/ 0x245d263b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.101444252/ 0x245d265c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.101445866/ 0x245d267b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.105728210/ 0x245e67a8] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.107882064/ 0x245f0934] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.107886179/ 0x245f0981] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.107888731/ 0x245f09b2] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.107894720/ 0x245f0a26] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.107896491/ 0x245f0a47] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.107898002/ 0x245f0a64] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.107899668/ 0x245f0a84] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.107901231/ 0x245f0aa2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.107902845/ 0x245f0ac1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.107904512/ 0x245f0ae1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.107906022/ 0x245f0afe] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.112191179/ 0x24604c62] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.112195189/ 0x24604cae] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.114397377/ 0x2460f1da] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.114401387/ 0x2460f225] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.114403939/ 0x2460f256] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.114409981/ 0x2460f2ca] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.114411752/ 0x2460f2ec] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.114413314/ 0x2460f30a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.114414929/ 0x2460f329] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.114416491/ 0x2460f347] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.114418054/ 0x2460f365] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.114419616/ 0x2460f383] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.114421127/ 0x2460f39f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.118716856/ 0x246235ce] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.121013939/ 0x2462e216] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.121018002/ 0x2462e264] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.121020710/ 0x2462e298] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.121026960/ 0x2462e312] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.121029095/ 0x2462e339] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.121030970/ 0x2462e35d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.121032585/ 0x2462e37c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.121034252/ 0x2462e39c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.121035814/ 0x2462e3ba] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.121037377/ 0x2462e3d8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.121038991/ 0x2462e3f7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.125332637/ 0x246425fd] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.125337168/ 0x24642654] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.127509095/ 0x2464c93b] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.127513366/ 0x2464c98b] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.127515866/ 0x2464c9bb] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.127521908/ 0x2464ca2f] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.127523835/ 0x2464ca54] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.127525397/ 0x2464ca72] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.127527064/ 0x2464ca91] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.127528627/ 0x2464cab0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.127530189/ 0x2464cace] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.127531908/ 0x2464caef] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.127533418/ 0x2464cb0b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.131818314/ 0x24660c6a] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.134122585/ 0x2466b93e] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.134126491/ 0x2466b987] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.134129252/ 0x2466b9bc] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.134135345/ 0x2466ba32] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.134137168/ 0x2466ba55] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.134138731/ 0x2466ba73] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.134140397/ 0x2466ba92] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.134141960/ 0x2466bab0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.134143522/ 0x2466bace] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.134145241/ 0x2466baef] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.134146752/ 0x2466bb0b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.138428522/ 0x2467fc2e] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.138432585/ 0x2467fc7c] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.140591075/ 0x24689e62] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.140595502/ 0x24689eb5] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.140598106/ 0x24689ee6] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.140604095/ 0x24689f59] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.140606022/ 0x24689f7e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.140607585/ 0x24689f9c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.140609252/ 0x24689fbc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.140610918/ 0x24689fdc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.140612533/ 0x24689ffb] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.140614043/ 0x2468a018] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.140615658/ 0x2468a037] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.144901335/ 0x2469e1a4] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.147185658/ 0x246a8cf9] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.147189616/ 0x246a8d43] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.147192168/ 0x246a8d74] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.147198314/ 0x246a8dea] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.147200085/ 0x246a8e0c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.147201752/ 0x246a8e2c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.147203418/ 0x246a8e4b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.147205085/ 0x246a8e6b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.147206700/ 0x246a8e8a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.147208262/ 0x246a8ea9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.147209720/ 0x246a8ec5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.151498002/ 0x246bd064] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.151501908/ 0x246bd0af] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.153656439/ 0x246c7248] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.153661022/ 0x246c729e] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.153663522/ 0x246c72ce] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.153669460/ 0x246c7340] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.153671283/ 0x246c7363] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.153672845/ 0x246c7381] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.153674460/ 0x246c73a0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.153676022/ 0x246c73be] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.153677637/ 0x246c73dd] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.153679304/ 0x246c73fd] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.153680918/ 0x246c741c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.157964512/ 0x246db562] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.160240293/ 0x246e6012] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.160244356/ 0x246e605e] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.160247012/ 0x246e6092] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.160253054/ 0x246e6105] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.160254773/ 0x246e6126] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.160256439/ 0x246e6147] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.160258106/ 0x246e6166] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.160259668/ 0x246e6184] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.160261231/ 0x246e61a2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.160262793/ 0x246e61c0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.160264252/ 0x246e61dc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.164549408/ 0x246fa33f] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.164553210/ 0x246fa388] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.166705970/ 0x247044ff] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.166710345/ 0x24704551] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.166713054/ 0x24704585] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.166719043/ 0x247045f8] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.166720814/ 0x2470461b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.166722481/ 0x2470463a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.166724148/ 0x24704659] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.166725658/ 0x24704677] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.166727273/ 0x24704696] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.166728835/ 0x247046b3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.166730293/ 0x247046d0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.171015450/ 0x24718833] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.173293262/ 0x2472330b] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.173297168/ 0x24723354] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.173299877/ 0x2472338b] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.173306075/ 0x247233ff] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.173307898/ 0x24723422] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.173309460/ 0x24723440] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.173311075/ 0x2472345f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.173312637/ 0x2472347d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.173314356/ 0x2472349d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.173316023/ 0x247234be] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.173317637/ 0x247234dd] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.177615970/ 0x2473773d] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.177619825/ 0x24737787] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.179783418/ 0x247419cd] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.179787845/ 0x24741a21] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.179790710/ 0x24741a5b] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.179796960/ 0x24741ad0] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.179798731/ 0x24741af2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.179800293/ 0x24741b10] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.179801908/ 0x24741b2f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.179803575/ 0x24741b4f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.179805345/ 0x24741b71] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.179806908/ 0x24741b8f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.179808418/ 0x24741bab] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.184093731/ 0x24755d12] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.186371283/ 0x247607e3] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.186374929/ 0x24760828] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.186377533/ 0x2476085a] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.186383731/ 0x247608d2] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.186385502/ 0x247608f4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.186387168/ 0x24760914] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.186388783/ 0x24760933] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.186390346/ 0x24760950] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.186391908/ 0x2476096f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.186393575/ 0x2476098e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.186395033/ 0x247609ab] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.190678991/ 0x24774af8] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.190683002/ 0x24774b44] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.192839512/ 0x2477ed03] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.192843575/ 0x2477ed4f] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.192846283/ 0x2477ed83] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.192852273/ 0x2477edf6] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.192853991/ 0x2477ee17] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.192855554/ 0x2477ee35] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.192857221/ 0x2477ee55] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.192858887/ 0x2477ee75] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.192860502/ 0x2477ee94] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.192862116/ 0x2477eeb2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.192863523/ 0x2477eece] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.197143991/ 0x24792fd7] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.199355085/ 0x2479d5ae] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.199360918/ 0x2479d61c] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.199363523/ 0x2479d652] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.199370137/ 0x2479d6ce] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.199371960/ 0x2479d6f0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.199373523/ 0x2479d70e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.199375241/ 0x2479d72f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.199376856/ 0x2479d74d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.199378418/ 0x2479d76c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.199379981/ 0x2479d78a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.199381439/ 0x2479d7a6] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.203673366/ 0x247b198c] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.203677585/ 0x247b19dd] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.205974721/ 0x247bc626] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.205978835/ 0x247bc674] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.205981491/ 0x247bc6a7] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.205987637/ 0x247bc71e] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.205989564/ 0x247bc742] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.205991283/ 0x247bc763] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.205993158/ 0x247bc787] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.205994721/ 0x247bc7a4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.205996283/ 0x247bc7c3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.205997898/ 0x247bc7e2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.205999356/ 0x247bc7fe] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.210282585/ 0x247d093c] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.212437898/ 0x247daae4] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.212442741/ 0x247dab3f] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.212445554/ 0x247dab76] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.212451596/ 0x247dabe9] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.212453314/ 0x247dac0a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.212454825/ 0x247dac27] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.212456439/ 0x247dac46] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.212458002/ 0x247dac64] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.212459616/ 0x247dac83] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.212461179/ 0x247daca1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.212462689/ 0x247dacbd] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.216741283/ 0x247eeda3] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.216745033/ 0x247eedeb] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.219022689/ 0x247f98c0] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.219026283/ 0x247f9903] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.219028783/ 0x247f9933] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.219034825/ 0x247f99a7] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.219036596/ 0x247f99ca] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.219038314/ 0x247f99ea] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.219039929/ 0x247f9a09] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.219041491/ 0x247f9a27] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.219043054/ 0x247f9a45] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.219044616/ 0x247f9a63] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.219046075/ 0x247f9a7f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.223338419/ 0x2480dc6c] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.225495033/ 0x24817e2d] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.225499148/ 0x24817e7a] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.225501700/ 0x24817eab] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.225507689/ 0x24817f1e] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.225509460/ 0x24817f40] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.225511179/ 0x24817f61] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.225512794/ 0x24817f80] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.225514304/ 0x24817f9d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.225515919/ 0x24817fbc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.225517585/ 0x24817fdc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.225519148/ 0x24817ffa] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.229804564/ 0x2482c162] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.229808471/ 0x2482c1ad] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.232084460/ 0x24836c62] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.232088314/ 0x24836caa] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.232090919/ 0x24836cdc] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.232096960/ 0x24836d50] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.232098731/ 0x24836d72] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.232100241/ 0x24836d8f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.232101908/ 0x24836dae] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.232103471/ 0x24836dcd] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.232105085/ 0x24836dec] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.232106752/ 0x24836e0b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.232108210/ 0x24836e28] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.236387846/ 0x2484af21] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.238542273/ 0x248550b8] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.238546283/ 0x24855103] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.238548887/ 0x24855135] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.238554877/ 0x248551a8] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.238556648/ 0x248551ca] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.238558314/ 0x248551ea] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.238559929/ 0x24855209] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.238561492/ 0x24855227] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.238563106/ 0x24855245] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.238564617/ 0x24855263] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.238566127/ 0x2485527f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.242866439/ 0x24869507] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.242870606/ 0x24869556] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.248250867/ 0x248828dd] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.248255814/ 0x24882939] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.248258575/ 0x2488296f] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.248264929/ 0x248829e9] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.248266804/ 0x24882a0e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.248268471/ 0x24882a2d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.248270242/ 0x24882a4f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.248271908/ 0x24882a6f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.248273679/ 0x24882a90] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.248275189/ 0x24882aae] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.248276804/ 0x24882acc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.255693054/ 0x248a5705] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.258046856/ 0x248b078f] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.258051127/ 0x248b07e0] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.258053783/ 0x248b0813] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.258059721/ 0x248b0886] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.258061544/ 0x248b08a8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.258063210/ 0x248b08c8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.258064825/ 0x248b08e7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.258066492/ 0x248b0907] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.258068106/ 0x248b0926] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.258069825/ 0x248b0946] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.258071283/ 0x248b0963] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.262358471/ 0x248c4aed] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.262362794/ 0x248c4b40] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.264520919/ 0x248ced1f] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.264525242/ 0x248ced70] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.264527898/ 0x248ceda3] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.264533835/ 0x248cee14] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.264535606/ 0x248cee36] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.264537325/ 0x248cee57] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.264538940/ 0x248cee76] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.264540502/ 0x248cee94] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.264542117/ 0x248ceeb3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.264543679/ 0x248ceed1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.264545137/ 0x248ceeed] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.268824877/ 0x248e2fe8] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.271048627/ 0x248ed6b2] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.271053523/ 0x248ed70e] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.271056179/ 0x248ed741] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.271062325/ 0x248ed7b7] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.271064200/ 0x248ed7db] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.271065710/ 0x248ed7f8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.271067377/ 0x248ed818] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.271068887/ 0x248ed835] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.271070502/ 0x248ed854] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.271072065/ 0x248ed872] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.271073523/ 0x248ed88e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.275362169/ 0x24901a35] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.275366023/ 0x24901a7e] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.277586492/ 0x2490c109] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.277590554/ 0x2490c155] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.277593054/ 0x2490c185] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.277599356/ 0x2490c1ff] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.277601231/ 0x2490c222] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.277602794/ 0x2490c240] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.277604460/ 0x2490c25f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.277605971/ 0x2490c27d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.277607533/ 0x2490c29b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.277609096/ 0x2490c2b9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.277610606/ 0x2490c2d5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.281900710/ 0x24920498] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.284104877/ 0x2492a9ea] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.284108992/ 0x2492aa37] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.284111492/ 0x2492aa67] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.284117533/ 0x2492aadb] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.284119356/ 0x2492aafe] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.284121075/ 0x2492ab1f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.284122690/ 0x2492ab3e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.284124200/ 0x2492ab5b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.284125815/ 0x2492ab7a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.284127481/ 0x2492ab9a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.284128992/ 0x2492abb7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.288415606/ 0x2493ed36] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.288419408/ 0x2493ed7f] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.290623783/ 0x249492d5] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.290628106/ 0x24949326] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.290630658/ 0x24949356] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.290636752/ 0x249493cc] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.290638523/ 0x249493ee] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.290640190/ 0x2494940e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.290641856/ 0x2494942d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.290643419/ 0x2494944c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.290645033/ 0x2494946a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.290646544/ 0x24949488] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.290648054/ 0x249494a4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.294933263/ 0x2495d609] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.297206335/ 0x24968089] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.297210346/ 0x249680d1] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.297212950/ 0x24968103] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.297219096/ 0x24968179] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.297220867/ 0x2496819b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.297222429/ 0x249681b9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.297224200/ 0x249681db] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.297225867/ 0x249681fb] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.297227429/ 0x24968219] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.297228992/ 0x24968237] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.297230502/ 0x24968253] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.301518367/ 0x2497c3eb] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.301522325/ 0x2497c438] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.303675815/ 0x249865bc] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.303680085/ 0x2498660c] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.303682533/ 0x2498663b] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.303688679/ 0x249866b1] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.303690398/ 0x249866d2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.303692065/ 0x249866f2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.303693679/ 0x24986711] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.303695398/ 0x24986732] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.303696960/ 0x24986750] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.303698575/ 0x2498676e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.303700033/ 0x2498678b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.307983054/ 0x2499a8c5] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.310188106/ 0x249a4e28] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.310192117/ 0x249a4e73] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.310194617/ 0x249a4ea3] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.310200606/ 0x249a4f16] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.310202377/ 0x249a4f38] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.310203940/ 0x249a4f56] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.310205606/ 0x249a4f75] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.310207273/ 0x249a4f96] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.310208888/ 0x249a4fb4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.310210450/ 0x249a4fd3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.310211908/ 0x249a4fef] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.314496492/ 0x249b9148] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.314500242/ 0x249b918f] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.316699565/ 0x249c3684] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.316703575/ 0x249c36cf] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.316706023/ 0x249c36fe] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.316712065/ 0x249c3773] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.316713888/ 0x249c3795] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.316715554/ 0x249c37b5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.316717169/ 0x249c37d4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.316718731/ 0x249c37f2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.316720346/ 0x249c3811] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.316722013/ 0x249c3831] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.316723471/ 0x249c384d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.321011231/ 0x249d79e2] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.323211596/ 0x249e1eeb] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.323215658/ 0x249e1f37] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.323218315/ 0x249e1f6a] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.323224408/ 0x249e1fe0] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.323226179/ 0x249e2001] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.323227742/ 0x249e201f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.323229356/ 0x249e203e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.323230919/ 0x249e205c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.323232533/ 0x249e207b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.323234044/ 0x249e2098] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.323235554/ 0x249e20b5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.327521127/ 0x249f6220] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.327525086/ 0x249f626c] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.329727221/ 0x24a00797] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.329731179/ 0x24a007e1] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.329733731/ 0x24a00812] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.329739721/ 0x24a00885] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.329741492/ 0x24a008a8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.329743054/ 0x24a008c5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.329744669/ 0x24a008e4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.329746336/ 0x24a00904] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.329747950/ 0x24a00923] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.329749513/ 0x24a00940] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.329750971/ 0x24a0095d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.334038002/ 0x24a14ae5] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.336239721/ 0x24a1f008] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.336243783/ 0x24a1f053] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.336246336/ 0x24a1f083] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.336252221/ 0x24a1f0f5] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.336253992/ 0x24a1f117] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.336255711/ 0x24a1f138] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.336257325/ 0x24a1f156] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.336258888/ 0x24a1f175] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.336260450/ 0x24a1f193] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.336262013/ 0x24a1f1b1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.336263523/ 0x24a1f1cd] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.340551596/ 0x24a33369] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.340555554/ 0x24a333b5] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.342751127/ 0x24a3d862] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.342755138/ 0x24a3d8ad] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.342757690/ 0x24a3d8de] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.342763679/ 0x24a3d951] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.342765450/ 0x24a3d973] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.342767013/ 0x24a3d991] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.342768679/ 0x24a3d9b1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.342770242/ 0x24a3d9ce] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.342771804/ 0x24a3d9ed] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.342773367/ 0x24a3da0b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.342774825/ 0x24a3da27] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.347054252/ 0x24a51b1c] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.349292221/ 0x24a5c2f7] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.349296284/ 0x24a5c343] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.349298836/ 0x24a5c374] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.349304981/ 0x24a5c3ea] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.349306804/ 0x24a5c40d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.349308315/ 0x24a5c42b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.349309981/ 0x24a5c449] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.349311492/ 0x24a5c467] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.349313106/ 0x24a5c485] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.349314617/ 0x24a5c4a3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.349316075/ 0x24a5c4bf] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.353675554/ 0x24a70bb5] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.353679409/ 0x24a70bff] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.355972846/ 0x24a7b802] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.355976492/ 0x24a7b847] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.355979513/ 0x24a7b881] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.355985711/ 0x24a7b8f8] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.355987481/ 0x24a7b91a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.355989096/ 0x24a7b939] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.355990763/ 0x24a7b959] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.355992429/ 0x24a7b979] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.355993992/ 0x24a7b997] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.355995554/ 0x24a7b9b5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.355997169/ 0x24a7b9d4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.360290398/ 0x24a8fbd2] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.362450659/ 0x24a99dda] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.362455242/ 0x24a99e2f] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.362457898/ 0x24a99e62] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.362464044/ 0x24a99ed8] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.362465815/ 0x24a99efa] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.362467325/ 0x24a99f18] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.362468992/ 0x24a99f37] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.362470554/ 0x24a99f55] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.362472117/ 0x24a99f73] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.362473784/ 0x24a99f93] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.362475294/ 0x24a99faf] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.366760919/ 0x24aae11d] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.366764877/ 0x24aae168] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.369042534/ 0x24ab8c3d] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.369046492/ 0x24ab8c87] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.369048992/ 0x24ab8cb7] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.369054877/ 0x24ab8d29] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.369057013/ 0x24ab8d51] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.369058575/ 0x24ab8d6f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.369060190/ 0x24ab8d8e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.369061856/ 0x24ab8dae] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.369063471/ 0x24ab8dcd] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.369065034/ 0x24ab8deb] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.369066492/ 0x24ab8e07] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.373357013/ 0x24accfd1] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.375511127/ 0x24ad7162] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.375515450/ 0x24ad71b3] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.375518002/ 0x24ad71e4] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.375523940/ 0x24ad7257] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.375525763/ 0x24ad7279] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.375527429/ 0x24ad7299] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.375529044/ 0x24ad72b8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.375530607/ 0x24ad72d6] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.375532325/ 0x24ad72f7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.375533888/ 0x24ad7315] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.375535294/ 0x24ad7330] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.379818679/ 0x24aeb471] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.379822482/ 0x24aeb4ba] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.382095919/ 0x24af5f3f] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.382100086/ 0x24af5f8c] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.382102638/ 0x24af5fbd] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.382108627/ 0x24af6031] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.382110450/ 0x24af6053] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.382112117/ 0x24af6073] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.382113784/ 0x24af6092] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.382115346/ 0x24af60b0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.382116909/ 0x24af60cf] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.382118419/ 0x24af60ec] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.382119929/ 0x24af6109] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.386405294/ 0x24b0a270] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.388560346/ 0x24b14412] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.388564461/ 0x24b14460] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.388567013/ 0x24b14491] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.388572950/ 0x24b14503] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.388574721/ 0x24b14525] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.388576284/ 0x24b14543] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.388577898/ 0x24b14562] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.388579461/ 0x24b14580] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.388581075/ 0x24b1459f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.388582586/ 0x24b145bc] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.388584096/ 0x24b145d9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.392871388/ 0x24b28765] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.392875554/ 0x24b287b5] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.395075919/ 0x24b32cbe] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.395079982/ 0x24b32d0a] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.395082482/ 0x24b32d3a] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.395088419/ 0x24b32dad] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.395090398/ 0x24b32dd2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.395092065/ 0x24b32df2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.395093679/ 0x24b32e11] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.395095242/ 0x24b32e2f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.395096857/ 0x24b32e4e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.395098419/ 0x24b32e6c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.395099877/ 0x24b32e88] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.399385607/ 0x24b46ff6] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.401592377/ 0x24b51579] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.401597065/ 0x24b515d2] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.401599513/ 0x24b51601] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.401605555/ 0x24b51675] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.401607430/ 0x24b5169a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.401608992/ 0x24b516b7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.401610659/ 0x24b516d7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.401612221/ 0x24b516f4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.401613784/ 0x24b51713] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.401615502/ 0x24b51734] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.401616961/ 0x24b51750] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.406276805/ 0x24b674cd] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.406281596/ 0x24b67529] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.408652221/ 0x24b726f6] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.408656752/ 0x24b7274c] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.408659669/ 0x24b72786] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.408666284/ 0x24b72803] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.408668159/ 0x24b72827] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.408669773/ 0x24b72847] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.408671440/ 0x24b72866] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.408673002/ 0x24b72884] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.408674617/ 0x24b728a2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.408676284/ 0x24b728c3] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.408677742/ 0x24b728df] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.412970919/ 0x24b86adc] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.415136127/ 0x24b90d42] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.415140398/ 0x24b90d92] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.415143055/ 0x24b90dc6] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.415149096/ 0x24b90e39] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.415150867/ 0x24b90e5b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.415152534/ 0x24b90e7b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.415154148/ 0x24b90e9a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.415155711/ 0x24b90eb8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.415157325/ 0x24b90ed7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.415158992/ 0x24b90ef7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.415160502/ 0x24b90f14] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.419440450/ 0x24ba5013] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.419444461/ 0x24ba5060] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.421736648/ 0x24bafc4c] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.421740763/ 0x24bafc99] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.421743159/ 0x24bafcc7] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.421749200/ 0x24bafd3b] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.421750971/ 0x24bafd5d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.421752586/ 0x24bafd7c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.421754200/ 0x24bafd9b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.421755867/ 0x24bafdbb] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.421757482/ 0x24bafdda] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.421759148/ 0x24bafdfa] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.421760815/ 0x24bafe1a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.426043107/ 0x24bc3f46] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.428197638/ 0x24bce0df] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.428201648/ 0x24bce12a] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.428204200/ 0x24bce15b] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.428210138/ 0x24bce1cd] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.428212013/ 0x24bce1f1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.428213575/ 0x24bce20f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.428215190/ 0x24bce22e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.428216857/ 0x24bce24e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.428218471/ 0x24bce26c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.428220034/ 0x24bce28a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.428221492/ 0x24bce2a6] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.432515398/ 0x24be24b2] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.432519617/ 0x24be2503] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.434744982/ 0x24becbec] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.434749669/ 0x24becc44] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.434752378/ 0x24becc78] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.434758367/ 0x24becceb] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.434760190/ 0x24becd0e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.434761753/ 0x24becd2c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.434763367/ 0x24becd4b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.434765086/ 0x24becd6b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.434766648/ 0x24becd8a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.434768211/ 0x24becda8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.434769669/ 0x24becdc4] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.439055763/ 0x24c00f3a] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.441263003/ 0x24c0b4c6] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.441267534/ 0x24c0b51b] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.441270138/ 0x24c0b54d] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.441276075/ 0x24c0b5bf] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.441277898/ 0x24c0b5e2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.441279461/ 0x24c0b600] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.441281075/ 0x24c0b61f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.441282794/ 0x24c0b640] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.441284461/ 0x24c0b660] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.441286128/ 0x24c0b680] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.441287742/ 0x24c0b69e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.445573680/ 0x24c1f812] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.445577794/ 0x24c1f860] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.447855555/ 0x24c2a337] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.447859669/ 0x24c2a384] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.447862482/ 0x24c2a3bb] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.447868471/ 0x24c2a42e] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.447870242/ 0x24c2a450] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.447871805/ 0x24c2a46d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.447873471/ 0x24c2a48c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.447875138/ 0x24c2a4ad] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.447876700/ 0x24c2a4cb] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.447878315/ 0x24c2a4e9] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.447879721/ 0x24c2a505] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.452178888/ 0x24c3e775] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 28.454332378/ 0x24c488f9] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.454336388/ 0x24c48945] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.454338992/ 0x24c48977] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.454345034/ 0x24c489eb] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.454346857/ 0x24c48a0e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.454348523/ 0x24c48a2e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.454350138/ 0x24c48a4d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.454351805/ 0x24c48a6d] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.454353367/ 0x24c48a8b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.454355034/ 0x24c48aab] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.454356648/ 0x24c48aca] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.458636076/ 0x24c5cbbf] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by PARF_MSI_GEN
[ 28.458639826/ 0x24c5cc07] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: MSI_EXIT_L1SS has been cleared
[ 28.460921857/ 0x24c6772e] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 28.460925555/ 0x24c67775] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 28.460928419/ 0x24c677ac] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 28.460934721/ 0x24c67825] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 28.460936753/ 0x24c6784c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 28.460938315/ 0x24c6786a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 28.460940086/ 0x24c6788b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 28.460941753/ 0x24c678ac] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 28.460943367/ 0x24c678ca] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 28.460944930/ 0x24c678e8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 28.460946388/ 0x24c67905] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 28.465243471/ 0x24c7bb4d] DBG2:ep_pcie_core_trigger_msi: PCIe V1711211: try to trigger MSI by direct address write as well
[ 31.006419000/ 0x27b03777] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 31.006422958/ 0x27b037c3] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 31.006425979/ 0x27b037fd] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 31.006432333/ 0x27b03877] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 31.006434208/ 0x27b0389b] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 31.006435979/ 0x27b038bd] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 31.006437750/ 0x27b038de] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 31.006439417/ 0x27b038ff] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 31.006441135/ 0x27b03920] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 31.006442906/ 0x27b03942] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 31.006444521/ 0x27b03961] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 31.008890667/ 0x27b0f0d7] ep_pcie_handle_dstate_change_irq: PCIe V1711211: No. 2 change to D3 state
[ 31.008893740/ 0x27b0f112] ep_pcie_notify_event: PCIe V1711211: Callback client for event 2
[ 32.651998380/ 0x299251ec] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 32.661535724/ 0x29951d39] ep_pcie_core_issue_inband_pme: PCIe V1711211: request to assert inband wake
[ 32.661538640/ 0x29951d71] ep_pcie_core_issue_inband_pme: PCIe V1711211: completed assert for inband wake
[ 32.661540255/ 0x29951d8f] ep_pcie_core_wakeup_host_internal: PCIe V1711211: Set wake pending : 1 and return ; perst is de-asserted; D3hot is set
[ 35.122094325/ 0x2c65fb1d] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 35.132264221/ 0x2c68f5dc] ep_pcie_core_issue_inband_pme: PCIe V1711211: request to assert inband wake
[ 35.132267190/ 0x2c68f614] ep_pcie_core_issue_inband_pme: PCIe V1711211: completed assert for inband wake
[ 35.132268700/ 0x2c68f631] ep_pcie_core_wakeup_host_internal: PCIe V1711211: Set wake pending : 1 and return ; perst is de-asserted; D3hot is set
[ 37.664039072/ 0x2f4eb0f9] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 37.674527249/ 0x2f51c395] ep_pcie_core_issue_inband_pme: PCIe V1711211: request to assert inband wake
[ 37.674530114/ 0x2f51c3cc] ep_pcie_core_issue_inband_pme: PCIe V1711211: completed assert for inband wake
[ 37.674531572/ 0x2f51c3e8] ep_pcie_core_wakeup_host_internal: PCIe V1711211: Set wake pending : 1 and return ; perst is de-asserted; D3hot is set
[ 40.306238716/ 0x3254c5f1] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 40.315775643/ 0x32579137] ep_pcie_core_issue_inband_pme: PCIe V1711211: request to assert inband wake
[ 40.315778664/ 0x32579170] ep_pcie_core_issue_inband_pme: PCIe V1711211: completed assert for inband wake
[ 40.315780122/ 0x3257918c] ep_pcie_core_wakeup_host_internal: PCIe V1711211: Set wake pending : 1 and return ; perst is de-asserted; D3hot is set
[ 42.746296223/ 0x351fa242] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 42.756870755/ 0x3522bb58] ep_pcie_core_issue_inband_pme: PCIe V1711211: request to assert inband wake
[ 42.756873671/ 0x3522bb90] ep_pcie_core_issue_inband_pme: PCIe V1711211: completed assert for inband wake
[ 42.756875130/ 0x3522bbac] ep_pcie_core_wakeup_host_internal: PCIe V1711211: Set wake pending : 1 and return ; perst is de-asserted; D3hot is set
[ 45.178265345/ 0x37e81ff5] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 45.188823262/ 0x37eb37cd] ep_pcie_core_issue_inband_pme: PCIe V1711211: request to assert inband wake
[ 45.188829772/ 0x37eb384a] ep_pcie_core_issue_inband_pme: PCIe V1711211: completed assert for inband wake
[ 45.188834512/ 0x37eb38a4] ep_pcie_core_wakeup_host_internal: PCIe V1711211: Set wake pending : 1 and return ; perst is de-asserted; D3hot is set
[ 47.605619936/ 0x3aaf438d] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 47.615707280/ 0x3ab2381e] ep_pcie_core_issue_inband_pme: PCIe V1711211: request to assert inband wake
[ 47.615714676/ 0x3ab238a8] ep_pcie_core_issue_inband_pme: PCIe V1711211: completed assert for inband wake
[ 47.615719780/ 0x3ab2390a] ep_pcie_core_wakeup_host_internal: PCIe V1711211: Set wake pending : 1 and return ; perst is de-asserted; D3hot is set
[ 50.046287339/ 0x3d7a4d97] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 50.056293537/ 0x3d7d3c12] ep_pcie_core_issue_inband_pme: PCIe V1711211: request to assert inband wake
[ 50.056296923/ 0x3d7d3c4e] ep_pcie_core_issue_inband_pme: PCIe V1711211: completed assert for inband wake
[ 50.056298537/ 0x3d7d3c6d] ep_pcie_core_wakeup_host_internal: PCIe V1711211: Set wake pending : 1 and return ; perst is de-asserted; D3hot is set
[ 52.475513440/ 0x4041fd8c] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 52.485694638/ 0x4044f924] ep_pcie_core_issue_inband_pme: PCIe V1711211: request to assert inband wake
[ 52.485698805/ 0x4044f973] ep_pcie_core_issue_inband_pme: PCIe V1711211: completed assert for inband wake
[ 52.485701461/ 0x4044f9a7] ep_pcie_core_wakeup_host_internal: PCIe V1711211: Set wake pending : 1 and return ; perst is de-asserted; D3hot is set
[ 54.905694281/ 0x4309f51b] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 54.915750844/ 0x430ce759] ep_pcie_core_issue_inband_pme: PCIe V1711211: request to assert inband wake
[ 54.915754229/ 0x430ce79a] ep_pcie_core_issue_inband_pme: PCIe V1711211: completed assert for inband wake
[ 54.915755688/ 0x430ce7b6] ep_pcie_core_wakeup_host_internal: PCIe V1711211: Set wake pending : 1 and return ; perst is de-asserted; D3hot is set
[ 57.335664757/ 0x45d1dce4] ep_pcie_core_wakeup_host_internal: PCIe V1711211: request to assert WAKE# when in D3hot
[ 57.345708507/ 0x45d4ce2c] ep_pcie_core_issue_inband_pme: PCIe V1711211: request to assert inband wake
[ 57.345711528/ 0x45d4ce66] ep_pcie_core_issue_inband_pme: PCIe V1711211: completed assert for inband wake
[ 57.345713143/ 0x45d4ce85] ep_pcie_core_wakeup_host_internal: PCIe V1711211: Set wake pending : 1 and return ; perst is de-asserted; D3hot is set
[ 90.129558764/ 0x6b5972fc] ep_pcie_handle_dstate_change_irq: PCIe V1711211: No. 2 change to D0 state, clearing wake pending:0
[ 90.129572305/ 0x6b5973fc] ep_pcie_notify_event: PCIe V1711211: Callback client for event 1
[ 90.142502722/ 0x6b5d3dc8] ep_pcie_handle_bme_irq: PCIe V1711211: No. 3 BME IRQ
[ 90.142513087/ 0x6b5d3e8a] ep_pcie_handle_bme_irq: PCIe V1711211:BME is set again after the enumeration has completed; callback client for link ready
[ 90.142522462/ 0x6b5d3f3e] ep_pcie_notify_event: PCIe V1711211: Client does not register for event 32
[ 90.142540222/ 0x6b5d4093] DBG2:ep_pcie_handle_bme_irq: PCIe V1711211: Allow L1 after BME is set
[ 90.152101368/ 0x6b600da8] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 90.152112410/ 0x6b600e7e] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 90.152125483/ 0x6b600f79] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 90.152145743/ 0x6b6010fe] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 90.152154076/ 0x6b60119e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 90.152161055/ 0x6b601224] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 90.152168347/ 0x6b6012ae] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 90.152175274/ 0x6b601333] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 90.152182305/ 0x6b6013bb] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 90.152189337/ 0x6b601441] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 90.152195951/ 0x6b6014c0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 90.152216055/ 0x6b601643] DBG2:ep_pcie_core_config_outbound_iatu: PCIe V1711211: No outbound iATU config is needed since active config is enabled
[ 90.152225430/ 0x6b6016f7] ep_pcie_core_config_outbound_iatu: PCIe V1711211: data_start:0x0; data_end:0xfffffffe; data_tgt_lower:0x0; data_tgt_upper:0x0; ctrl_start:0x0; ctrl_end:0xfffffffe; ctrl_tgt_lower:0x0; ctrl_tgt_upper:0x0
[ 90.152247410/ 0x6b60189e] ep_pcie_core_config_outbound_iatu: PCIe V1711211: iATU configuration case No. 2: included
[ 90.152255274/ 0x6b601934] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:3; lower:0x0; limit:0xfffffffe; target_lower:0x0; target_upper:0x0
[ 90.152275170/ 0x6b601ab3] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 90.152282983/ 0x6b601b48] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 90.152289597/ 0x6b601bc7] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x0
[ 90.152296108/ 0x6b601c43] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 90.152302878/ 0x6b601cc5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0xffffffff
[ 90.152309753/ 0x6b601d49] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0x0
[ 90.152316003/ 0x6b601dc2] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 90.152322253/ 0x6b601e3a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 90.152344337/ 0x6b601fe3] ep_pcie_core_config_db_routing: PCIe V1711211: DB routing info: chdb_cfg.base:0x64; chdb_cfg.end:0x6e; erdb_cfg.base:0x4; erdb_cfg.end:0x5; chdb_cfg.tgt_addr:0x3e28000; erdb_cfg.tgt_addr:0x3e28848
[ 90.170405326/ 0x6b656a6d] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 90.170409076/ 0x6b656ab5] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 90.170412149/ 0x6b656aef] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 90.170418503/ 0x6b656b6a] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 90.170420431/ 0x6b656b8f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 90.170422097/ 0x6b656baf] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 90.170423868/ 0x6b656bd1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 90.170425587/ 0x6b656bf1] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 90.170427306/ 0x6b656c12] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 90.170428972/ 0x6b656c33] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 90.170430431/ 0x6b656c4f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 91.423934914/ 0x6cd4a927] ep_pcie_core_register_event: PCIe V1711211: Event 0x20 is registered
[ 91.423961216/ 0x6cd4ab21] ep_pcie_core_get_linkstatus: PCIe V1711211: PCIe link is up and BME is enabled; current SW link status:2
[ 91.423969653/ 0x6cd4abc1] ep_pcie_core_register_event: PCIe V1711211: Event 0x31f is registered
[ 91.424239341/ 0x6cd4c000] ep_pcie_core_get_linkstatus: PCIe V1711211: PCIe link is up and BME is enabled; current SW link status:2
[ 91.473629549/ 0x6ce33842] ep_pcie_handle_dstate_change_irq: PCIe V1711211: No. 3 change to D3 state
[ 91.473637362/ 0x6ce338db] ep_pcie_notify_event: PCIe V1711211: Callback client for event 2
[ 91.747734185/ 0x6d33863a] ep_pcie_handle_perst_irq: PCIe V1711211: No. 1 PERST assertion
[ 91.747762831/ 0x6d338851] ep_pcie_notify_event: PCIe V1711211: Callback client for event 4
[ 91.748071685/ 0x6d339f70] ep_pcie_core_disable_endpoint: PCIe V1711211
[ 91.748079394/ 0x6d33a003] ep_pcie_core_disable_endpoint: PCIe V1711211: shut down the link
[ 91.748095696/ 0x6d33a13c] DBG2:ep_pcie_core_disable_endpoint: PCIe V1711211: Set pcie_disconnect_req during D3_COLD
[ 91.748105956/ 0x6d33a203] ep_pcie_pipe_clk_deinit: PCIe V1711211
[ 91.748148977/ 0x6d33a53e] ep_pcie_clk_deinit: PCIe V1711211
[ 91.748575019/ 0x6d33c535] ep_pcie_clk_deinit: PCIe V1711211: relinquish bus bandwidth returns 0
[ 91.748645487/ 0x6d33ca7e] ep_pcie_vreg_deinit: PCIe V1711211
[ 91.748654758/ 0x6d33cb2c] ep_pcie_vreg_deinit: Vreg vreg-mx is being disabled
[ 91.748664967/ 0x6d33cbf0] ep_pcie_vreg_deinit: PCIe V1711211: Removing vote for vreg-mx.
[ 91.748799185/ 0x6d33d605] ep_pcie_vreg_deinit: Vreg vreg-cx is being disabled
[ 91.748810383/ 0x6d33d6d7] ep_pcie_vreg_deinit: Vreg vreg-0p9 is being disabled
[ 91.748970331/ 0x6d33e2d6] ep_pcie_vreg_deinit: Vreg vreg-1p8 is being disabled
[ 91.749122571/ 0x6d33ee41] ep_pcie_core_disable_endpoint: PCIe V1711211: Released wakelock
[ 91.833692571/ 0x6d4cb4fb] ep_pcie_suspend_noirq: PCIe V1711211: Perst asserted, allow suspend
[ 92.474390906/ 0x7b12fbfc] ep_pcie_suspend_noirq: PCIe V1711211: Perst asserted, allow suspend
[ 92.475193146/ 0x8f8e7997] ep_pcie_handle_perst_irq: PCIe V1711211: Acquired wakelock
[ 92.475207677/ 0x8f8e7aa0] ep_pcie_handle_perst_irq: PCIe V1711211: No. 1 PERST deassertion
[ 92.475269968/ 0x8f8e7f4a] ep_pcie_notify_event: PCIe V1711211: Callback client for event 8
[ 92.475317729/ 0x8f8e82de] ep_pcie_core_enable_endpoint: PCIe V1711211: options input are 0x2
[ 92.475321427/ 0x8f8e8325] ep_pcie_vreg_init: PCIe V1711211
[ 92.475323823/ 0x8f8e8352] ep_pcie_vreg_init: PCIe V1711211: Vreg vreg-1p8 is being enabled
[ 92.475366010/ 0x8f8e867c] ep_pcie_handle_perst_irq: PCIe V1711211: No. 2 PERST assertion
[ 92.475369343/ 0x8f8e86bc] ep_pcie_notify_event: PCIe V1711211: Callback client for event 4
[ 92.475682833/ 0x8f8e9e40] ep_pcie_vreg_init: PCIe V1711211: Vreg vreg-0p9 is being enabled
[ 92.475770854/ 0x8f8ea4db] ep_pcie_vreg_init: PCIe V1711211: Vreg vreg-cx is being enabled
[ 92.475775593/ 0x8f8ea534] ep_pcie_vreg_init: PCIe V1711211: Vreg vreg-mx is being enabled
[ 92.475805229/ 0x8f8ea76d] ep_pcie_clk_init: PCIe V1711211
[ 92.475950698/ 0x8f8eb259] ep_pcie_clk_init: PCIe V1711211: set bus bandwidth
[ 92.475966062/ 0x8f8eb37e] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_cfg_ahb_clk
[ 92.475972573/ 0x8f8eb3fa] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_mstr_axi_clk
[ 92.475978198/ 0x8f8eb466] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_slv_axi_clk
[ 92.475998771/ 0x8f8eb5f2] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_aux_clk
[ 92.476014239/ 0x8f8eb71a] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_ldo
[ 92.476040073/ 0x8f8eb90c] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_sleep_clk
[ 92.476046218/ 0x8f8eb980] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_slv_q2a_axi_clk
[ 92.476050489/ 0x8f8eb9d2] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_pipe_clk_mux
[ 92.476053718/ 0x8f8eba10] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_pipe_clk_ext_src
[ 92.476056635/ 0x8f8eba48] ep_pcie_clk_init: PCIe V1711211: enable clk pcie_0_ref_clk_src
[ 92.476060125/ 0x8f8eba8b] ep_pcie_core_enable_endpoint: TCSR PERST_EN value before configure:0x0
[ 92.476063093/ 0x8f8ebac4] ep_pcie_core_enable_endpoint: TCSR PERST_EN value after configure:0x0
[ 92.476068041/ 0x8f8ebb23] ep_pcie_reset_init: PCIe V1711211: successfully asserted reset for pcie_core_reset
[ 92.476073562/ 0x8f8ebb8d] ep_pcie_reset_init: After Reset assert pcie_core_reset
[ 92.477120958/ 0x8f8f0a27] ep_pcie_reset_init: PCIe V1711211: successfully deasserted reset for pcie_core_reset
[ 92.477133354/ 0x8f8f0b09] ep_pcie_reset_init: After Reset de-assert pcie_core_reset
[ 92.477146531/ 0x8f8f0c09] ep_pcie_reset_init: PCIe V1711211: successfully asserted reset for pcie_phy_reset
[ 92.477152052/ 0x8f8f0c70] ep_pcie_reset_init: After Reset assert pcie_phy_reset
[ 92.478191583/ 0x8f8f5a6c] ep_pcie_reset_init: PCIe V1711211: successfully deasserted reset for pcie_phy_reset
[ 92.478201687/ 0x8f8f5b29] ep_pcie_reset_init: After Reset de-assert pcie_phy_reset
[ 92.478341323/ 0x8f8f65a2] ep_pcie_core_enable_endpoint: PCIe V1711211: options input are 0xc
[ 92.478344812/ 0x8f8f65e5] ep_pcie_core_enable_endpoint: TCSR PERST_EN value before configure:0x0
[ 92.478347573/ 0x8f8f661b] ep_pcie_core_enable_endpoint: TCSR PERST_EN value after configure:0x0
[ 92.503568354/ 0x8f96c9b3] ep_pcie_handle_perst_irq: PCIe V1711211: No. 2 PERST deassertion
[ 92.503610073/ 0x8f96cccc] ep_pcie_core_enable_endpoint: PCIe V1711211: number of PERST retries:5
[ 92.503618875/ 0x8f96cd73] ep_pcie_phy_init: PCIe V1711211: Unexpected phy version 8 is caught
[ 92.503631896/ 0x8f96ce6f] ep_pcie_phy_init: PCIe V1711211: PHY V8: process the sequence specified by DT
[ 92.503687469/ 0x8f96d298] ep_pcie_pipe_clk_init: PCIe V1711211
[ 92.503713458/ 0x8f96d48b] ep_pcie_pipe_clk_init: PCIe V1711211: enabled pipe clk pcie_pipe_clk
[ 92.503716635/ 0x8f96d4c8] ep_pcie_core_enable_endpoint: PCIe V1711211: waiting for phy ready...
[ 92.509634135/ 0x8f98909e] ep_pcie_core_enable_endpoint: PCIe V1711211: number of PHY retries:1
[ 92.509642208/ 0x8f989134] ep_pcie_core_enable_endpoint: PCIe V1711211: PCIe PHY is ready
[ 92.509649864/ 0x8f9891c7] ep_pcie_core_init: PCIe V1711211
[ 92.509652052/ 0x8f9891f1] ep_pcie_core_init: PCIe V1711211: WRITING TO BDF TO SID
[ 92.509655594/ 0x8f989235] ep_pcie_core_init: PCIe V1711211: FINISHED WRITING BDF TO SID
[ 92.509658875/ 0x8f989274] ep_pcie_core_init: PCIe V1711211: Updating SOC reset offset with val:0xb01b8
[ 92.509662573/ 0x8f9892ba] ep_pcie_core_init: PCIe V1711211:SOC reset offset val:0xb01b8
[ 92.509669135/ 0x8f989338] DBG2:ep_pcie_core_init: PCIe V1711211: Clear disconn_req after D3_COLD
[ 92.509674344/ 0x8f98939c] ep_pcie_core_init: PCIe V1711211: DBI base:0x40000000
[ 92.509677364/ 0x8f9893d6] ep_pcie_core_init: PCIe V1711211: configure MSB of ATU base for flipping and LSB as 0x40001000
[ 92.509681323/ 0x8f989423] ep_pcie_core_init: PCIe V1711211: LSB of ATU base:0x40001000
[ 92.509689135/ 0x8f9894b8] ep_pcie_core_init: Initial: CLASS_CODE_REVISION_ID:0xff000000; HDR_TYPE:0x0
[ 92.509725906/ 0x8f98977c] ep_pcie_core_init: [FOX] pcie-subsys-id:0xe0d9105b
[ 92.509737052/ 0x8f989851] ep_pcie_core_init: After program: CLASS_CODE_REVISION_ID:0xd400000; HDR_TYPE:0x10; L1SUB_CAPABILITY:0x461f; PARF_SYS_CTRL:0x2000365c
[ 92.509741948/ 0x8f9898ae] ep_pcie_bar_init: PCIe V1711211: BAR mask to program is 0xfff
[ 92.509751948/ 0x8f98996e] ep_pcie_core_init: PCIe V1711211: PCIE20_PARF_INT_ALL_MASK:0x210e
[ 92.509756844/ 0x8f9899cc] ep_pcie_config_mmio: Initial version of MMIO is:0x1000000
[ 92.509759187/ 0x8f9899f9] ep_pcie_config_mmio: PCIe V1711211: MMIO already initialized, return
[ 92.509762052/ 0x8f989a31] ep_pcie_config_inbound_iatu: PCIe V1711211: BAR0 is 0x4; MMIO[0x1c03000-0x1c03fff]
[ 92.509768250/ 0x8f989aa7] ep_pcie_config_inbound_iatu: PCIe V1711211: Inbound iATU configuration
[ 92.509771166/ 0x8f989adf] ep_pcie_config_inbound_iatu: PCIE20_IATU_I_CTRL1(0):0x0
[ 92.509773458/ 0x8f989b0b] ep_pcie_config_inbound_iatu: PCIE20_IATU_I_LTAR(0):0x1c03000
[ 92.509776010/ 0x8f989b3b] ep_pcie_config_inbound_iatu: PCIE20_IATU_I_UTAR(0):0x0
[ 92.509778250/ 0x8f989b67] ep_pcie_config_inbound_iatu: PCIE20_IATU_I_CTRL2(0):0xc0000000
[ 92.509781166/ 0x8f989b9f] ep_pcie_core_enable_endpoint: PCIe V1711211: check if link is up
[ 92.536632729/ 0x8fa0797e] ep_pcie_handle_linkup_irq: PCIe V1711211: No. 2 linkup IRQ
[ 92.536646010/ 0x8fa07a80] ep_pcie_confirm_linkup: PCIe V1711211: device ID and vendor ID are 0xe0d9105b
[ 92.536650594/ 0x8fa07ad4] ep_pcie_core_enable_endpoint: PCIe V1711211: link is up after 4 checkings (4 ms)
[ 92.536657469/ 0x8fa07b59] ep_pcie_core_enable_endpoint: PCIe V1711211: link initialized for LE PCIe endpoint
[ 92.542025437/ 0x8fa20df3] ep_pcie_core_toggle_wake_gpio: PCIe V1711211: deassert PCIe WAKE# after PERST# is deasserted
[ 92.542033250/ 0x8fa20e8a] ep_pcie_core_toggle_wake_gpio: PCIe V1711211: No. 0 to de-assert PCIe WAKE#; perst is de-asserted; D3hot is not received, WAKE GPIO state:1
[ 92.542039187/ 0x8fa20efa] ep_pcie_core_enable_endpoint: PCIe V1711211: EP_PCIE_OPT_ENUM_ASYNC is true
[ 92.542042104/ 0x8fa20f31] ep_pcie_core_enable_endpoint: PCIe V1711211: PCIe link is up but BME is disabled; current SW link status:1
[ 92.542067364/ 0x8fa21116] ep_pcie_notify_event: PCIe V1711211: Callback client for event 8
[ 92.550541219/ 0x8fa48ca0] ep_pcie_handle_dstate_change_irq: PCIe V1711211: No. 3 change to D0 state, clearing wake pending:0
[ 92.550545333/ 0x8fa48cef] ep_pcie_notify_event: PCIe V1711211: Callback client for event 1
[ 92.561605542/ 0x8fa7ca73] ep_pcie_core_disable_endpoint: PCIe V1711211
[ 92.561608562/ 0x8fa7caae] ep_pcie_core_disable_endpoint: PCIe V1711211: PERST is de-asserted, exiting disable
[ 92.582958875/ 0x8fae0bf3] ep_pcie_core_get_linkstatus: PCIe V1711211: PCIe link is up but BME is disabled; current SW link status:1
[ 92.583095906/ 0x8fae163b] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x18a7005
[ 92.583102104/ 0x8fae16b2] ep_pcie_core_get_msi_config: PCIe V1711211: MSI is not enabled yet
[ 111.621972996/ 0xa577e20d] ep_pcie_handle_bme_irq: PCIe V1711211: No. 4 BME IRQ
[ 111.621983308/ 0xa577e2ce] ep_pcie_handle_bme_irq: PCIe V1711211:BME is set again after the enumeration has completed; callback client for link ready
[ 111.621992631/ 0xa577e382] ep_pcie_notify_event: PCIe V1711211: Client does not register for event 32
[ 111.622010704/ 0xa577e4dc] DBG2:ep_pcie_handle_bme_irq: PCIe V1711211: Allow L1 after BME is set
[ 111.831330705/ 0xa5b537dc] ep_pcie_core_get_msi_config: PCIe V1711211: MSI CAP:0x1bb7005
[ 111.831342059/ 0xa5b538b6] ep_pcie_core_get_msi_config: PCIe V1711211: MSI info: lower:0xfee30040; upper:0x0; data:0x0
[ 111.831355080/ 0xa5b539b1] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:1; lower:0x40002000; limit:0x40002fff; target_lower:0xfee30040; target_upper:0x0
[ 111.831375288/ 0xa5b53b35] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 111.831383777/ 0xa5b53bd8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 111.831390652/ 0xa5b53c5c] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0x40002000
[ 111.831398048/ 0xa5b53ce8] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x100
[ 111.831404819/ 0xa5b53d6a] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0x40002fff
[ 111.831411798/ 0xa5b53df0] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 111.831418673/ 0xa5b53e74] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 111.831425340/ 0xa5b53ef5] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 111.831432996/ 0xa5b53f88] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: region:4; lower:0xfee30040; limit:0xfee3103f; target_lower:0xfee30040; target_upper:0x0
[ 111.831452527/ 0xa5b54100] ep_pcie_config_outbound_iatu_entry: PCIe V1711211: Outbound iATU configuration
[ 111.831460132/ 0xa5b54191] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL1:0x0
[ 111.831466694/ 0xa5b5420f] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LBAR:0xfee30000
[ 111.831473830/ 0xa5b54297] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UBAR:0x0
[ 111.831480027/ 0xa5b5430e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LAR:0xfee31fff
[ 111.831486902/ 0xa5b54392] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_LTAR:0xfee30040
[ 111.831493673/ 0xa5b54414] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_UTAR:0x0
[ 111.831499975/ 0xa5b5448e] ep_pcie_config_outbound_iatu_entry: PCIE20_IATU_O_CTRL2:0x80000000
[ 111.831506538/ 0xa5b5450c] ep_pcie_core_get_msi_config: PCIe V1711211: Conf iATU for IPA MSI info: lower:0xfee30040; upper:0x0
[ 111.831533361/ 0xa5b54710] ep_pcie_core_config_db_routing: PCIe V1711211: DB routing info: chdb_cfg.base:0x64; chdb_cfg.end:0x6e; erdb_cfg.base:0x2; erdb_cfg.end:0x3; chdb_cfg.tgt_addr:0x3e28000; erdb_cfg.tgt_addr:0x3e28848
~ # cat /sys/kernel/debug/ipc_logging/mhi/log
[ 15.471733692/ 0x15e90a12] [0x0 mhi_dev_resume_init_w[ 337.415552] debug_log: buffer size 955 < 1020
[ 337.419704] debug_log: buffer size 955 < 1020
ith_link_up] PCIe event=0x0
[ 15.771136974/ 0x1640c15e] [0x0 mhi_dev_recover] mhi_syserr = 0x0
[ 15.820496974/ 0x164f3754] [0x0 mhi_dev_resume_mmio_mhi_init] Registering with IPA
[ 15.820505620/ 0x164f37f7] [0x0 mhi_dev_sm_init] ENTRY
[ 15.820753224/ 0x164f4a8b] [0x0 mhi_dev_sm_init] EXIT
[ 15.820756818/ 0x164f4ad0] [0x0 mhi_dev_sm_set_ready] ENTRY
[ 15.820760933/ 0x164f4b1d] [0x0 mhi_sm_mmio_set_mhistatus] ENTRY
[ 15.820762912/ 0x164f4b43] [0x0 mhi_sm_mmio_set_mhistatus] set MHISTATUS to READY mode
[ 15.820765881/ 0x164f4b7c] [0x0 mhi_sm_mmio_set_mhistatus] EXIT
[ 15.820767704/ 0x164f4b9f] [0x0 mhi_dev_sm_set_ready] EXIT
[ 16.970577811/ 0x17a02762] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x200, reset:0
[ 16.970581718/ 0x17a027ac] [0x0 mhi_dev_enable] state:2
[ 16.970591665/ 0x17a0286b] [0x0 mhi_dev_cache_host_cfg] Number of Event rings : 6, HW Event rings : 2
[ 16.970608540/ 0x17a029af] [0x0 mhi_dev_cache_host_cfg] MEM_ALLOC: size:17280 RING_ALLOC
[ 16.970826978/ 0x17a03a1b] [0x0 mhi_dev_ring_init] initializing all rings
[ 16.970845259/ 0x17a03b76] [0x0 mhi_dev_read_from_host_ipa] device 0xb011391c8b9d5000 <<-- host 0x10009aa7000, size 44
[ 16.970927082/ 0x17a04198] [0x0 mhi_dev_read_from_host_ipa] device 0xb084d9308b9d6000 <<-- host 0x10009b52000, size 264
[ 16.972592134/ 0x17a0be7e] [0x0 mhi_dev_cache_host_cfg] cmd ring_base:0x1c68000, rp:0x1c68000, wp:0x1c68000
[ 16.972604270/ 0x17a0bf62] [0x0 mhi_dev_cache_host_cfg] ev ring_base:0x9b53000, rp:0x9b53000, wp:0x9b533f0
[ 16.972729582/ 0x17a0c8ce] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 0
[ 16.972736613/ 0x17a0c94a] [0x0 mhi_dev_cache_ring] new wr_offset 0
[ 16.972738957/ 0x17a0c977] [0x0 mhi_ring_start] ctx ring_base:0x1c68000, rp:0x1c68000, wp:0x1c68000
[ 16.972799686/ 0x17a0ce04] [0x0 mhi_pcie_config_db_routing] Event rings 0x6 => er_base 0x4, er_end 5
[ 16.972809426/ 0x17a0cec0] [0x0 mhi_hwc_init] Event rings 0x6 => er_base 0x4, er_end 5
[ 16.972812447/ 0x17a0cefa] [0x0 mhi_hwc_init] MMIO Addr 0x1c03000, MSI config: U:0x0 L: 0xfee30040 D: 0x0
[ 16.975737811/ 0x17a1aa61] [0x0 mhi_hwc_cb] HW ch uC is ready event=0x0
[ 16.975780311/ 0x17a1ad91] [0x0 mhi_enable_int] Enable ctrl and cmdb interrupts
[ 16.975797811/ 0x17a1aee2] [0x0 mhi_dev_isr] mhi irq triggered
[ 16.975808853/ 0x17a1afb5] [0x0 mhi_hwc_cb] Device in M0 State
[ 16.975895676/ 0x17a1b63a] [0x0 mhi_dev_scheduler] processing ctrl interrupt with 5
[ 16.975900207/ 0x17a1b68f] [0x0 mhi_dev_scheduler] BHI_IMGTXDB = 0x0
[ 16.975903072/ 0x17a1b6c7] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x200, reset:0
[ 16.975930415/ 0x17a1b8d4] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 16.978193228/ 0x17a26289] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_M0_STATE
[ 16.978204061/ 0x17a2635a] [0x0 mhi_dev_notify_sm_event] Got M0, wait until resume is done
[ 16.978209895/ 0x17a263ca] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 16.985765988/ 0x17a49a84] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_M0_STATE event, current states: READY & D0_STATE
[ 16.985778645/ 0x17a49b73] [0x0 mhi_sm_prepare_resume] ENTRY
[ 16.985843280/ 0x17a4a049] [0x0 mhi_pcie_config_db_routing] Event rings 0x6 => er_base 0x4, er_end 5
[ 16.985853280/ 0x17a4a10a] [0x0 mhi_sm_mmio_set_mhistatus] ENTRY
[ 16.985855103/ 0x17a4a12e] [0x0 mhi_sm_mmio_set_mhistatus] set MHISTATUS.MHISTATE to M0 state
[ 16.985858020/ 0x17a4a165] [0x0 mhi_sm_mmio_set_mhistatus] EXIT
[ 16.986187395/ 0x17a4ba28] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 16.986195572/ 0x17a4bab9] [0x0 mhi_ring_start] ctx ring_base:0x9b53000, rp:0x9b53000, wp:0x9b533f0
[ 16.986200103/ 0x17a4bb0d] [0x0 mhi_dev_send_multiple_tr_events] Flushing 0 cmpl events of cmd ring
[ 16.986205780/ 0x17a4bb7a] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:1, local wr_ofst 63
[ 16.986208436/ 0x17a4bbad] [0x0 mhi_dev_cache_ring] new wr_offset 63
[ 16.986210676/ 0x17a4bbd8] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x0, new-offset 0x1
[ 16.986214009/ 0x17a4bc18] [0x0 mhi_dev_add_element] evnt ptr : 0x9a0b1082f52
[ 16.986216561/ 0x17a4bc48] [0x0 mhi_dev_add_element] evnt len : 0x0
[ 16.986218228/ 0x17a4bc68] [0x0 mhi_dev_add_element] evnt code :0x2
[ 16.986220103/ 0x17a4bc8c] [0x0 mhi_dev_add_element] evnt type :0x20
[ 16.986221718/ 0x17a4bcac] [0x0 mhi_dev_add_element] evnt ch_id :0x0
[ 16.986224530/ 0x17a4bce2] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53000, size 16
[ 16.986246613/ 0x17a4be8a] [0x0 mhi_dev_send_multiple_tr_events] Caching rp 9b53010 for rd offset 1
[ 16.986290624/ 0x17a4c1d8] [0x0 mhi_dev_send_multiple_tr_events] ev.rp = 9b53010 for 1
[ 16.986293384/ 0x17a4c20c] [0x0 mhi_dev_send_multiple_tr_events] RP phy addr = 0x8b9db008 for ring rd offset 1
[ 16.986296301/ 0x17a4c244] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 16.986332291/ 0x17a4c4f7] [0x0 mhi_dev_schedule_msi_ipa] Sending MSI 1 to 0xfee30040 as data = 0x1 for cmd ack ereq flush_num 0
[ 16.986335728/ 0x17a4c539] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100fee30040, size 4
[ 16.986343280/ 0x17a4c5ca] [0x0 mhi_dev_send_multiple_tr_events] Flushing 0 cmpl events of cmd ring
[ 16.986346509/ 0x17a4c608] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:1, local wr_ofst 63
[ 16.986348593/ 0x17a4c630] [0x0 mhi_dev_cache_ring] new wr_offset 63
[ 16.986350259/ 0x17a4c650] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x1, new-offset 0x2
[ 16.986352916/ 0x17a4c683] [0x0 mhi_dev_add_element] evnt ptr : 0x9a0b1082f52
[ 16.986354478/ 0x17a4c6a1] [0x0 mhi_dev_add_element] evnt len : 0x0
[ 16.986355936/ 0x17a4c6bd] [0x0 mhi_dev_add_element] evnt code :0x2
[ 16.986357291/ 0x17a4c6d7] [0x0 mhi_dev_add_element] evnt type :0x40
[ 16.986358697/ 0x17a4c6f2] [0x0 mhi_dev_add_element] evnt ch_id :0x0
[ 16.986360155/ 0x17a4c70f] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53010, size 16
[ 16.986366666/ 0x17a4c78b] [0x0 mhi_dev_send_multiple_tr_events] Caching rp 9b53020 for rd offset 2
[ 16.986368905/ 0x17a4c7b6] [0x0 mhi_dev_send_multiple_tr_events] ev.rp = 9b53020 for 1
[ 16.986370884/ 0x17a4c7dc] [0x0 mhi_dev_send_multiple_tr_events] RP phy addr = 0x8b9db010 for ring rd offset 2
[ 16.986373020/ 0x17a4c805] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 16.986402395/ 0x17a4ca39] [0x0 mhi_dev_schedule_msi_ipa] Sending MSI 1 to 0xfee30040 as data = 0x1 for cmd ack ereq flush_num 0
[ 16.986405103/ 0x17a4ca6d] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100fee30040, size 4
[ 16.986410832/ 0x17a4cadb] [0x0 mhi_sm_prepare_resume] EXIT
[ 16.986413905/ 0x17a4cb16] [0x0 mhi_sm_dev_event_manager] EXIT
[ 16.986436353/ 0x17a4ccc6] [0x0 mhi_dev_event_buf_completion_cb] Event buf dma completed for flush req 0
[ 16.986443801/ 0x17a4cd54] [0x0 mhi_dev_event_rd_offset_completion_cb] Rd offset dma completed for flush req 0
[ 16.986448228/ 0x17a4cda9] [0x0 mhi_dev_cmd_event_msi_cb] MSI completed for flush req 0
[ 16.986452238/ 0x17a4cdf9] [0x0 mhi_dev_event_buf_completion_cb] Event buf dma completed for flush req 0
[ 16.986455780/ 0x17a4ce3a] [0x0 mhi_dev_event_rd_offset_completion_cb] Rd offset dma completed for flush req 0
[ 16.986459009/ 0x17a4ce78] [0x0 mhi_dev_cmd_event_msi_cb] MSI completed for flush req 0
[ 16.986478072/ 0x17a4cfe6] [0x0 mhi_dev_notify_sm_event] EXIT
[ 16.993787916/ 0x17a6f443] [0x0 mhi_dev_isr] mhi irq triggered
[ 16.995853541/ 0x17a78f27] [0x0 mhi_dev_scheduler] processing cmd db interrupt with 6
[ 16.996357968/ 0x17a7b4e7] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:0 wp:0
[ 16.996363176/ 0x17a7b54b] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68010
[ 16.996366978/ 0x17a7b591] [0x0 mhi_dev_cache_ring] caching ring_id:0, start 0, end 1
[ 16.996370520/ 0x17a7b5d5] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b9d7000 <<-- host 0x10001c68000, size 16
[ 16.996456874/ 0x17a7bc52] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:0 with wr:1
[ 16.996460780/ 0x17a7bc9b] [0x0 mhi_dev_process_ring] Processing ring_id:0 rd_offset:0, wr_offset:1
[ 16.996464738/ 0x17a7bce6] [0x0 mhi_dev_process_cmd_ring] for ch_id:46 and cmd 18
[ 16.996467655/ 0x17a7bd1e] [0x0 mhi_dev_process_cmd_ring] received start cmd for ch_id:46
[ 16.996472238/ 0x17a7bd76] [0x0 mhi_dev_read_from_host_ipa] device 0xb137a7508b9d87e8 <<-- host 0x100e79807e8, size 44
[ 16.996614478/ 0x17a7c829] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:53, local wr_ofst 0
[ 16.996621353/ 0x17a7c8a8] [0x0 mhi_dev_cache_ring] new wr_offset 0
[ 16.996623905/ 0x17a7c8d6] [0x0 mhi_ring_start] ctx ring_base:0xa30e000, rp:0xa30e000, wp:0xa30e000
[ 16.996750832/ 0x17a7d267] [0x0 mhi_dev_cache_ring] not caching event ring_id:3
[ 16.996756509/ 0x17a7d2c9] [0x0 mhi_ring_start] ctx ring_base:0x9a1b000, rp:0x9a1b000, wp:0x9a1b3f0
[ 16.996760520/ 0x17a7d315] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e79807e8, size 4
[ 17.011170780/ 0x17ac0bf4] [0x0 mhi_dev_send_cmd_comp_event] evt cmd comp ptr :1c68000
[ 17.011186249/ 0x17ac0d09] [0x0 mhi_dev_send_multiple_tr_events] Flushing 0 cmpl events of cmd ring
[ 17.011193541/ 0x17ac0d8f] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 17.011196561/ 0x17ac0dc9] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x2, new-offset 0x3
[ 17.011200363/ 0x17ac0e12] [0x0 mhi_dev_add_element] evnt ptr : 0x1c68000
[ 17.011202707/ 0x17ac0e3f] [0x0 mhi_dev_add_element] evnt len : 0x0
[ 17.011204374/ 0x17ac0e5f] [0x0 mhi_dev_add_element] evnt code :0x1
[ 17.011206145/ 0x17ac0e81] [0x0 mhi_dev_add_element] evnt type :0x21
[ 17.011207759/ 0x17ac0ea0] [0x0 mhi_dev_add_element] evnt ch_id :0x0
[ 17.011210624/ 0x17ac0ed7] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53020, size 16
[ 17.011233384/ 0x17ac108e] [0x0 mhi_dev_send_multiple_tr_events] Caching rp 9b53030 for rd offset 3
[ 17.011284374/ 0x17ac1460] [0x0 mhi_dev_send_multiple_tr_events] ev.rp = 9b53030 for 1
[ 17.011287082/ 0x17ac1493] [0x0 mhi_dev_send_multiple_tr_events] RP phy addr = 0x8b9db018 for ring rd offset 3
[ 17.011289738/ 0x17ac14c5] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 17.011326978/ 0x17ac1793] [0x0 mhi_dev_schedule_msi_ipa] Sending MSI 1 to 0xfee30040 as data = 0x1 for cmd ack ereq flush_num 0
[ 17.011331197/ 0x17ac17e2] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100fee30040, size 4
[ 17.011339895/ 0x17ac1889] [0x0 mhi_ctrl_state_info] idx:46, ctrl:1
[ 17.011342707/ 0x17ac18c0] [0x0 mhi_ctrl_state_info] idx:47, ctrl:0
[ 17.011344530/ 0x17ac18e2] [0x0 mhi_ctrl_state_info] idx:46, ctrl:1
[ 17.011398072/ 0x17ac1ce7] [0x0 mhi_dev_event_buf_completion_cb] Event buf dma completed for flush req 0
[ 17.011405988/ 0x17ac1d7e] [0x0 mhi_dev_event_rd_offset_completion_cb] Rd offset dma completed for flush req 0
[ 17.011410676/ 0x17ac1dd8] [0x0 mhi_dev_cmd_event_msi_cb] MSI completed for flush req 0
[ 17.011669530/ 0x17ac3147] [0x0 mhi_dev_isr] mhi irq triggered
[ 17.040105989/ 0x17b48611] [0x0 mhi_dev_scheduler] processing cmd db interrupt with 6
[ 17.040138020/ 0x17b48868] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:1 wp:1
[ 17.040143541/ 0x17b488cf] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68020
[ 17.040147447/ 0x17b4891a] [0x0 mhi_dev_cache_ring] caching ring_id:0, start 1, end 2
[ 17.040151093/ 0x17b48961] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b9d7010 <<-- host 0x10001c68010, size 16
[ 17.050128020/ 0x17b775b3] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:1 with wr:2
[ 17.050140624/ 0x17b77699] [0x0 mhi_dev_process_ring] Processing ring_id:0 rd_offset:1, wr_offset:2
[ 17.050144843/ 0x17b776eb] [0x0 mhi_dev_process_cmd_ring] for ch_id:47 and cmd 18
[ 17.050148853/ 0x17b77736] [0x0 mhi_dev_process_cmd_ring] received start cmd for ch_id:47
[ 17.050154062/ 0x17b7779a] [0x0 mhi_dev_read_from_host_ipa] device 0xb137a7508b9d8814 <<-- host 0x100e7980814, size 44
[ 17.060271249/ 0x17ba6e68] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:54, local wr_ofst 0
[ 17.060277864/ 0x17ba6ee7] [0x0 mhi_dev_cache_ring] new wr_offset 0
[ 17.060280624/ 0x17ba6f17] [0x0 mhi_ring_start] ctx ring_base:0x9511000, rp:0x9511000, wp:0x9511000
[ 17.060423541/ 0x17ba79db] [0x0 mhi_dev_cache_ring] not caching event ring_id:4
[ 17.060428697/ 0x17ba7a34] [0x0 mhi_ring_start] ctx ring_base:0x9a1c000, rp:0x9a1c000, wp:0x9a1c3f0
[ 17.060432864/ 0x17ba7a82] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e7980814, size 4
[ 17.061530416/ 0x17baccdc] [0x0 mhi_dev_send_cmd_comp_event] evt cmd comp ptr :1c68010
[ 17.061538124/ 0x17bacd67] [0x0 mhi_dev_send_multiple_tr_events] Flushing 0 cmpl events of cmd ring
[ 17.061543593/ 0x17bacdd0] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 17.061546041/ 0x17bacdff] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x3, new-offset 0x4
[ 17.061549374/ 0x17bace3f] [0x0 mhi_dev_add_element] evnt ptr : 0x1c68010
[ 17.061551457/ 0x17bace67] [0x0 mhi_dev_add_element] evnt len : 0x0
[ 17.061553228/ 0x17bace89] [0x0 mhi_dev_add_element] evnt code :0x1
[ 17.061554999/ 0x17baceaa] [0x0 mhi_dev_add_element] evnt type :0x21
[ 17.061556614/ 0x17baceca] [0x0 mhi_dev_add_element] evnt ch_id :0x0
[ 17.061559009/ 0x17bacef8] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53030, size 16
[ 17.061574895/ 0x17bad02c] [0x0 mhi_dev_send_multiple_tr_events] Caching rp 9b53040 for rd offset 4
[ 17.061612395/ 0x17bad2f9] [0x0 mhi_dev_send_multiple_tr_events] ev.rp = 9b53040 for 1
[ 17.061614999/ 0x17bad32b] [0x0 mhi_dev_send_multiple_tr_events] RP phy addr = 0x8b9db020 for ring rd offset 4
[ 17.061617655/ 0x17bad35e] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 17.061654634/ 0x17bad624] [0x0 mhi_dev_schedule_msi_ipa] Sending MSI 1 to 0xfee30040 as data = 0x1 for cmd ack ereq flush_num 0
[ 17.061658593/ 0x17bad670] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100fee30040, size 4
[ 17.061667447/ 0x17bad71a] [0x0 mhi_ctrl_state_info] idx:47, ctrl:1
[ 17.061670364/ 0x17bad752] [0x0 mhi_ctrl_state_info] idx:47, ctrl:1
[ 17.061672134/ 0x17bad775] [0x0 mhi_ctrl_state_info] idx:46, ctrl:1
[ 17.061679791/ 0x17bad807] [0x0 mhi_ctrl_state_info] idx:46, ctrl:1
[ 17.061682395/ 0x17bad839] [0x0 mhi_dev_alloc_evt_buf_evt_req] ch_id:46 evt buf size is 64
[ 17.061689530/ 0x17bad8c2] [0x0 mhi_ctrl_state_info] idx:47, ctrl:1
[ 17.061691718/ 0x17bad8ed] [0x0 mhi_dev_alloc_evt_buf_evt_req] ch_id:47 evt buf size is 64
[ 17.063000468/ 0x17bb3b1e] [0x0 mhi_dev_isr] mhi irq triggered
[ 17.070462395/ 0x17bd6ac1] [0x0 mhi_dev_event_buf_completion_cb] Event buf dma completed for flush req 0
[ 17.070474843/ 0x17bd6bab] [0x0 mhi_dev_event_rd_offset_completion_cb] Rd offset dma completed for flush req 0
[ 17.070479635/ 0x17bd6c04] [0x0 mhi_dev_cmd_event_msi_cb] MSI completed for flush req 0
[ 17.070499739/ 0x17bd6d8b] [0x0 mhi_dev_scheduler] processing cmd db interrupt with 6
[ 17.070520364/ 0x17bd6f15] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:2 wp:2
[ 17.070525832/ 0x17bd6f7b] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68030
[ 17.070529322/ 0x17bd6fbe] [0x0 mhi_dev_cache_ring] caching ring_id:0, start 2, end 3
[ 17.070532968/ 0x17bd7004] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b9d7020 <<-- host 0x10001c68020, size 16
[ 17.080107551/ 0x17c03e25] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:2 with wr:3
[ 17.080118749/ 0x17c03ef4] [0x0 mhi_dev_process_ring] Processing ring_id:0 rd_offset:2, wr_offset:3
[ 17.080123072/ 0x17c03f46] [0x0 mhi_dev_process_cmd_ring] for ch_id:100 and cmd 18
[ 17.080126614/ 0x17c03f8b] [0x0 mhi_dev_process_cmd_ring] received start cmd for ch_id:100
[ 17.111843489/ 0x17c98a4e] [0x0 mhi_dev_send_cmd_comp_event] evt cmd comp ptr :1c68020
[ 17.111848176/ 0x17c98aa8] [0x0 mhi_dev_send_multiple_tr_events] Flushing 0 cmpl events of cmd ring
[ 17.111855103/ 0x17c98b2d] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 17.111857760/ 0x17c98b60] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x4, new-offset 0x5
[ 17.111861458/ 0x17c98ba7] [0x0 mhi_dev_add_element] evnt ptr : 0x1c68020
[ 17.111863801/ 0x17c98bd4] [0x0 mhi_dev_add_element] evnt len : 0x0
[ 17.111865416/ 0x17c98bf3] [0x0 mhi_dev_add_element] evnt code :0x1
[ 17.111867187/ 0x17c98c14] [0x0 mhi_dev_add_element] evnt type :0x21
[ 17.111868853/ 0x17c98c35] [0x0 mhi_dev_add_element] evnt ch_id :0x0
[ 17.111871666/ 0x17c98c6b] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53040, size 16
[ 17.111890208/ 0x17c98dcf] [0x0 mhi_dev_send_multiple_tr_events] Caching rp 9b53050 for rd offset 5
[ 17.111934374/ 0x17c9911f] [0x0 mhi_dev_send_multiple_tr_events] ev.rp = 9b53050 for 1
[ 17.111936978/ 0x17c99151] [0x0 mhi_dev_send_multiple_tr_events] RP phy addr = 0x8b9db028 for ring rd offset 5
[ 17.111939530/ 0x17c99182] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 17.111976926/ 0x17c99450] [0x0 mhi_dev_schedule_msi_ipa] Sending MSI 1 to 0xfee30040 as data = 0x1 for cmd ack ereq flush_num 0
[ 17.111980676/ 0x17c99498] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100fee30040, size 4
[ 17.115743905/ 0x17caaed7] [0x0 mhi_dev_isr] mhi irq triggered
[ 17.115778385/ 0x17cab16c] [0x0 mhi_dev_event_buf_completion_cb] Event buf dma completed for flush req 0
[ 17.115784739/ 0x17cab1e6] [0x0 mhi_dev_event_rd_offset_completion_cb] Rd offset dma completed for flush req 0
[ 17.115789114/ 0x17cab23a] [0x0 mhi_dev_cmd_event_msi_cb] MSI completed for flush req 0
[ 17.115806874/ 0x17cab394] [0x0 mhi_dev_scheduler] processing cmd db interrupt with 6
[ 17.115821458/ 0x17cab4a7] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:3 wp:3
[ 17.115826197/ 0x17cab502] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68040
[ 17.115829374/ 0x17cab53f] [0x0 mhi_dev_cache_ring] caching ring_id:0, start 3, end 4
[ 17.115832499/ 0x17cab57b] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b9d7030 <<-- host 0x10001c68030, size 16
[ 17.116899062/ 0x17cb0585] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:3 with wr:4
[ 17.116906510/ 0x17cb0609] [0x0 mhi_dev_process_ring] Processing ring_id:0 rd_offset:3, wr_offset:4
[ 17.116910833/ 0x17cb065d] [0x0 mhi_dev_process_cmd_ring] for ch_id:101 and cmd 18
[ 17.116914322/ 0x17cb069e] [0x0 mhi_dev_process_cmd_ring] received start cmd for ch_id:101
[ 17.141561510/ 0x17d23f28] [0x0 mhi_dev_send_cmd_comp_event] evt cmd comp ptr :1c68030
[ 17.141566666/ 0x17d23f8b] [0x0 mhi_dev_send_multiple_tr_events] Flushing 0 cmpl events of cmd ring
[ 17.141572656/ 0x17d23ffe] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 17.141575260/ 0x17d24030] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x5, new-offset 0x6
[ 17.141578697/ 0x17d24073] [0x0 mhi_dev_add_element] evnt ptr : 0x1c68030
[ 17.141580937/ 0x17d2409c] [0x0 mhi_dev_add_element] evnt len : 0x0
[ 17.141582551/ 0x17d240bc] [0x0 mhi_dev_add_element] evnt code :0x1
[ 17.141584270/ 0x17d240dd] [0x0 mhi_dev_add_element] evnt type :0x21
[ 17.141585937/ 0x17d240fd] [0x0 mhi_dev_add_element] evnt ch_id :0x0
[ 17.141588749/ 0x17d24133] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53050, size 16
[ 17.141603958/ 0x17d24257] [0x0 mhi_dev_send_multiple_tr_events] Caching rp 9b53060 for rd offset 6
[ 17.141637864/ 0x17d244e3] [0x0 mhi_dev_send_multiple_tr_events] ev.rp = 9b53060 for 1
[ 17.141640468/ 0x17d24514] [0x0 mhi_dev_send_multiple_tr_events] RP phy addr = 0x8b9db030 for ring rd offset 6
[ 17.141643020/ 0x17d24545] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 17.141679531/ 0x17d24802] [0x0 mhi_dev_schedule_msi_ipa] Sending MSI 1 to 0xfee30040 as data = 0x1 for cmd ack ereq flush_num 0
[ 17.141683541/ 0x17d24850] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100fee30040, size 4
[ 17.145510572/ 0x17d36757] [0x0 mhi_dev_event_buf_completion_cb] Event buf dma completed for flush req 0
[ 17.145516562/ 0x17d367c9] [0x0 mhi_dev_event_rd_offset_completion_cb] Rd offset dma completed for flush req 0
[ 17.145521093/ 0x17d36823] [0x0 mhi_dev_cmd_event_msi_cb] MSI completed for flush req 0
[ 19.639118028/ 0x1aadf3f9] [0x0 mhi_dev_isr] mhi irq triggered
[ 19.640081049/ 0x1aae3c28] [0x0 mhi_dev_scheduler] processing ctrl interrupt with 5
[ 19.640087142/ 0x1aae3c95] [0x0 mhi_dev_scheduler] BHI_IMGTXDB = 0x0
[ 19.640089903/ 0x1aae3cc9] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x500, reset:0
[ 19.640117976/ 0x1aae3ee4] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 19.642381882/ 0x1aaee8af] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_M3_STATE
[ 19.642392090/ 0x1aaee973] [0x0 mhi_dev_notify_sm_event] EXIT
[ 19.642397767/ 0x1aaee9e5] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 19.649243497/ 0x1ab0eb4e] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_M3_STATE event, current states: M0 & D0_STATE
[ 19.649250007/ 0x1ab0ebcb] [0x0 mhi_sm_prepare_suspend] Switching event:5
[ 19.649252090/ 0x1ab0ebf3] [0x0 mhi_sm_prepare_suspend] ENTRY
[ 19.649254069/ 0x1ab0ec19] [0x0 mhi_sm_prepare_suspend] Switching state from 2 state with event:5
[ 19.649263757/ 0x1ab0ecd4] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e79807e8, size 4
[ 19.650352247/ 0x1ab13e7d] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e7980814, size 4
[ 19.774903028/ 0x1ad5bbc5] [0x0 mhi_sm_mmio_set_mhistatus] ENTRY
[ 19.774905580/ 0x1ad5bbf7] [0x0 mhi_sm_mmio_set_mhistatus] set MHISTATUS.MHISTATE to M3 state
[ 19.774908966/ 0x1ad5bc37] [0x0 mhi_sm_mmio_set_mhistatus] EXIT
[ 19.774912976/ 0x1ad5bc84] [0x0 mhi_dev_send_multiple_tr_events] Flushing 0 cmpl events of cmd ring
[ 19.774918601/ 0x1ad5bcf1] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 19.774921257/ 0x1ad5bd22] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x6, new-offset 0x7
[ 19.774924695/ 0x1ad5bd65] [0x0 mhi_dev_add_element] evnt ptr : 0x200000005
[ 19.774926934/ 0x1ad5bd90] [0x0 mhi_dev_add_element] evnt len : 0x0
[ 19.774928549/ 0x1ad5bdaf] [0x0 mhi_dev_add_element] evnt code :0x5
[ 19.774930320/ 0x1ad5bdd0] [0x0 mhi_dev_add_element] evnt type :0x20
[ 19.774931987/ 0x1ad5bdf1] [0x0 mhi_dev_add_element] evnt ch_id :0x0
[ 19.774934799/ 0x1ad5be27] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53060, size 16
[ 19.774950632/ 0x1ad5bf57] [0x0 mhi_dev_send_multiple_tr_events] Caching rp 9b53070 for rd offset 7
[ 19.774987612/ 0x1ad5c21d] [0x0 mhi_dev_send_multiple_tr_events] ev.rp = 9b53070 for 1
[ 19.774990164/ 0x1ad5c24e] [0x0 mhi_dev_send_multiple_tr_events] RP phy addr = 0x8b9db038 for ring rd offset 7
[ 19.774992820/ 0x1ad5c281] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 19.775029226/ 0x1ad5c53c] [0x0 mhi_dev_schedule_msi_ipa] Sending MSI 1 to 0xfee30040 as data = 0x1 for cmd ack ereq flush_num 0
[ 19.775032872/ 0x1ad5c582] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100fee30040, size 4
[ 19.775039226/ 0x1ad5c5fe] [0x0 mhi_sm_prepare_suspend] Disable IPA with ipa_dma_disable()
[ 19.777557143/ 0x1ad682d4] [0x0 mhi_dev_sm_pcie_handler] ENTRY
[ 19.777559539/ 0x1ad68302] [0x0 mhi_dev_sm_pcie_handler] received: EP_PCIE_PM_D3_HOT_EVENT
[ 19.777564903/ 0x1ad68369] [0x0 mhi_dev_sm_pcie_handler] Disable MHI IRQ during D3 HOT
[ 19.777832143/ 0x1ad69774] [0x0 mhi_dev_sm_pcie_handler] Hold wake for D3_HOT event
[ 19.777839122/ 0x1ad697fa] [0x0 mhi_dev_sm_pcie_handler] EXIT
[ 19.777868028/ 0x1ad69a27] [0x0 mhi_dev_event_buf_completion_cb] Event buf dma completed for flush req 0
[ 19.777874539/ 0x1ad69aa3] [0x0 mhi_dev_event_rd_offset_completion_cb] Rd offset dma completed for flush req 0
[ 19.777878757/ 0x1ad69af3] [0x0 mhi_dev_cmd_event_msi_cb] MSI completed for flush req 0
[ 19.790181049/ 0x1ada35a1] [0x0 mhi_sm_prepare_suspend] IPA disable fail cnt:0
[ 19.820100632/ 0x1ae2f9a2] [0x0 mhi_sm_prepare_suspend] IPA DMA successfully disabled
[ 19.820107768/ 0x1ae2fa20] [0x0 mhi_sm_prepare_suspend] EXIT
[ 19.820112560/ 0x1ae2fa7d] [0x0 mhi_dev_pm_relax] releasing mhi wakelock
[ 19.820117351/ 0x1ae2fad8] [0x0 mhi_sm_dev_event_manager] EXIT
[ 19.820123132/ 0x1ae2fb47] [0x0 mhi_sm_pcie_event_manager] ENTRY
[ 19.825490424/ 0x1ae48dd4] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D3_HOT_EVENT event, current states: M3 and D0_STATE
[ 19.825496622/ 0x1ae48e4a] [0x0 mhi_sm_pcie_event_manager] Release wake for D3_HOT event
[ 19.825499226/ 0x1ae48e7c] [0x0 mhi_sm_pcie_event_manager] EXIT
[ 22.473998609/ 0x1dec7bfe] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 22.474008661/ 0x1dec7cb2] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 22.474013141/ 0x1dec7d07] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 22.474017047/ 0x1dec7d52] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 22.474020745/ 0x1dec7d99] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 22.474024599/ 0x1dec7de3] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 22.474028557/ 0x1dec7e2f] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 22.474032516/ 0x1dec7e7b] [0x0 mhi_ctrl_state_info] idx:20, ctrl:0
[ 22.474036734/ 0x1dec7ecc] [0x0 mhi_ctrl_state_info] idx:21, ctrl:0
[ 22.474040849/ 0x1dec7f1b] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 22.474044651/ 0x1dec7f64] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 22.474048609/ 0x1dec7fb0] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 22.474052568/ 0x1dec7ffc] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 27.759799511/ 0x23f90f01] [0x0 mhi_dev_sm_pcie_handler] ENTRY
[ 27.759802480/ 0x23f90f3c] [0x0 mhi_dev_sm_pcie_handler] received: EP_PCIE_PM_D0_EVENT
[ 27.759808782/ 0x23f90fb3] [0x0 mhi_dev_sm_pcie_handler] Enable MHI IRQ during D0
[ 27.759810709/ 0x23f90fd8] [0x0 mhi_dev_sm_pcie_handler] Hold wake for D0 change event
[ 27.759816178/ 0x23f91042] [0x0 mhi_dev_sm_pcie_handler] EXIT
[ 27.759825657/ 0x23f910f8] [0x0 mhi_sm_pcie_event_manager] ENTRY
[ 27.759863782/ 0x23f913d4] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D0_EVENT event, current states: M3 and D3_HOT_STATE
[ 27.759869980/ 0x23f9144a] [0x0 mhi_sm_pcie_event_manager] Release wake for D0 change event
[ 27.759874459/ 0x23f914a0] [0x0 mhi_sm_pcie_event_manager] EXIT
[ 27.771632115/ 0x23fc8674] [0x0 mhi_dev_isr] acquiring mhi wakelock in ISR
[ 27.771639042/ 0x23fc86f8] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.771651334/ 0x23fc87e5] [0x0 mhi_dev_scheduler] processing ctrl interrupt with 5
[ 27.771654355/ 0x23fc881e] [0x0 mhi_dev_scheduler] BHI_IMGTXDB = 0x0
[ 27.771656855/ 0x23fc884e] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x200, reset:0
[ 27.771677011/ 0x23fc89d2] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 27.773941386/ 0x23fd33a5] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_M0_STATE
[ 27.773950396/ 0x23fd3453] [0x0 mhi_dev_notify_sm_event] Got M0, wait until resume is done
[ 27.773955292/ 0x23fd34b2] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 27.780830240/ 0x23ff3853] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_M0_STATE event, current states: M3 & D0_STATE
[ 27.780837532/ 0x23ff38db] [0x0 mhi_sm_prepare_resume] ENTRY
[ 27.780898573/ 0x23ff3d71] [0x0 mhi_pcie_config_db_routing] Event rings 0x6 => er_base 0x4, er_end 5
[ 27.780908261/ 0x23ff3e29] [0x0 mhi_sm_mmio_set_mhistatus] ENTRY
[ 27.780910344/ 0x23ff3e51] [0x0 mhi_sm_mmio_set_mhistatus] set MHISTATUS.MHISTATE to M0 state
[ 27.780913261/ 0x23ff3e89] [0x0 mhi_sm_mmio_set_mhistatus] EXIT
[ 27.799200449/ 0x24049a13] [0x0 mhi_dev_send_multiple_tr_events] Flushing 0 cmpl events of cmd ring
[ 27.799206282/ 0x24049a84] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:1, local wr_ofst 5
[ 27.799208730/ 0x24049ab2] [0x0 mhi_dev_cache_ring] new wr_offset 5
[ 27.799211074/ 0x24049adf] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x7, new-offset 0x8
[ 27.799214459/ 0x24049b20] [0x0 mhi_dev_add_element] evnt ptr : 0x9a0b1082f52
[ 27.799216907/ 0x24049b4f] [0x0 mhi_dev_add_element] evnt len : 0x0
[ 27.799218521/ 0x24049b6e] [0x0 mhi_dev_add_element] evnt code :0x2
[ 27.799220292/ 0x24049b90] [0x0 mhi_dev_add_element] evnt type :0x20
[ 27.799221959/ 0x24049bb0] [0x0 mhi_dev_add_element] evnt ch_id :0x0
[ 27.799224771/ 0x24049be6] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53070, size 16
[ 27.799240032/ 0x24049d0e] [0x0 mhi_dev_send_multiple_tr_events] Caching rp 9b53080 for rd offset 8
[ 27.799273990/ 0x24049f97] [0x0 mhi_dev_send_multiple_tr_events] ev.rp = 9b53080 for 1
[ 27.799276751/ 0x24049fcc] [0x0 mhi_dev_send_multiple_tr_events] RP phy addr = 0x8b9db040 for ring rd offset 8
[ 27.799279459/ 0x2404a000] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.799315084/ 0x2404a2ac] [0x0 mhi_dev_schedule_msi_ipa] Sending MSI 1 to 0xfee30040 as data = 0x1 for cmd ack ereq flush_num 0
[ 27.799318834/ 0x2404a2f4] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100fee30040, size 4
[ 27.799330969/ 0x2404a3dd] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e79807e8, size 4
[ 27.799361386/ 0x2404a627] [0x0 mhi_dev_event_buf_completion_cb] Event buf dma completed for flush req 0
[ 27.799367271/ 0x2404a696] [0x0 mhi_dev_event_rd_offset_completion_cb] Rd offset dma completed for flush req 0
[ 27.799371907/ 0x2404a6ef] [0x0 mhi_dev_cmd_event_msi_cb] MSI completed for flush req 0
[ 27.801474563/ 0x240544a3] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e7980814, size 4
[ 27.803614355/ 0x2405e51f] [0x0 mhi_sm_prepare_resume] EXIT
[ 27.803618678/ 0x2405e574] [0x0 mhi_sm_dev_event_manager] EXIT
[ 27.803629042/ 0x2405e639] [0x0 mhi_dev_notify_sm_event] EXIT
[ 27.803642428/ 0x2405e73c] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.803653001/ 0x2405e805] [0x0 mhi_dev_scheduler] processing cmd db interrupt with 6
[ 27.803665553/ 0x2405e8f6] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:4 wp:4
[ 27.803669876/ 0x2405e948] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68050
[ 27.803673157/ 0x2405e987] [0x0 mhi_dev_cache_ring] caching ring_id:0, start 4, end 5
[ 27.803676490/ 0x2405e9c7] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b9d7040 <<-- host 0x10001c68040, size 16
[ 27.803723678/ 0x2405ed52] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:4 with wr:5
[ 27.803727271/ 0x2405ed96] [0x0 mhi_dev_process_ring] Processing ring_id:0 rd_offset:4, wr_offset:5
[ 27.803731074/ 0x2405eddf] [0x0 mhi_dev_process_cmd_ring] for ch_id:20 and cmd 18
[ 27.803733834/ 0x2405ee15] [0x0 mhi_dev_process_cmd_ring] received start cmd for ch_id:20
[ 27.803738105/ 0x2405ee66] [0x0 mhi_dev_read_from_host_ipa] device 0xb137a7508b9d8370 <<-- host 0x100e7980370, size 44
[ 27.804889199/ 0x240644c4] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:27, local wr_ofst 0
[ 27.804895292/ 0x24064530] [0x0 mhi_dev_cache_ring] new wr_offset 0
[ 27.804897428/ 0x24064559] [0x0 mhi_ring_start] ctx ring_base:0x184d000, rp:0x184d000, wp:0x184d000
[ 27.804902480/ 0x240645bb] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e7980370, size 4
[ 27.807039980/ 0x2406e60b] [0x0 mhi_dev_send_cmd_comp_event] evt cmd comp ptr :1c68040
[ 27.807044511/ 0x2406e661] [0x0 mhi_dev_send_multiple_tr_events] Flushing 0 cmpl events of cmd ring
[ 27.807048834/ 0x2406e6b5] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.807050969/ 0x2406e6dd] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x8, new-offset 0x9
[ 27.807053886/ 0x2406e716] [0x0 mhi_dev_add_element] evnt ptr : 0x1c68040
[ 27.807055709/ 0x2406e738] [0x0 mhi_dev_add_element] evnt len : 0x0
[ 27.807057271/ 0x2406e756] [0x0 mhi_dev_add_element] evnt code :0x1
[ 27.807058678/ 0x2406e771] [0x0 mhi_dev_add_element] evnt type :0x21
[ 27.807060240/ 0x2406e78f] [0x0 mhi_dev_add_element] evnt ch_id :0x0
[ 27.807062584/ 0x2406e7bc] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53080, size 16
[ 27.807071907/ 0x2406e870] [0x0 mhi_dev_send_multiple_tr_events] Caching rp 9b53090 for rd offset 9
[ 27.807094511/ 0x2406ea22] [0x0 mhi_dev_send_multiple_tr_events] ev.rp = 9b53090 for 1
[ 27.807096855/ 0x2406ea4e] [0x0 mhi_dev_send_multiple_tr_events] RP phy addr = 0x8b9db048 for ring rd offset 9
[ 27.807099251/ 0x2406ea7c] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.807133678/ 0x2406ed11] [0x0 mhi_dev_schedule_msi_ipa] Sending MSI 1 to 0xfee30040 as data = 0x1 for cmd ack ereq flush_num 0
[ 27.807137271/ 0x2406ed56] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100fee30040, size 4
[ 27.807268626/ 0x2406f739] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.809202115/ 0x2407883f] [0x0 mhi_dev_scheduler] processing cmd db interrupt with 6
[ 27.809229876/ 0x24078a49] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:5 wp:5
[ 27.809235240/ 0x24078aaf] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.809239407/ 0x24078aff] [0x0 mhi_dev_cache_ring] caching ring_id:0, start 5, end 6
[ 27.809242792/ 0x24078b44] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b9d7050 <<-- host 0x10001c68050, size 16
[ 27.809282011/ 0x24078e32] [0x0 mhi_dev_event_buf_completion_cb] Event buf dma completed for flush req 0
[ 27.809289199/ 0x24078ebb] [0x0 mhi_dev_event_rd_offset_completion_cb] Rd offset dma completed for flush req 0
[ 27.809294146/ 0x24078f1a] [0x0 mhi_dev_cmd_event_msi_cb] MSI completed for flush req 0
[ 27.809303365/ 0x24078fcd] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:5 with wr:6
[ 27.809306594/ 0x24079009] [0x0 mhi_dev_process_ring] Processing ring_id:0 rd_offset:5, wr_offset:6
[ 27.809310449/ 0x24079053] [0x0 mhi_dev_process_cmd_ring] for ch_id:21 and cmd 18
[ 27.809313209/ 0x24079089] [0x0 mhi_dev_process_cmd_ring] received start cmd for ch_id:21
[ 27.809317636/ 0x240790dd] [0x0 mhi_dev_read_from_host_ipa] device 0xb137a7508b9d839c <<-- host 0x100e798039c, size 44
[ 27.809477688/ 0x24079ce9] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:28, local wr_ofst 0
[ 27.809485865/ 0x24079d7b] [0x0 mhi_dev_cache_ring] new wr_offset 0
[ 27.809488001/ 0x24079da4] [0x0 mhi_ring_start] ctx ring_base:0x58cc000, rp:0x58cc000, wp:0x58cc000
[ 27.809492688/ 0x24079dfe] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e798039c, size 4
[ 27.811643209/ 0x24083f4a] [0x0 mhi_dev_send_cmd_comp_event] evt cmd comp ptr :1c68050
[ 27.811648261/ 0x24083fab] [0x0 mhi_dev_send_multiple_tr_events] Flushing 0 cmpl events of cmd ring
[ 27.811653730/ 0x24084012] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.811656490/ 0x24084047] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x9, new-offset 0xa
[ 27.811659824/ 0x24084087] [0x0 mhi_dev_add_element] evnt ptr : 0x1c68050
[ 27.811662063/ 0x240840b2] [0x0 mhi_dev_add_element] evnt len : 0x0
[ 27.811663782/ 0x240840d3] [0x0 mhi_dev_add_element] evnt code :0x1
[ 27.811665553/ 0x240840f4] [0x0 mhi_dev_add_element] evnt type :0x21
[ 27.811667167/ 0x24084114] [0x0 mhi_dev_add_element] evnt ch_id :0x0
[ 27.811669771/ 0x24084146] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53090, size 16
[ 27.811684407/ 0x24084260] [0x0 mhi_dev_send_multiple_tr_events] Caching rp 9b530a0 for rd offset 10
[ 27.811720344/ 0x24084511] [0x0 mhi_dev_send_multiple_tr_events] ev.rp = 9b530a0 for 1
[ 27.811722949/ 0x24084543] [0x0 mhi_dev_send_multiple_tr_events] RP phy addr = 0x8b9db050 for ring rd offset 10
[ 27.811725709/ 0x24084578] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.811761959/ 0x24084830] [0x0 mhi_dev_schedule_msi_ipa] Sending MSI 1 to 0xfee30040 as data = 0x1 for cmd ack ereq flush_num 0
[ 27.811765813/ 0x2408487a] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100fee30040, size 4
[ 27.811773574/ 0x2408490f] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.811778834/ 0x24084975] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 27.811781282/ 0x240849a4] [0x0 mhi_dev_alloc_evt_buf_evt_req] ch_id:20 evt buf size is 64
[ 27.811789094/ 0x24084a39] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.811791386/ 0x24084a65] [0x0 mhi_dev_alloc_evt_buf_evt_req] ch_id:21 evt buf size is 64
[ 27.811889771/ 0x240851d0] [0x0 mhi_dev_event_buf_completion_cb] Event buf dma completed for flush req 0
[ 27.811897480/ 0x2408525d] [0x0 mhi_dev_event_rd_offset_completion_cb] Rd offset dma completed for flush req 0
[ 27.811901959/ 0x240852b1] [0x0 mhi_dev_cmd_event_msi_cb] MSI completed for flush req 0
[ 27.812200032/ 0x2408690f] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.812904459/ 0x24089dea] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.812930605/ 0x24089fd8] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.812935396/ 0x2408a033] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.812939094/ 0x2408a079] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.812941751/ 0x2408a0ac] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.812943834/ 0x2408a0d4] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.812947115/ 0x2408a113] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.812949719/ 0x2408a146] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:0 wp:0
[ 27.812953521/ 0x2408a18e] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc070
[ 27.812956282/ 0x2408a1c2] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 0, end 7
[ 27.812975240/ 0x2408a330] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd000 <<-- host 0x100058cc000, size 112
[ 27.815073469/ 0x24094099] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:0 with wr:7
[ 27.815084563/ 0x24094165] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 27.815088157/ 0x240941a6] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:0
[ 27.815341282/ 0x240954a5] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.815349511/ 0x24095541] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c80000, size 52
[ 27.817528730/ 0x2409f8b2] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.817531490/ 0x2409f8e7] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0xa, new-offset 0xb
[ 27.817535240/ 0x2409f92f] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.817537219/ 0x2409f955] [0x0 mhi_dev_add_element] rd_ofset 11
[ 27.817539094/ 0x2409f979] [0x0 mhi_dev_add_element] type 34
[ 27.817541438/ 0x2409f9a6] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b530a0, size 16
[ 27.819672324/ 0x240a9979] [0x0 mhi_dev_send_event] ev.rp = 9b530b0 for 1
[ 27.819676751/ 0x240a99cc] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.821804459/ 0x240b3962] [0x0 mhi_dev_send_event] event sent:
[ 27.821808521/ 0x240b39b1] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc000
[ 27.821810865/ 0x240b39db] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.821812740/ 0x240b39ff] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.821814511/ 0x240b3a21] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.821816230/ 0x240b3a42] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.821923001/ 0x240b4246] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.821941594/ 0x240b43ab] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x300000
[ 27.821958157/ 0x240b44eb] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.821962167/ 0x240b4537] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.821965501/ 0x240b4574] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.821968001/ 0x240b45a4] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.821969719/ 0x240b45c5] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.821972480/ 0x240b45fa] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.821974876/ 0x240b4628] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:7
[ 27.821978365/ 0x240b466b] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc000
[ 27.821981126/ 0x240b46a0] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 7, end 0
[ 27.821984511/ 0x240b46e1] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd070 <<-- host 0x100058cc070, size 16
[ 27.822043417/ 0x240b4b4d] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:0
[ 27.822047115/ 0x240b4b94] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 27.822049511/ 0x240b4bc1] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 27.822054667/ 0x240b4c24] [0x0 mhi_dev_process_ring_pending] processing ring_id:27
[ 27.822056438/ 0x240b4c46] [0x0 mhi_dev_process_ring] Before wr update ring_id:27 rp:0 wp:0
[ 27.822059407/ 0x240b4c7f] [0x0 mhi_dev_update_wr_offset] ring_id:27 wr_offset from db 0x184d010
[ 27.822061959/ 0x240b4caf] [0x0 mhi_dev_cache_ring] caching ring_id:27, start 0, end 1
[ 27.822064251/ 0x240b4cdc] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4da000 <<-- host 0x1000184d000, size 16
[ 27.822079719/ 0x240b4e06] [0x0 mhi_dev_process_ring] After wp update ring_id:27 rp:0 with wr:1
[ 27.822083053/ 0x240b4e45] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x72f3480
[ 27.822084928/ 0x240b4e69] [0x0 mhi_dev_process_ring_element] TRE len : 0x34, rd_offset:0
[ 27.822088938/ 0x240b4eb6] [0x0 mhi_dev_read_channel] evtptr : 0x72f3480
[ 27.822091282/ 0x240b4ee3] [0x0 mhi_dev_read_channel] evntlen : 0x34, offset:0
[ 27.822093990/ 0x240b4f17] [0x0 mhi_dev_read_channel] user_buf_remaining 32768, ch->tre_size 52
[ 27.822096907/ 0x240b4f4f] [0x0 mhi_dev_read_channel] reading 52 bytes from ch_id:20
[ 27.822099824/ 0x240b4f88] [0x0 mhi_transfer_host_to_device_ipa] device 0x8b9c8000 <-- host 0x100072f3480, size 52
[ 27.824235188/ 0x240befb2] [0x0 mhi_dev_send_completion_event_async] Ch 20
[ 27.824239928/ 0x240bf00c] [0x0 mhi_dev_queue_transfer_completion] evnt ptr : 0x184d000
[ 27.824242480/ 0x240bf03a] [0x0 mhi_dev_queue_transfer_completion] evnt len : 0x34
[ 27.824244355/ 0x240bf05d] [0x0 mhi_dev_queue_transfer_completion] evnt code :0x2
[ 27.824246178/ 0x240bf081] [0x0 mhi_dev_queue_transfer_completion] evnt type :0x22
[ 27.824248053/ 0x240bf0a5] [0x0 mhi_dev_queue_transfer_completion] evnt chid :0x14
[ 27.824249771/ 0x240bf0c6] [0x0 mhi_dev_queue_transfer_completion] evt_buf_rp: 0x1, curr_ereq:0x1
[ 27.824252792/ 0x240bf100] [0x0 mhi_dev_send_completion_event_async] Calling flush for ch_id:20
[ 27.824255188/ 0x240bf12e] [0x0 mhi_dev_flush_transfer_completion_events] Flush num 1 called for ch_id:20
[ 27.824259771/ 0x240bf186] [0x0 mhi_dev_send_multiple_tr_events] Flushing 1 cmpl events of ch_id:20
[ 27.824264355/ 0x240bf1de] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.824266282/ 0x240bf203] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0xb, new-offset 0xc
[ 27.824269146/ 0x240bf23a] [0x0 mhi_dev_add_element] evnt ptr : 0x184d000
[ 27.824271074/ 0x240bf25f] [0x0 mhi_dev_add_element] evnt len : 0x34
[ 27.824272740/ 0x240bf27f] [0x0 mhi_dev_add_element] evnt code :0x2
[ 27.824274407/ 0x240bf29f] [0x0 mhi_dev_add_element] evnt type :0x22
[ 27.824276074/ 0x240bf2bf] [0x0 mhi_dev_add_element] evnt ch_id :0x14
[ 27.824278574/ 0x240bf2f0] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b530b0, size 16
[ 27.824288938/ 0x240bf3b6] [0x0 mhi_dev_send_multiple_tr_events] Caching rp 9b530c0 for rd offset 12
[ 27.824310605/ 0x240bf556] [0x0 mhi_dev_send_multiple_tr_events] ev.rp = 9b530c0 for 1
[ 27.824313209/ 0x240bf588] [0x0 mhi_dev_send_multiple_tr_events] RP phy addr = 0x8b9db060 for ring rd offset 12
[ 27.824315969/ 0x240bf5bd] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.824349199/ 0x240bf83b] [0x0 mhi_dev_schedule_msi_ipa] Sending MSI 1 to 0xfee30040 as data = 0x1 for ch_id:20 msi_count 1, ereq flush_num 1
[ 27.824353469/ 0x240bf88d] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100fee30040, size 4
[ 27.824381386/ 0x240bfaa8] [0x0 mhi_dev_read_channel] evtptr : 0x0
[ 27.824383782/ 0x240bfad3] [0x0 mhi_dev_read_channel] evntlen : 0x0, offset:1
[ 27.824385865/ 0x240bfafb] [0x0 mhi_dev_read_channel] nothing to read, returning
[ 27.824401438/ 0x240bfc27] [0x0 mhi_dev_event_buf_completion_cb] Event buf dma completed for flush req 1
[ 27.824406803/ 0x240bfc8d] [0x0 mhi_dev_event_rd_offset_completion_cb] Rd offset dma completed for flush req 1
[ 27.824411178/ 0x240bfce1] [0x0 mhi_dev_event_msi_cb] MSI completed for flush req 1
[ 27.824569980/ 0x240c08cb] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.824573521/ 0x240c090e] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c90000, size 52
[ 27.826737636/ 0x240cab5d] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.826739511/ 0x240cab81] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0xc, new-offset 0xd
[ 27.826742688/ 0x240cabbe] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.826744459/ 0x240cabe0] [0x0 mhi_dev_add_element] rd_ofset 13
[ 27.826746178/ 0x240cac01] [0x0 mhi_dev_add_element] type 34
[ 27.826748313/ 0x240cac2a] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b530c0, size 16
[ 27.828876178/ 0x240d4bc2] [0x0 mhi_dev_send_event] ev.rp = 9b530d0 for 1
[ 27.828879772/ 0x240d4c06] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.831011594/ 0x240debed] [0x0 mhi_dev_send_event] event sent:
[ 27.831015501/ 0x240dec37] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc010
[ 27.831017688/ 0x240dec5f] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.831019303/ 0x240dec7d] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.831020917/ 0x240dec9c] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.831022532/ 0x240decbb] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.831058261/ 0x240def69] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.831061490/ 0x240defa8] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ca0000, size 52
[ 27.831117063/ 0x240df3d5] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.831134511/ 0x240df522] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.833223157/ 0x240e91c7] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.833225240/ 0x240e91ef] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0xd, new-offset 0xe
[ 27.833228209/ 0x240e9228] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.833229824/ 0x240e9247] [0x0 mhi_dev_add_element] rd_ofset 14
[ 27.833231490/ 0x240e9266] [0x0 mhi_dev_add_element] type 34
[ 27.833233313/ 0x240e928d] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b530d0, size 16
[ 27.835360553/ 0x240f3217] [0x0 mhi_dev_send_event] ev.rp = 9b530e0 for 1
[ 27.835364147/ 0x240f325b] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.837489876/ 0x240fd1cc] [0x0 mhi_dev_send_event] event sent:
[ 27.837492219/ 0x240fd1f6] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc020
[ 27.837494147/ 0x240fd21a] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.837495761/ 0x240fd239] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.837497115/ 0x240fd253] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.837498574/ 0x240fd26f] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.837532428/ 0x240fd4f9] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.837535084/ 0x240fd52c] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cb0000, size 52
[ 27.839690501/ 0x241076d4] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.839692219/ 0x241076f5] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0xe, new-offset 0xf
[ 27.839695240/ 0x2410772f] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.839696751/ 0x2410774c] [0x0 mhi_dev_add_element] rd_ofset 15
[ 27.839698261/ 0x24107769] [0x0 mhi_dev_add_element] type 34
[ 27.839699824/ 0x24107787] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b530e0, size 16
[ 27.841830605/ 0x24111759] [0x0 mhi_dev_send_event] ev.rp = 9b530f0 for 1
[ 27.841834251/ 0x2411179d] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.843960344/ 0x2411b713] [0x0 mhi_dev_send_event] event sent:
[ 27.843962844/ 0x2411b741] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc030
[ 27.843964876/ 0x2411b768] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.843966386/ 0x2411b785] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.843967792/ 0x2411b7a0] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.843969303/ 0x2411b7bc] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.844009772/ 0x2411bacb] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.844014094/ 0x2411bb1a] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.844016751/ 0x2411bb4c] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.844019042/ 0x2411bb78] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.844020657/ 0x2411bb97] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.844023469/ 0x2411bbcd] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.844025449/ 0x2411bbf3] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:4 wp:0
[ 27.844029147/ 0x2411bc3a] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc020
[ 27.844031542/ 0x2411bc68] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 0, end 2
[ 27.844034355/ 0x2411bc9f] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd000 <<-- host 0x100058cc000, size 32
[ 27.844071751/ 0x2411bf70] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.844074719/ 0x2411bfa5] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cc0000, size 52
[ 27.844097532/ 0x2411c15c] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:4 with wr:2
[ 27.844100865/ 0x2411c19c] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cc0000
[ 27.844103053/ 0x2411c1c5] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:4
[ 27.846249980/ 0x241262ca] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.846251699/ 0x241262eb] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0xf, new-offset 0x10
[ 27.846254563/ 0x24126322] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.846256074/ 0x2412633f] [0x0 mhi_dev_add_element] rd_ofset 16
[ 27.846257844/ 0x24126361] [0x0 mhi_dev_add_element] type 34
[ 27.846259511/ 0x24126381] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b530f0, size 16
[ 27.848386647/ 0x2413030c] [0x0 mhi_dev_send_event] ev.rp = 9b53100 for 1
[ 27.848390449/ 0x24130353] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.850519563/ 0x2413a304] [0x0 mhi_dev_send_event] event sent:
[ 27.850522063/ 0x2413a332] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc040
[ 27.850523990/ 0x2413a357] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.850525605/ 0x2413a376] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.850527167/ 0x2413a394] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.850528730/ 0x2413a3b2] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.850553001/ 0x2413a585] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.850564615/ 0x2413a667] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.850573001/ 0x2413a704] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.850576334/ 0x2413a744] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.850578730/ 0x2413a772] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.850580813/ 0x2413a79a] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.850582324/ 0x2413a7b7] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.850584615/ 0x2413a7e3] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.850586178/ 0x2413a802] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:5 wp:2
[ 27.850589355/ 0x2413a83e] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc030
[ 27.850591647/ 0x2413a86a] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 2, end 3
[ 27.850594094/ 0x2413a899] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd020 <<-- host 0x100058cc020, size 16
[ 27.850640136/ 0x2413ac0d] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.850643261/ 0x2413ac49] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cd0000, size 52
[ 27.850662792/ 0x2413adc1] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:5 with wr:3
[ 27.850666386/ 0x2413ae05] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 27.850668522/ 0x2413ae2e] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:5
[ 27.852821855/ 0x24144fae] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.852824042/ 0x24144fd8] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x10, new-offset 0x11
[ 27.852827324/ 0x24145017] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.852828886/ 0x24145035] [0x0 mhi_dev_add_element] rd_ofset 17
[ 27.852830397/ 0x24145052] [0x0 mhi_dev_add_element] type 34
[ 27.852832011/ 0x24145071] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53100, size 16
[ 27.854960084/ 0x2414f00e] [0x0 mhi_dev_send_event] ev.rp = 9b53110 for 1
[ 27.854963782/ 0x2414f053] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.857087115/ 0x24158f94] [0x0 mhi_dev_send_event] event sent:
[ 27.857089303/ 0x24158fbd] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc050
[ 27.857091022/ 0x24158fde] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.857092584/ 0x24158ffc] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.857094095/ 0x24159019] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.857095657/ 0x24159038] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.857116855/ 0x241591ce] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.857129147/ 0x241592ba] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.857137636/ 0x2415935e] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.857140970/ 0x2415939d] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.857143209/ 0x241593c8] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.857145136/ 0x241593ed] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.857146699/ 0x2415940b] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.857148938/ 0x24159436] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.857150605/ 0x24159456] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:6 wp:3
[ 27.857153834/ 0x24159494] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc040
[ 27.857156074/ 0x241594bf] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 3, end 4
[ 27.857158417/ 0x241594ec] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd030 <<-- host 0x100058cc030, size 16
[ 27.857209147/ 0x241598ba] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.857211803/ 0x241598ed] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ce0000, size 52
[ 27.857234095/ 0x24159a9a] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:6 with wr:4
[ 27.857237636/ 0x24159add] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ce0000
[ 27.857239824/ 0x24159b07] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:6
[ 27.859381542/ 0x24163ba8] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.859383417/ 0x24163bcc] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x11, new-offset 0x12
[ 27.859386438/ 0x24163c06] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.859388105/ 0x24163c26] [0x0 mhi_dev_add_element] rd_ofset 18
[ 27.859389615/ 0x24163c43] [0x0 mhi_dev_add_element] type 34
[ 27.859391126/ 0x24163c60] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53110, size 16
[ 27.861526647/ 0x2416dc91] [0x0 mhi_dev_send_event] ev.rp = 9b53120 for 1
[ 27.861533678/ 0x2416dd14] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.863664095/ 0x24177cdb] [0x0 mhi_dev_send_event] event sent:
[ 27.863667480/ 0x24177d1b] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc060
[ 27.863669563/ 0x24177d42] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.863671438/ 0x24177d66] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.863673053/ 0x24177d85] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.863674667/ 0x24177da4] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.863702845/ 0x24177fc2] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.863715292/ 0x241780b0] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.863724095/ 0x2417815d] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.863728105/ 0x241781a6] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.863730865/ 0x241781db] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.863733313/ 0x24178209] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.863735032/ 0x2417822b] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.863737584/ 0x2417825c] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.863739199/ 0x2417827c] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:4
[ 27.863742584/ 0x241782bc] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc050
[ 27.863745032/ 0x241782eb] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 4, end 5
[ 27.863747740/ 0x2417831f] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd040 <<-- host 0x100058cc040, size 16
[ 27.863804772/ 0x24178766] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.863807949/ 0x241787a3] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c80000, size 52
[ 27.863833053/ 0x24178986] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:5
[ 27.863836751/ 0x241789cd] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 27.863839042/ 0x241789f8] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 27.865984667/ 0x24182ae5] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.865986803/ 0x24182b0d] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x12, new-offset 0x13
[ 27.865990136/ 0x24182b4d] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.865992063/ 0x24182b72] [0x0 mhi_dev_add_element] rd_ofset 19
[ 27.865993782/ 0x24182b93] [0x0 mhi_dev_add_element] type 34
[ 27.865995553/ 0x24182bb5] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53120, size 16
[ 27.868120084/ 0x2418cb0d] [0x0 mhi_dev_send_event] ev.rp = 9b53130 for 1
[ 27.868123522/ 0x2418cb4e] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.870249459/ 0x24196ac2] [0x0 mhi_dev_send_event] event sent:
[ 27.870251907/ 0x24196af0] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc070
[ 27.870253834/ 0x24196b14] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.870255397/ 0x24196b32] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.870256907/ 0x24196b4f] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.870258365/ 0x24196b6b] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.870279720/ 0x24196d06] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.870295553/ 0x24196e36] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.870304720/ 0x24196ee6] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.870308105/ 0x24196f26] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.870310501/ 0x24196f54] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.870312584/ 0x24196f7c] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.870314199/ 0x24196f9b] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.870316334/ 0x24196fc5] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.870318105/ 0x24196fe6] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:0 wp:5
[ 27.870321126/ 0x24197020] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc060
[ 27.870323417/ 0x2419704c] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 5, end 6
[ 27.870325761/ 0x24197079] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd050 <<-- host 0x100058cc050, size 16
[ 27.870364928/ 0x2419736a] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:0 with wr:6
[ 27.870368053/ 0x241973a6] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 27.870370032/ 0x241973cb] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:0
[ 27.870377584/ 0x2419745d] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.870392115/ 0x24197574] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.870399876/ 0x24197609] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.870403313/ 0x2419764a] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.870405813/ 0x2419767a] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.870407845/ 0x241976a0] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.870409251/ 0x241976bc] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.870411386/ 0x241976e6] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.870413001/ 0x24197704] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:0 wp:6
[ 27.870415865/ 0x2419773c] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc070
[ 27.870418157/ 0x24197767] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 6, end 7
[ 27.870420345/ 0x24197792] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd060 <<-- host 0x100058cc060, size 16
[ 27.870449303/ 0x241979bd] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.870452167/ 0x241979f4] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c90000, size 52
[ 27.871453313/ 0x2419c50c] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:0 with wr:7
[ 27.871456699/ 0x2419c54c] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 27.871458782/ 0x2419c573] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:0
[ 27.872607376/ 0x241a1b99] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.872609251/ 0x241a1bbc] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x13, new-offset 0x14
[ 27.872612428/ 0x241a1bf9] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.872614095/ 0x241a1c19] [0x0 mhi_dev_add_element] rd_ofset 20
[ 27.872615605/ 0x241a1c36] [0x0 mhi_dev_add_element] type 34
[ 27.872617376/ 0x241a1c58] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53130, size 16
[ 27.874741959/ 0x241abbb1] [0x0 mhi_dev_send_event] ev.rp = 9b53140 for 1
[ 27.874745032/ 0x241abbec] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.876867740/ 0x241b5b21] [0x0 mhi_dev_send_event] event sent:
[ 27.876870240/ 0x241b5b50] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc000
[ 27.876872272/ 0x241b5b76] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.876873834/ 0x241b5b94] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.876875397/ 0x241b5bb2] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.876876855/ 0x241b5bce] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.876913157/ 0x241b5e88] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.876915709/ 0x241b5eb8] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ca0000, size 52
[ 27.876964928/ 0x241b626a] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.876976282/ 0x241b6344] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.879068834/ 0x241c0034] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.879070657/ 0x241c0056] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x14, new-offset 0x15
[ 27.879073678/ 0x241c0091] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.879075240/ 0x241c00af] [0x0 mhi_dev_add_element] rd_ofset 21
[ 27.879076751/ 0x241c00cc] [0x0 mhi_dev_add_element] type 34
[ 27.879078209/ 0x241c00e8] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53140, size 16
[ 27.881205657/ 0x241ca07a] [0x0 mhi_dev_send_event] ev.rp = 9b53150 for 1
[ 27.881209407/ 0x241ca0c0] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.883335449/ 0x241d4035] [0x0 mhi_dev_send_event] event sent:
[ 27.883337845/ 0x241d4061] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc010
[ 27.883339772/ 0x241d4086] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.883341386/ 0x241d40a5] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.883342793/ 0x241d40bf] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.883344355/ 0x241d40de] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.883364824/ 0x241d4268] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.883368313/ 0x241d42aa] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.883370970/ 0x241d42dd] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.883372897/ 0x241d4302] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.883374355/ 0x241d431e] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.883376647/ 0x241d434a] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.883378261/ 0x241d4369] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:2 wp:7
[ 27.883381334/ 0x241d43a4] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc000
[ 27.883383678/ 0x241d43d1] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 7, end 0
[ 27.883386074/ 0x241d43ff] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd070 <<-- host 0x100058cc070, size 16
[ 27.883424772/ 0x241d46e7] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:2 with wr:0
[ 27.883427897/ 0x241d4722] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 27.883429772/ 0x241d4746] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:2
[ 27.883437272/ 0x241d47d6] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.883451907/ 0x241d48f0] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.883459824/ 0x241d4988] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.883463261/ 0x241d49ca] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.883465657/ 0x241d49f7] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.883467532/ 0x241d4a1b] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.883468990/ 0x241d4a37] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.883471126/ 0x241d4a61] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.883472740/ 0x241d4a7f] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:2 wp:0
[ 27.883475605/ 0x241d4ab6] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc010
[ 27.883477949/ 0x241d4ae3] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 0, end 1
[ 27.883480293/ 0x241d4b10] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd000 <<-- host 0x100058cc000, size 16
[ 27.883507688/ 0x241d4d1e] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.883510084/ 0x241d4d4d] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cb0000, size 52
[ 27.884513626/ 0x241d9893] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:2 with wr:1
[ 27.884517584/ 0x241d98dd] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 27.884519511/ 0x241d9901] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:2
[ 27.885667532/ 0x241def1b] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.885669251/ 0x241def3c] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x15, new-offset 0x16
[ 27.885672168/ 0x241def74] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.885673730/ 0x241def92] [0x0 mhi_dev_add_element] rd_ofset 22
[ 27.885675240/ 0x241defaf] [0x0 mhi_dev_add_element] type 34
[ 27.885677011/ 0x241defd1] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53150, size 16
[ 27.887805188/ 0x241e8f70] [0x0 mhi_dev_send_event] ev.rp = 9b53160 for 1
[ 27.887808678/ 0x241e8fb2] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.889934615/ 0x241f2f25] [0x0 mhi_dev_send_event] event sent:
[ 27.889936907/ 0x241f2f4f] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc020
[ 27.889938834/ 0x241f2f74] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.889940553/ 0x241f2f95] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.889941959/ 0x241f2fb0] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.889943418/ 0x241f2fcc] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.889978990/ 0x241f3278] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.889982011/ 0x241f32b1] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cc0000, size 52
[ 27.890042168/ 0x241f3734] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.890054668/ 0x241f3826] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.892137168/ 0x241fd455] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.892138938/ 0x241fd475] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x16, new-offset 0x17
[ 27.892141803/ 0x241fd4ad] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.892143365/ 0x241fd4cb] [0x0 mhi_dev_add_element] rd_ofset 23
[ 27.892144876/ 0x241fd4e8] [0x0 mhi_dev_add_element] type 34
[ 27.892146386/ 0x241fd505] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53160, size 16
[ 27.894272220/ 0x24207477] [0x0 mhi_dev_send_event] ev.rp = 9b53170 for 1
[ 27.894275397/ 0x242074b3] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.896400813/ 0x2421141c] [0x0 mhi_dev_send_event] event sent:
[ 27.896403001/ 0x24211445] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc030
[ 27.896404824/ 0x24211467] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.896406438/ 0x24211486] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.896407845/ 0x242114a1] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.896409251/ 0x242114bc] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.896428418/ 0x2421162d] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.896432063/ 0x24211672] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.896434303/ 0x2421169d] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.896436334/ 0x242116c4] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.896437793/ 0x242116e0] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.896440084/ 0x2421170c] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.896441699/ 0x2421172b] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:4 wp:1
[ 27.896444720/ 0x24211765] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc020
[ 27.896447011/ 0x24211790] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 1, end 2
[ 27.896449199/ 0x242117bb] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd010 <<-- host 0x100058cc010, size 16
[ 27.896487168/ 0x24211a95] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:4 with wr:2
[ 27.896490345/ 0x24211ad2] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 27.896492220/ 0x24211af5] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:4
[ 27.896501595/ 0x24211baa] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.896514095/ 0x24211c99] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.896521751/ 0x24211d2d] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.896525084/ 0x24211d6c] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.896527272/ 0x24211d96] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.896529199/ 0x24211dbb] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.896530657/ 0x24211dd7] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.896532793/ 0x24211e00] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.896534407/ 0x24211e1f] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:4 wp:2
[ 27.896537272/ 0x24211e57] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc030
[ 27.896539668/ 0x24211e84] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 2, end 3
[ 27.896542063/ 0x24211eb2] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd020 <<-- host 0x100058cc020, size 16
[ 27.896566803/ 0x2421208d] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.896569355/ 0x242120bf] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cd0000, size 52
[ 27.897574303/ 0x24216c1f] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:4 with wr:3
[ 27.897577949/ 0x24216c63] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 27.897579876/ 0x24216c88] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:4
[ 27.898726074/ 0x2421c27f] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.898727793/ 0x2421c29f] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x17, new-offset 0x18
[ 27.898730761/ 0x2421c2da] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.898732428/ 0x2421c2f9] [0x0 mhi_dev_add_element] rd_ofset 24
[ 27.898733990/ 0x2421c317] [0x0 mhi_dev_add_element] type 34
[ 27.898735605/ 0x2421c336] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53170, size 16
[ 27.900865918/ 0x242262fe] [0x0 mhi_dev_send_event] ev.rp = 9b53180 for 1
[ 27.900869251/ 0x2422633d] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.902992949/ 0x24230285] [0x0 mhi_dev_send_event] event sent:
[ 27.902995397/ 0x242302b2] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc040
[ 27.902997168/ 0x242302d4] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.902998730/ 0x242302f2] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.903000136/ 0x2423030d] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.903001699/ 0x2423032b] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.903037324/ 0x242305d7] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.903039980/ 0x2423060a] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ce0000, size 52
[ 27.903135709/ 0x24230d39] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.903146803/ 0x24230e11] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.905192688/ 0x2423a77e] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.905194355/ 0x2423a79e] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x18, new-offset 0x19
[ 27.905197324/ 0x2423a7d7] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.905198990/ 0x2423a7f7] [0x0 mhi_dev_add_element] rd_ofset 25
[ 27.905200553/ 0x2423a814] [0x0 mhi_dev_add_element] type 34
[ 27.905202376/ 0x2423a838] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53180, size 16
[ 27.907326855/ 0x2424478f] [0x0 mhi_dev_send_event] ev.rp = 9b53190 for 1
[ 27.907329772/ 0x242447c7] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.909452532/ 0x2424e6fd] [0x0 mhi_dev_send_event] event sent:
[ 27.909454668/ 0x2424e725] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc050
[ 27.909456491/ 0x2424e747] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.909458001/ 0x2424e764] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.909459407/ 0x2424e77f] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.909460866/ 0x2424e79b] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.909479616/ 0x2424e904] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.909483261/ 0x2424e94a] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.909485605/ 0x2424e976] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.909487636/ 0x2424e99d] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.909489147/ 0x2424e9ba] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.909491334/ 0x2424e9e4] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.909492949/ 0x2424ea03] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:6 wp:3
[ 27.909495813/ 0x2424ea3a] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc040
[ 27.909498209/ 0x2424ea68] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 3, end 4
[ 27.909500657/ 0x2424ea97] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd030 <<-- host 0x100058cc030, size 16
[ 27.909536282/ 0x2424ed44] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:6 with wr:4
[ 27.909539355/ 0x2424ed7e] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 27.909541334/ 0x2424eda4] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:6
[ 27.909567428/ 0x2424ef9a] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.909570084/ 0x2424efcc] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c80000, size 52
[ 27.909581751/ 0x2424f0ad] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.909591699/ 0x2424f16b] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.911717584/ 0x242590dc] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.911719407/ 0x242590ff] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x19, new-offset 0x1a
[ 27.911722428/ 0x2425913a] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.911723991/ 0x24259157] [0x0 mhi_dev_add_element] rd_ofset 26
[ 27.911725501/ 0x24259174] [0x0 mhi_dev_add_element] type 34
[ 27.911727116/ 0x24259194] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53190, size 16
[ 27.913853418/ 0x2426310e] [0x0 mhi_dev_send_event] ev.rp = 9b531a0 for 1
[ 27.913856855/ 0x2426314e] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.915983001/ 0x2426d0c7] [0x0 mhi_dev_send_event] event sent:
[ 27.915985397/ 0x2426d0f5] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc060
[ 27.915987324/ 0x2426d117] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.915988834/ 0x2426d134] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.915990188/ 0x2426d14e] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.915991751/ 0x2426d16c] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.916015918/ 0x2426d33d] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.916019459/ 0x2426d380] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.916021855/ 0x2426d3ae] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.916023730/ 0x2426d3d2] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.916025188/ 0x2426d3ee] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.916027636/ 0x2426d41d] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.916029251/ 0x2426d43c] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:4
[ 27.916032116/ 0x2426d474] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc050
[ 27.916034407/ 0x2426d49f] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 4, end 5
[ 27.916036699/ 0x2426d4cb] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd040 <<-- host 0x100058cc040, size 16
[ 27.916071595/ 0x2426d769] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:5
[ 27.916074668/ 0x2426d7a5] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 27.916076699/ 0x2426d7cb] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 27.916105866/ 0x2426d9fc] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.916115605/ 0x2426dab7] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.916123834/ 0x2426db55] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.916126959/ 0x2426db91] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.916129303/ 0x2426dbbd] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.916131386/ 0x2426dbe5] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.916132845/ 0x2426dc01] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.916134928/ 0x2426dc29] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.916136543/ 0x2426dc48] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:5
[ 27.916139459/ 0x2426dc80] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc060
[ 27.916141699/ 0x2426dcab] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 5, end 6
[ 27.916143886/ 0x2426dcd6] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd050 <<-- host 0x100058cc050, size 16
[ 27.916155188/ 0x2426ddaf] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.916157897/ 0x2426dde3] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c90000, size 52
[ 27.917151855/ 0x24272870] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:6
[ 27.917155397/ 0x242728b3] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 27.917157532/ 0x242728db] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 27.918312949/ 0x24277f83] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.918314668/ 0x24277fa4] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x1a, new-offset 0x1b
[ 27.918317584/ 0x24277fdc] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.918319147/ 0x24277ffa] [0x0 mhi_dev_add_element] rd_ofset 27
[ 27.918320657/ 0x24278017] [0x0 mhi_dev_add_element] type 34
[ 27.918322272/ 0x24278037] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b531a0, size 16
[ 27.920452428/ 0x24281ffa] [0x0 mhi_dev_send_event] ev.rp = 9b531b0 for 1
[ 27.920455553/ 0x24282035] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.922581543/ 0x2428bfaa] [0x0 mhi_dev_send_event] event sent:
[ 27.922583991/ 0x2428bfd7] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc070
[ 27.922585761/ 0x2428bffa] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.922587324/ 0x2428c017] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.922588730/ 0x2428c032] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.922590188/ 0x2428c04e] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.922621751/ 0x2428c2ac] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.922624251/ 0x2428c2dd] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ca0000, size 52
[ 27.922699876/ 0x2428c88a] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.922712011/ 0x2428c972] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.924778886/ 0x24296475] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.924780553/ 0x24296495] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x1b, new-offset 0x1c
[ 27.924783470/ 0x242964cd] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.924785032/ 0x242964eb] [0x0 mhi_dev_add_element] rd_ofset 28
[ 27.924786543/ 0x24296508] [0x0 mhi_dev_add_element] type 34
[ 27.924788001/ 0x24296524] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b531b0, size 16
[ 27.926914407/ 0x242a04a1] [0x0 mhi_dev_send_event] ev.rp = 9b531c0 for 1
[ 27.926917845/ 0x242a04e2] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.929043001/ 0x242aa447] [0x0 mhi_dev_send_event] event sent:
[ 27.929045241/ 0x242aa470] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc000
[ 27.929047063/ 0x242aa492] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.929048574/ 0x242aa4af] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.929049980/ 0x242aa4c9] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.929051386/ 0x242aa4e5] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.929072897/ 0x242aa683] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.929076699/ 0x242aa6cb] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.929078938/ 0x242aa6f6] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.929080866/ 0x242aa71b] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.929082324/ 0x242aa737] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.929084511/ 0x242aa761] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.929086386/ 0x242aa785] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:6
[ 27.929089303/ 0x242aa7bd] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc070
[ 27.929091699/ 0x242aa7eb] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 6, end 7
[ 27.929094251/ 0x242aa81c] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd060 <<-- host 0x100058cc060, size 16
[ 27.929131022/ 0x242aaadf] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:7
[ 27.929134095/ 0x242aab1a] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 27.929135970/ 0x242aab3d] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 27.929145084/ 0x242aabed] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.929157376/ 0x242aacd9] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.929164928/ 0x242aad69] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.929168261/ 0x242aada9] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.929170449/ 0x242aadd3] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.929172376/ 0x242aadf8] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.929173782/ 0x242aae13] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.929175918/ 0x242aae3d] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.929177532/ 0x242aae5c] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:7
[ 27.929180397/ 0x242aae92] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc000
[ 27.929182688/ 0x242aaebe] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 7, end 0
[ 27.929184980/ 0x242aaeeb] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd070 <<-- host 0x100058cc070, size 16
[ 27.929209511/ 0x242ab0c1] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.929212063/ 0x242ab0f2] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cb0000, size 52
[ 27.930220709/ 0x242afc99] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:0
[ 27.930224616/ 0x242afce4] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 27.930226647/ 0x242afd0a] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 27.931368157/ 0x242b52a7] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.931369876/ 0x242b52c8] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x1c, new-offset 0x1d
[ 27.931372793/ 0x242b5300] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.931374407/ 0x242b531f] [0x0 mhi_dev_add_element] rd_ofset 29
[ 27.931375970/ 0x242b533d] [0x0 mhi_dev_add_element] type 34
[ 27.931377741/ 0x242b535f] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b531c0, size 16
[ 27.933503782/ 0x242bf2d6] [0x0 mhi_dev_send_event] ev.rp = 9b531d0 for 1
[ 27.933507116/ 0x242bf314] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.935632272/ 0x242c9278] [0x0 mhi_dev_send_event] event sent:
[ 27.935634459/ 0x242c92a0] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc010
[ 27.935636230/ 0x242c92c2] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.935637793/ 0x242c92df] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.935639147/ 0x242c92fa] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.935640605/ 0x242c9316] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.935673209/ 0x242c9588] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.935675605/ 0x242c95b6] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cc0000, size 52
[ 27.935747845/ 0x242c9b25] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.935760397/ 0x242c9c13] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.937830709/ 0x242d3758] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.937832428/ 0x242d3779] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x1d, new-offset 0x1e
[ 27.937835345/ 0x242d37b1] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.937836855/ 0x242d37ce] [0x0 mhi_dev_add_element] rd_ofset 30
[ 27.937838418/ 0x242d37eb] [0x0 mhi_dev_add_element] type 34
[ 27.937839980/ 0x242d380a] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b531d0, size 16
[ 27.939967324/ 0x242dd799] [0x0 mhi_dev_send_event] ev.rp = 9b531e0 for 1
[ 27.939970709/ 0x242dd7d9] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.942098834/ 0x242e7776] [0x0 mhi_dev_send_event] event sent:
[ 27.942101074/ 0x242e779f] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc020
[ 27.942102845/ 0x242e77c1] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.942104355/ 0x242e77de] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.942105709/ 0x242e77f8] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.942107168/ 0x242e7814] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.942128730/ 0x242e79b3] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.942132220/ 0x242e79f6] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.942134720/ 0x242e7a25] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.942136855/ 0x242e7a4d] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.942138314/ 0x242e7a6a] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.942140501/ 0x242e7a95] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.942142168/ 0x242e7ab4] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:3 wp:0
[ 27.942145032/ 0x242e7aec] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc010
[ 27.942147324/ 0x242e7b17] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 0, end 1
[ 27.942149511/ 0x242e7b41] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd000 <<-- host 0x100058cc000, size 16
[ 27.942185189/ 0x242e7def] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:3 with wr:1
[ 27.942188314/ 0x242e7e2b] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 27.942190189/ 0x242e7e4e] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:3
[ 27.942208053/ 0x242e7fa6] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.942217480/ 0x242e805a] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.942224564/ 0x242e80e2] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.942227689/ 0x242e8121] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.942230032/ 0x242e814b] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.942232116/ 0x242e8173] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.942233574/ 0x242e818f] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.942235709/ 0x242e81b8] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.942237324/ 0x242e81d7] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:3 wp:1
[ 27.942240189/ 0x242e820e] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc020
[ 27.942242480/ 0x242e823a] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 1, end 2
[ 27.942244668/ 0x242e8264] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd010 <<-- host 0x100058cc010, size 16
[ 27.942265084/ 0x242e83ec] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.942267584/ 0x242e841d] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cd0000, size 52
[ 27.943263939/ 0x242eced7] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:3 with wr:2
[ 27.943267949/ 0x242ecf23] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 27.943269876/ 0x242ecf47] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:3
[ 27.944422064/ 0x242f25b2] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.944423782/ 0x242f25d2] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x1e, new-offset 0x1f
[ 27.944426647/ 0x242f260a] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.944428209/ 0x242f2628] [0x0 mhi_dev_add_element] rd_ofset 31
[ 27.944429772/ 0x242f2646] [0x0 mhi_dev_add_element] type 34
[ 27.944431230/ 0x242f2662] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b531e0, size 16
[ 27.946557636/ 0x242fc5df] [0x0 mhi_dev_send_event] ev.rp = 9b531f0 for 1
[ 27.946560918/ 0x242fc61d] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.948686022/ 0x2430657f] [0x0 mhi_dev_send_event] event sent:
[ 27.948688261/ 0x243065a9] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc030
[ 27.948690032/ 0x243065cb] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.948691595/ 0x243065e9] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.948693001/ 0x24306604] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.948694616/ 0x24306623] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.948727689/ 0x2430689e] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.948730084/ 0x243068cc] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ce0000, size 52
[ 27.948794720/ 0x24306da7] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.948806647/ 0x24306e8b] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.950887636/ 0x24310a9e] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.950889355/ 0x24310abe] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x1f, new-offset 0x20
[ 27.950892324/ 0x24310af7] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.950893886/ 0x24310b15] [0x0 mhi_dev_add_element] rd_ofset 32
[ 27.950895397/ 0x24310b32] [0x0 mhi_dev_add_element] type 34
[ 27.950896907/ 0x24310b4f] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b531f0, size 16
[ 27.953022845/ 0x2431aac2] [0x0 mhi_dev_send_event] ev.rp = 9b53200 for 1
[ 27.953026022/ 0x2431aaff] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.955150918/ 0x24324a5f] [0x0 mhi_dev_send_event] event sent:
[ 27.955153157/ 0x24324a87] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc040
[ 27.955154928/ 0x24324aa9] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.955156386/ 0x24324ac5] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.955157793/ 0x24324ae0] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.955159199/ 0x24324afb] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.955181543/ 0x24324ca9] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.955185084/ 0x24324cec] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.955187376/ 0x24324d18] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.955189251/ 0x24324d3c] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.955190761/ 0x24324d58] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.955192949/ 0x24324d83] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.955194564/ 0x24324da2] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:5 wp:2
[ 27.955197480/ 0x24324dda] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc030
[ 27.955199876/ 0x24324e08] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 2, end 3
[ 27.955202064/ 0x24324e32] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd020 <<-- host 0x100058cc020, size 16
[ 27.955239928/ 0x2432510a] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:5 with wr:3
[ 27.955243053/ 0x24325146] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 27.955244928/ 0x24325169] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:5
[ 27.955263314/ 0x243252cb] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.955273678/ 0x24325391] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.955281022/ 0x2432541f] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.955284303/ 0x2432545e] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.955286543/ 0x24325488] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.955288678/ 0x243254b1] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.955290136/ 0x243254cd] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.955292480/ 0x243254fb] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.955294095/ 0x2432551a] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:5 wp:3
[ 27.955297011/ 0x24325551] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc040
[ 27.955299407/ 0x2432557f] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 3, end 4
[ 27.955301595/ 0x243255aa] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd030 <<-- host 0x100058cc030, size 16
[ 27.955323418/ 0x2432574c] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.955326126/ 0x24325781] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c80000, size 52
[ 27.956318626/ 0x2432a1f2] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:5 with wr:4
[ 27.956322272/ 0x2432a236] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 27.956324199/ 0x2432a25b] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:5
[ 27.957481022/ 0x2432f91e] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.957482741/ 0x2432f93f] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x20, new-offset 0x21
[ 27.957485657/ 0x2432f977] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.957487168/ 0x2432f994] [0x0 mhi_dev_add_element] rd_ofset 33
[ 27.957488678/ 0x2432f9b1] [0x0 mhi_dev_add_element] type 34
[ 27.957490189/ 0x2432f9ce] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53200, size 16
[ 27.959616439/ 0x24339948] [0x0 mhi_dev_send_event] ev.rp = 9b53210 for 1
[ 27.959619824/ 0x24339988] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.961748053/ 0x24343927] [0x0 mhi_dev_send_event] event sent:
[ 27.961750293/ 0x24343950] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc050
[ 27.961752168/ 0x24343975] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.961753782/ 0x24343993] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.961755189/ 0x243439ae] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.961756647/ 0x243439ca] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.961787949/ 0x24343c23] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.961790345/ 0x24343c52] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c90000, size 52
[ 27.961863522/ 0x243441d1] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.961875553/ 0x243442b6] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.963945866/ 0x2434ddfb] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.963947584/ 0x2434de1c] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x21, new-offset 0x22
[ 27.963950501/ 0x2434de54] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.963952012/ 0x2434de71] [0x0 mhi_dev_add_element] rd_ofset 34
[ 27.963953522/ 0x2434de8e] [0x0 mhi_dev_add_element] type 34
[ 27.963954980/ 0x2434deaa] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53210, size 16
[ 27.966081803/ 0x24357e2f] [0x0 mhi_dev_send_event] ev.rp = 9b53220 for 1
[ 27.966084980/ 0x24357e6b] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.968209355/ 0x24361dbf] [0x0 mhi_dev_send_event] event sent:
[ 27.968211543/ 0x24361de9] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc060
[ 27.968213470/ 0x24361e0d] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.968215084/ 0x24361e2c] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.968216491/ 0x24361e47] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.968217949/ 0x24361e63] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.968240241/ 0x24362010] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.968244095/ 0x24362059] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.968246491/ 0x24362087] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.968248418/ 0x243620ab] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.968249824/ 0x243620c7] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.968252012/ 0x243620f1] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.968253626/ 0x24362110] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:4
[ 27.968256491/ 0x24362147] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc050
[ 27.968258782/ 0x24362172] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 4, end 5
[ 27.968260970/ 0x2436219d] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd040 <<-- host 0x100058cc040, size 16
[ 27.968300449/ 0x24362494] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:5
[ 27.968303991/ 0x243624d7] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ca0000
[ 27.968305918/ 0x243624fc] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 27.968315293/ 0x243625b1] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.968323782/ 0x24362654] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.968330814/ 0x243626db] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.968333939/ 0x24362716] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.968336282/ 0x24362743] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.968338209/ 0x24362768] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.968339668/ 0x24362784] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.968341803/ 0x243627ae] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.968343418/ 0x243627cc] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:5
[ 27.968346282/ 0x24362803] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc060
[ 27.968348574/ 0x2436282f] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 5, end 6
[ 27.968350762/ 0x24362859] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd050 <<-- host 0x100058cc050, size 16
[ 27.968372689/ 0x243629fe] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.968375449/ 0x24362a34] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ca0000, size 52
[ 27.969365345/ 0x24367472] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:6
[ 27.969368782/ 0x243674b4] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ca0000
[ 27.969370918/ 0x243674dc] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 27.970532324/ 0x2436cbf7] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.970534147/ 0x2436cc1a] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x22, new-offset 0x23
[ 27.970537012/ 0x2436cc51] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.970538574/ 0x2436cc6f] [0x0 mhi_dev_add_element] rd_ofset 35
[ 27.970540084/ 0x2436cc8c] [0x0 mhi_dev_add_element] type 34
[ 27.970541647/ 0x2436ccaa] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53220, size 16
[ 27.972668730/ 0x24376c34] [0x0 mhi_dev_send_event] ev.rp = 9b53230 for 1
[ 27.972672116/ 0x24376c74] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.974797428/ 0x24380bdb] [0x0 mhi_dev_send_event] event sent:
[ 27.974799616/ 0x24380c03] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc070
[ 27.974801387/ 0x24380c25] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.974802949/ 0x24380c42] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.974804459/ 0x24380c60] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.974805918/ 0x24380c7c] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.974838834/ 0x24380ef4] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.974841647/ 0x24380f2a] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cb0000, size 52
[ 27.974903574/ 0x243813d1] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.974915032/ 0x243814ac] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.976996439/ 0x2438b0c7] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.976998157/ 0x2438b0e7] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x23, new-offset 0x24
[ 27.977001022/ 0x2438b11e] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.977002532/ 0x2438b13b] [0x0 mhi_dev_add_element] rd_ofset 36
[ 27.977004043/ 0x2438b158] [0x0 mhi_dev_add_element] type 34
[ 27.977005553/ 0x2438b175] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53230, size 16
[ 27.979131543/ 0x243950ea] [0x0 mhi_dev_send_event] ev.rp = 9b53240 for 1
[ 27.979134616/ 0x24395124] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.981262272/ 0x2439f0b8] [0x0 mhi_dev_send_event] event sent:
[ 27.981264564/ 0x2439f0e3] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc000
[ 27.981266387/ 0x2439f105] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.981267845/ 0x2439f120] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.981269199/ 0x2439f13c] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.981270709/ 0x2439f157] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.981292897/ 0x2439f303] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.981296439/ 0x2439f346] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.981298678/ 0x2439f371] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.981300709/ 0x2439f398] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.981302168/ 0x2439f3b4] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.981304303/ 0x2439f3de] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.981305970/ 0x2439f3fd] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:6
[ 27.981308834/ 0x2439f434] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc070
[ 27.981311126/ 0x2439f460] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 6, end 7
[ 27.981313314/ 0x2439f48b] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd060 <<-- host 0x100058cc060, size 16
[ 27.981354355/ 0x2439f79f] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:7
[ 27.981357689/ 0x2439f7de] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cc0000
[ 27.981359720/ 0x2439f805] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 27.981379668/ 0x2439f985] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.981388626/ 0x2439fa31] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.981395657/ 0x2439fab8] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.981398887/ 0x2439faf6] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.981401126/ 0x2439fb20] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.981403053/ 0x2439fb45] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.981404512/ 0x2439fb61] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.981406647/ 0x2439fb8a] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.981408209/ 0x2439fba9] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:7
[ 27.981411126/ 0x2439fbe0] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc000
[ 27.981413418/ 0x2439fc0c] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 7, end 0
[ 27.981415762/ 0x2439fc39] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd070 <<-- host 0x100058cc070, size 16
[ 27.981425345/ 0x2439fcf2] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.981428105/ 0x2439fd26] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cc0000, size 52
[ 27.982417689/ 0x243a4760] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:0
[ 27.982421959/ 0x243a47b0] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cc0000
[ 27.982423991/ 0x243a47d7] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 27.983583001/ 0x243a9ec4] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.983584720/ 0x243a9ee4] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x24, new-offset 0x25
[ 27.983587584/ 0x243a9f1c] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.983589095/ 0x243a9f39] [0x0 mhi_dev_add_element] rd_ofset 37
[ 27.983590762/ 0x243a9f59] [0x0 mhi_dev_add_element] type 34
[ 27.983592272/ 0x243a9f76] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53240, size 16
[ 27.985719303/ 0x243b3eff] [0x0 mhi_dev_send_event] ev.rp = 9b53250 for 1
[ 27.985722532/ 0x243b3f3c] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.987847793/ 0x243bdea2] [0x0 mhi_dev_send_event] event sent:
[ 27.987849980/ 0x243bdecb] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc010
[ 27.987851803/ 0x243bdeed] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.987853470/ 0x243bdf0d] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.987854876/ 0x243bdf28] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.987856334/ 0x243bdf44] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.987888001/ 0x243be1a4] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.987890709/ 0x243be1d8] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cd0000, size 52
[ 27.987954043/ 0x243be699] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.987965501/ 0x243be775] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.990172637/ 0x243c8cfd] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.990174772/ 0x243c8d26] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x25, new-offset 0x26
[ 27.990177741/ 0x243c8d5f] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.990179564/ 0x243c8d82] [0x0 mhi_dev_add_element] rd_ofset 38
[ 27.990181230/ 0x243c8da2] [0x0 mhi_dev_add_element] type 34
[ 27.990182845/ 0x243c8dc1] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53250, size 16
[ 27.992530189/ 0x243d3dd0] [0x0 mhi_dev_send_event] ev.rp = 9b53260 for 1
[ 27.992536387/ 0x243d3e46] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 27.994665449/ 0x243dddf5] [0x0 mhi_dev_send_event] event sent:
[ 27.994669043/ 0x243dde38] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc020
[ 27.994670866/ 0x243dde5b] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 27.994672376/ 0x243dde78] [0x0 mhi_dev_send_event] evnt code :0x2
[ 27.994674043/ 0x243dde97] [0x0 mhi_dev_send_event] evnt type :0x22
[ 27.994675710/ 0x243ddeb8] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 27.994704043/ 0x243de0d9] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.994707845/ 0x243de121] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.994710345/ 0x243de151] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.994712585/ 0x243de17c] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.994714199/ 0x243de19b] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.994716595/ 0x243de1c9] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.994718210/ 0x243de1e8] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:3 wp:0
[ 27.994721230/ 0x243de222] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc010
[ 27.994723522/ 0x243de24e] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 0, end 1
[ 27.994726230/ 0x243de282] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd000 <<-- host 0x100058cc000, size 16
[ 27.994770501/ 0x243de5d5] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:3 with wr:1
[ 27.994773939/ 0x243de616] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ce0000
[ 27.994776178/ 0x243de641] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:3
[ 27.994790866/ 0x243de75d] [0x0 mhi_dev_isr] mhi irq triggered
[ 27.994801126/ 0x243de820] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 27.994809147/ 0x243de8be] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 27.994812532/ 0x243de8fb] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 27.994814876/ 0x243de928] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 27.994816803/ 0x243de94d] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 27.994818210/ 0x243de968] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 27.994820345/ 0x243de991] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 27.994821960/ 0x243de9b0] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:3 wp:1
[ 27.994824824/ 0x243de9e8] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc020
[ 27.994827116/ 0x243dea13] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 1, end 2
[ 27.994829460/ 0x243dea40] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd010 <<-- host 0x100058cc010, size 16
[ 27.994858522/ 0x243dec6e] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 27.994861543/ 0x243deca8] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ce0000, size 52
[ 27.995854824/ 0x243e3729] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:3 with wr:2
[ 27.995858730/ 0x243e3772] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ce0000
[ 27.995860657/ 0x243e3798] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:3
[ 27.997021907/ 0x243e8eaf] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 27.997023887/ 0x243e8ed5] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x26, new-offset 0x27
[ 27.997026855/ 0x243e8f0e] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 27.997028626/ 0x243e8f30] [0x0 mhi_dev_add_element] rd_ofset 39
[ 27.997030137/ 0x243e8f4d] [0x0 mhi_dev_add_element] type 34
[ 27.997031647/ 0x243e8f6a] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53260, size 16
[ 27.999160814/ 0x243f2f1c] [0x0 mhi_dev_send_event] ev.rp = 9b53270 for 1
[ 27.999164251/ 0x243f2f5c] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.001296699/ 0x243fcf4d] [0x0 mhi_dev_send_event] event sent:
[ 28.001299460/ 0x243fcf80] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc030
[ 28.001301387/ 0x243fcfa5] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.001303053/ 0x243fcfc5] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.001304616/ 0x243fcfe3] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.001306230/ 0x243fd002] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.001341335/ 0x243fd2a4] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.001343887/ 0x243fd2d5] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c80000, size 52
[ 28.001437949/ 0x243fd9e5] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.001451230/ 0x243fdae3] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.003499147/ 0x2440747a] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.003500918/ 0x2440749c] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x27, new-offset 0x28
[ 28.003503835/ 0x244074d5] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.003505553/ 0x244074f5] [0x0 mhi_dev_add_element] rd_ofset 40
[ 28.003507064/ 0x24407512] [0x0 mhi_dev_add_element] type 34
[ 28.003508678/ 0x24407531] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53270, size 16
[ 28.005635501/ 0x244114b6] [0x0 mhi_dev_send_event] ev.rp = 9b53280 for 1
[ 28.005638782/ 0x244114f4] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.007764251/ 0x2441b45e] [0x0 mhi_dev_send_event] event sent:
[ 28.007766439/ 0x2441b487] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc040
[ 28.007768366/ 0x2441b4ac] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.007769876/ 0x2441b4c8] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.007771282/ 0x2441b4e3] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.007772689/ 0x2441b4fe] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.007795605/ 0x2441b6b7] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.007799251/ 0x2441b6fd] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.007801647/ 0x2441b72a] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.007803678/ 0x2441b751] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.007805241/ 0x2441b76f] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.007807428/ 0x2441b799] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.007809043/ 0x2441b7b8] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:5 wp:2
[ 28.007811907/ 0x2441b7ef] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc030
[ 28.007814199/ 0x2441b81b] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 2, end 3
[ 28.007816907/ 0x2441b84f] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd020 <<-- host 0x100058cc020, size 16
[ 28.007858418/ 0x2441bb6d] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:5 with wr:3
[ 28.007861803/ 0x2441bbad] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 28.007863730/ 0x2441bbd2] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:5
[ 28.007882428/ 0x2441bd39] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.007885137/ 0x2441bd6d] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c90000, size 52
[ 28.007891907/ 0x2441bdf0] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.007901230/ 0x2441bea3] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.010062637/ 0x244260be] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.010064512/ 0x244260e1] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x28, new-offset 0x29
[ 28.010067585/ 0x2442611c] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.010069147/ 0x2442613a] [0x0 mhi_dev_add_element] rd_ofset 41
[ 28.010070866/ 0x2442615a] [0x0 mhi_dev_add_element] type 34
[ 28.010072480/ 0x2442617a] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53280, size 16
[ 28.012197532/ 0x244300dc] [0x0 mhi_dev_send_event] ev.rp = 9b53290 for 1
[ 28.012200762/ 0x24430119] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.014323314/ 0x2443a04b] [0x0 mhi_dev_send_event] event sent:
[ 28.014325866/ 0x2443a07b] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc050
[ 28.014327741/ 0x2443a09f] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.014329251/ 0x2443a0bc] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.014330918/ 0x2443a0dc] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.014332324/ 0x2443a0f7] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.014352689/ 0x2443a27f] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.014356335/ 0x2443a2c4] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.014358574/ 0x2443a2ef] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.014360501/ 0x2443a314] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.014361960/ 0x2443a330] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.014364251/ 0x2443a35c] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.014365866/ 0x2443a37b] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:6 wp:3
[ 28.014368887/ 0x2443a3b5] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc040
[ 28.014371282/ 0x2443a3e3] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 3, end 4
[ 28.014373522/ 0x2443a40e] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd030 <<-- host 0x100058cc030, size 16
[ 28.014413001/ 0x2443a704] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:6 with wr:4
[ 28.014416230/ 0x2443a742] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ca0000
[ 28.014418105/ 0x2443a766] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:6
[ 28.014440241/ 0x2443a912] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.014449928/ 0x2443a9cd] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.014436387/ 0x2443a8c5] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.014457220/ 0x2443aa56] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ca0000, size 52
[ 28.016610137/ 0x24444bcd] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.016612012/ 0x24444bf1] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x29, new-offset 0x2a
[ 28.016614980/ 0x24444c2a] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.016616595/ 0x24444c49] [0x0 mhi_dev_add_element] rd_ofset 42
[ 28.016618157/ 0x24444c67] [0x0 mhi_dev_add_element] type 34
[ 28.016619616/ 0x24444c83] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53290, size 16
[ 28.018744303/ 0x2444ebde] [0x0 mhi_dev_send_event] ev.rp = 9b532a0 for 1
[ 28.018747376/ 0x2444ec18] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.020872845/ 0x24458b85] [0x0 mhi_dev_send_event] event sent:
[ 28.020875866/ 0x24458bbc] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc060
[ 28.020877741/ 0x24458bdf] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.020879251/ 0x24458bfc] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.020880762/ 0x24458c19] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.020882220/ 0x24458c35] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.020904355/ 0x24458de2] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.020907949/ 0x24458e23] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.020910293/ 0x24458e50] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.020912324/ 0x24458e77] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.020913835/ 0x24458e93] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.020915970/ 0x24458ebd] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.020917585/ 0x24458edd] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:4
[ 28.020920501/ 0x24458f14] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc050
[ 28.020922845/ 0x24458f41] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 4, end 5
[ 28.020925189/ 0x24458f6e] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd040 <<-- host 0x100058cc040, size 16
[ 28.020966543/ 0x24459289] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:5
[ 28.020969928/ 0x244592ca] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 28.020971803/ 0x244592ed] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 28.020978887/ 0x24459375] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.020988939/ 0x24459437] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.020996595/ 0x244594c9] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.021000033/ 0x2445950c] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.021002428/ 0x24459539] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.021004355/ 0x2445955e] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.021005814/ 0x2445957a] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.021007949/ 0x244595a3] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.021009564/ 0x244595c2] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:5
[ 28.021012428/ 0x244595f9] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc060
[ 28.021014720/ 0x24459625] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 5, end 6
[ 28.021016960/ 0x24459650] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd050 <<-- host 0x100058cc050, size 16
[ 28.021037845/ 0x244597e1] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.021040397/ 0x24459813] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cb0000, size 52
[ 28.022030605/ 0x2445e258] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:6
[ 28.022034303/ 0x2445e29d] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 28.022036230/ 0x2445e2c2] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 28.023195345/ 0x244639b1] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.023197220/ 0x244639d5] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x2a, new-offset 0x2b
[ 28.023200241/ 0x24463a0f] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.023201960/ 0x24463a30] [0x0 mhi_dev_add_element] rd_ofset 43
[ 28.023203470/ 0x24463a4d] [0x0 mhi_dev_add_element] type 34
[ 28.023204980/ 0x24463a6b] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b532a0, size 16
[ 28.025331126/ 0x2446d9e1] [0x0 mhi_dev_send_event] ev.rp = 9b532b0 for 1
[ 28.025334303/ 0x2446da1e] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.027458626/ 0x24477972] [0x0 mhi_dev_send_event] event sent:
[ 28.027460918/ 0x2447799d] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc070
[ 28.027462741/ 0x244779bf] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.027464303/ 0x244779dd] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.027465814/ 0x244779fb] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.027467428/ 0x24477a19] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.027499564/ 0x24477c82] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.027502116/ 0x24477cb4] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cc0000, size 52
[ 28.027577272/ 0x2447825a] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.027589303/ 0x2447833e] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.029656074/ 0x24481e40] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.029657793/ 0x24481e60] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x2b, new-offset 0x2c
[ 28.029660710/ 0x24481e98] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.029662220/ 0x24481eb5] [0x0 mhi_dev_add_element] rd_ofset 44
[ 28.029663730/ 0x24481ed2] [0x0 mhi_dev_add_element] type 34
[ 28.029665241/ 0x24481eef] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b532b0, size 16
[ 28.031794564/ 0x2448bea4] [0x0 mhi_dev_send_event] ev.rp = 9b532c0 for 1
[ 28.031798210/ 0x2448bee9] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.033922376/ 0x24495e3a] [0x0 mhi_dev_send_event] event sent:
[ 28.033924616/ 0x24495e64] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc000
[ 28.033926439/ 0x24495e86] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.033927949/ 0x24495ea3] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.033929303/ 0x24495ebe] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.033930814/ 0x24495eda] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.033954147/ 0x2449609b] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.033958001/ 0x244960e4] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.033960345/ 0x24496112] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.033962272/ 0x24496136] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.033963730/ 0x24496152] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.033965866/ 0x2449617c] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.033967533/ 0x2449619b] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:6
[ 28.033970397/ 0x244961d2] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc070
[ 28.033972637/ 0x244961fd] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 6, end 7
[ 28.033974980/ 0x2449622a] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd060 <<-- host 0x100058cc060, size 16
[ 28.034014772/ 0x24496527] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:7
[ 28.034018053/ 0x24496565] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 28.034019928/ 0x24496589] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 28.034030501/ 0x24496654] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.034039199/ 0x244966fc] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.034046595/ 0x2449678a] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.034049876/ 0x244967c9] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.034052116/ 0x244967f3] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.034054199/ 0x2449681a] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.034055605/ 0x24496836] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.034057793/ 0x24496860] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.034059355/ 0x2449687e] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:7
[ 28.034062272/ 0x244968b6] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc000
[ 28.034064512/ 0x244968e1] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 7, end 0
[ 28.034067012/ 0x24496911] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd070 <<-- host 0x100058cc070, size 16
[ 28.034087533/ 0x24496a9b] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.034090033/ 0x24496acb] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cd0000, size 52
[ 28.035079668/ 0x2449b506] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:0
[ 28.035083522/ 0x2449b54f] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 28.035085501/ 0x2449b574] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 28.036245137/ 0x244a0c6d] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.036247012/ 0x244a0c91] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x2c, new-offset 0x2d
[ 28.036250033/ 0x244a0ccb] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.036251543/ 0x244a0ce8] [0x0 mhi_dev_add_element] rd_ofset 45
[ 28.036253053/ 0x244a0d05] [0x0 mhi_dev_add_element] type 34
[ 28.036254720/ 0x244a0d25] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b532c0, size 16
[ 28.038380137/ 0x244aac8f] [0x0 mhi_dev_send_event] ev.rp = 9b532d0 for 1
[ 28.038383470/ 0x244aaccd] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.040510553/ 0x244b4c57] [0x0 mhi_dev_send_event] event sent:
[ 28.040512793/ 0x244b4c80] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc010
[ 28.040514564/ 0x244b4ca2] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.040516126/ 0x244b4cbf] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.040517637/ 0x244b4cdd] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.040519095/ 0x244b4cf9] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.040550137/ 0x244b4f4e] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.040552741/ 0x244b4f7f] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ce0000, size 52
[ 28.040609668/ 0x244b53c6] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.040621439/ 0x244b54a7] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.042706699/ 0x244bf10b] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.042708366/ 0x244bf12b] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x2d, new-offset 0x2e
[ 28.042711387/ 0x244bf165] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.042712897/ 0x244bf182] [0x0 mhi_dev_add_element] rd_ofset 46
[ 28.042714408/ 0x244bf19f] [0x0 mhi_dev_add_element] type 34
[ 28.042716022/ 0x244bf1be] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b532d0, size 16
[ 28.044841751/ 0x244c9130] [0x0 mhi_dev_send_event] ev.rp = 9b532e0 for 1
[ 28.044845085/ 0x244c916d] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.046969303/ 0x244d30bf] [0x0 mhi_dev_send_event] event sent:
[ 28.046971543/ 0x244d30e9] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc020
[ 28.046973366/ 0x244d310b] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.046974876/ 0x244d3128] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.046976283/ 0x244d3142] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.046977689/ 0x244d315e] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.047000345/ 0x244d3312] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.047003731/ 0x244d3353] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.047006126/ 0x244d3380] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.047008053/ 0x244d33a5] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.047009512/ 0x244d33c1] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.047011908/ 0x244d33ef] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.047013626/ 0x244d3410] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:3 wp:0
[ 28.047016543/ 0x244d3448] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc010
[ 28.047018939/ 0x244d3476] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 0, end 1
[ 28.047021178/ 0x244d34a1] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd000 <<-- host 0x100058cc000, size 16
[ 28.047061803/ 0x244d37ae] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:3 with wr:1
[ 28.047065137/ 0x244d37ee] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 28.047067064/ 0x244d3812] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:3
[ 28.047085710/ 0x244d3978] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.047088262/ 0x244d39a9] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c80000, size 52
[ 28.047101491/ 0x244d3aaa] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.047111439/ 0x244d3b66] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.049219408/ 0x244dd980] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.049221178/ 0x244dd9a1] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x2e, new-offset 0x2f
[ 28.049224095/ 0x244dd9da] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.049225658/ 0x244dd9f7] [0x0 mhi_dev_add_element] rd_ofset 47
[ 28.049227168/ 0x244dda14] [0x0 mhi_dev_add_element] type 34
[ 28.049228939/ 0x244dda36] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b532e0, size 16
[ 28.051357793/ 0x244e79e2] [0x0 mhi_dev_send_event] ev.rp = 9b532f0 for 1
[ 28.051361439/ 0x244e7a27] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.053485606/ 0x244f1978] [0x0 mhi_dev_send_event] event sent:
[ 28.053487845/ 0x244f19a2] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc030
[ 28.053489772/ 0x244f19c6] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.053491283/ 0x244f19e3] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.053492637/ 0x244f19fd] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.053494251/ 0x244f1a1c] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.053514408/ 0x244f1ba0] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.053517845/ 0x244f1be1] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.053520085/ 0x244f1c0c] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.053522168/ 0x244f1c34] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.053523626/ 0x244f1c52] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.053526022/ 0x244f1c7e] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.053527637/ 0x244f1c9d] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:4 wp:1
[ 28.053530553/ 0x244f1cd5] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc020
[ 28.053532793/ 0x244f1d00] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 1, end 2
[ 28.053535033/ 0x244f1d2b] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd010 <<-- host 0x100058cc010, size 16
[ 28.053575345/ 0x244f2032] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:4 with wr:2
[ 28.053578470/ 0x244f206d] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 28.053580345/ 0x244f2091] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:4
[ 28.053587012/ 0x244f2113] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.053596908/ 0x244f21d3] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.053605085/ 0x244f226d] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.053608314/ 0x244f22aa] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.053610553/ 0x244f22d5] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.053612481/ 0x244f22fa] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.053613887/ 0x244f2315] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.053616022/ 0x244f233f] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.053617793/ 0x244f2360] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:4 wp:2
[ 28.053620762/ 0x244f239a] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc030
[ 28.053623053/ 0x244f23c5] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 2, end 3
[ 28.053625293/ 0x244f23f0] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd020 <<-- host 0x100058cc020, size 16
[ 28.053645814/ 0x244f257a] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.053648626/ 0x244f25b0] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c90000, size 52
[ 28.054640814/ 0x244f701d] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:4 with wr:3
[ 28.054644616/ 0x244f7064] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 28.054646595/ 0x244f7089] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:4
[ 28.055804251/ 0x244fc75c] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.055805970/ 0x244fc77d] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x2f, new-offset 0x30
[ 28.055808887/ 0x244fc7b5] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.055810397/ 0x244fc7d2] [0x0 mhi_dev_add_element] rd_ofset 48
[ 28.055812064/ 0x244fc7f2] [0x0 mhi_dev_add_element] type 34
[ 28.055813731/ 0x244fc812] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b532f0, size 16
[ 28.057940710/ 0x24506799] [0x0 mhi_dev_send_event] ev.rp = 9b53300 for 1
[ 28.057943939/ 0x245067d7] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.060071074/ 0x24510761] [0x0 mhi_dev_send_event] event sent:
[ 28.060073314/ 0x2451078a] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc040
[ 28.060075085/ 0x245107ac] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.060076751/ 0x245107cc] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.060078210/ 0x245107e8] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.060079668/ 0x24510804] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.060114460/ 0x24510aa0] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.060117168/ 0x24510ad4] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ca0000, size 52
[ 28.060239928/ 0x2451140b] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.060251647/ 0x245114eb] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.062271960/ 0x2451ac70] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.062273731/ 0x2451ac91] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x30, new-offset 0x31
[ 28.062276647/ 0x2451acca] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.062278158/ 0x2451ace7] [0x0 mhi_dev_add_element] rd_ofset 49
[ 28.062279720/ 0x2451ad04] [0x0 mhi_dev_add_element] type 34
[ 28.062281178/ 0x2451ad21] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53300, size 16
[ 28.064406074/ 0x24524c81] [0x0 mhi_dev_send_event] ev.rp = 9b53310 for 1
[ 28.064409356/ 0x24524cbf] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.066533626/ 0x2452ec12] [0x0 mhi_dev_send_event] event sent:
[ 28.066535866/ 0x2452ec3c] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc050
[ 28.066537793/ 0x2452ec60] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.066539460/ 0x2452ec7f] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.066540814/ 0x2452ec9a] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.066542272/ 0x2452ecb6] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.066561856/ 0x2452ee30] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.066565397/ 0x2452ee72] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.066567637/ 0x2452ee9d] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.066569668/ 0x2452eec4] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.066571126/ 0x2452eee0] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.066573314/ 0x2452ef0a] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.066574928/ 0x2452ef29] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:6 wp:3
[ 28.066577897/ 0x2452ef62] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc040
[ 28.066580189/ 0x2452ef8e] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 3, end 4
[ 28.066582533/ 0x2452efbb] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd030 <<-- host 0x100058cc030, size 16
[ 28.066622689/ 0x2452f2bf] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:6 with wr:4
[ 28.066625918/ 0x2452f2fc] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 28.066627793/ 0x2452f320] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:6
[ 28.066646491/ 0x2452f488] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.066649095/ 0x2452f4ba] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cb0000, size 52
[ 28.066710449/ 0x2452f955] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.066722637/ 0x2452fa3f] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.068778731/ 0x24539472] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.068780501/ 0x24539493] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x31, new-offset 0x32
[ 28.068783418/ 0x245394cc] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.068784928/ 0x245394e9] [0x0 mhi_dev_add_element] rd_ofset 50
[ 28.068786491/ 0x24539507] [0x0 mhi_dev_add_element] type 34
[ 28.068788001/ 0x24539524] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53310, size 16
[ 28.070916751/ 0x245434cd] [0x0 mhi_dev_send_event] ev.rp = 9b53320 for 1
[ 28.070920085/ 0x2454350d] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.073045137/ 0x2454d46f] [0x0 mhi_dev_send_event] event sent:
[ 28.073047376/ 0x2454d498] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc060
[ 28.073049147/ 0x2454d4ba] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.073050658/ 0x2454d4d7] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.073052064/ 0x2454d4f2] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.073053522/ 0x2454d50e] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.073076908/ 0x2454d6d0] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.073080501/ 0x2454d714] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.073082741/ 0x2454d740] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.073084772/ 0x2454d767] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.073086283/ 0x2454d783] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.073088418/ 0x2454d7ad] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.073090085/ 0x2454d7cc] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:4
[ 28.073092949/ 0x2454d803] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc050
[ 28.073095241/ 0x2454d82e] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 4, end 5
[ 28.073097429/ 0x2454d859] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd040 <<-- host 0x100058cc040, size 16
[ 28.073136647/ 0x2454db4c] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:5
[ 28.073139720/ 0x2454db86] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cc0000
[ 28.073141595/ 0x2454dba9] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 28.073160137/ 0x2454dd0e] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.073162793/ 0x2454dd40] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cc0000, size 52
[ 28.073193887/ 0x2454df97] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.073205345/ 0x2454e072] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.075293887/ 0x24557d15] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.075295762/ 0x24557d39] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x32, new-offset 0x33
[ 28.075298679/ 0x24557d71] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.075300189/ 0x24557d8e] [0x0 mhi_dev_add_element] rd_ofset 51
[ 28.075301751/ 0x24557dac] [0x0 mhi_dev_add_element] type 34
[ 28.075303470/ 0x24557dcd] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53320, size 16
[ 28.077429460/ 0x24561d42] [0x0 mhi_dev_send_event] ev.rp = 9b53330 for 1
[ 28.077432897/ 0x24561d83] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.079557324/ 0x2456bcd9] [0x0 mhi_dev_send_event] event sent:
[ 28.079559512/ 0x2456bd02] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc070
[ 28.079561335/ 0x2456bd24] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.079562949/ 0x2456bd43] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.079564460/ 0x2456bd60] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.079565918/ 0x2456bd7c] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.079585710/ 0x2456bef9] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.079589251/ 0x2456bf3d] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.079591543/ 0x2456bf68] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.079593470/ 0x2456bf8d] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.079594929/ 0x2456bfa9] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.079597116/ 0x2456bfd3] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.079598731/ 0x2456bff2] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:0 wp:5
[ 28.079601699/ 0x2456c02c] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc060
[ 28.079603991/ 0x2456c057] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 5, end 6
[ 28.079606335/ 0x2456c084] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd050 <<-- host 0x100058cc050, size 16
[ 28.079644460/ 0x2456c361] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:0 with wr:6
[ 28.079647481/ 0x2456c39a] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 28.079649356/ 0x2456c3be] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:0
[ 28.079668522/ 0x2456c52e] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.079671074/ 0x2456c55f] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cd0000, size 52
[ 28.079707533/ 0x2456c81d] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.079719304/ 0x2456c8fe] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.081803158/ 0x24576548] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.081804876/ 0x24576568] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x33, new-offset 0x34
[ 28.081807949/ 0x245765a3] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.081809668/ 0x245765c4] [0x0 mhi_dev_add_element] rd_ofset 52
[ 28.081811231/ 0x245765e2] [0x0 mhi_dev_add_element] type 34
[ 28.081812845/ 0x24576601] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53330, size 16
[ 28.083938366/ 0x2458056d] [0x0 mhi_dev_send_event] ev.rp = 9b53340 for 1
[ 28.083941699/ 0x245805ac] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.086066126/ 0x2458a502] [0x0 mhi_dev_send_event] event sent:
[ 28.086068418/ 0x2458a52c] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc000
[ 28.086070189/ 0x2458a54e] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.086071699/ 0x2458a56b] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.086073106/ 0x2458a585] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.086074512/ 0x2458a5a1] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.086098783/ 0x2458a77a] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.086102741/ 0x2458a7bf] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.086105085/ 0x2458a7ec] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.086107220/ 0x2458a815] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.086108783/ 0x2458a833] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.086110918/ 0x2458a85c] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.086112689/ 0x2458a87e] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:6
[ 28.086115554/ 0x2458a8b5] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc070
[ 28.086117793/ 0x2458a8e0] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 6, end 7
[ 28.086120397/ 0x2458a912] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd060 <<-- host 0x100058cc060, size 16
[ 28.086159147/ 0x2458abfb] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:7
[ 28.086162220/ 0x2458ac36] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ce0000
[ 28.086164095/ 0x2458ac59] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 28.086181647/ 0x2458adaa] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.086187637/ 0x2458ae1d] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.086196751/ 0x2458aecd] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.086201335/ 0x2458af25] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ce0000, size 52
[ 28.088357168/ 0x245950d4] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.088358835/ 0x245950f4] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x34, new-offset 0x35
[ 28.088361751/ 0x2459512c] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.088363314/ 0x2459514a] [0x0 mhi_dev_add_element] rd_ofset 53
[ 28.088364876/ 0x24595168] [0x0 mhi_dev_add_element] type 34
[ 28.088366335/ 0x24595184] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53340, size 16
[ 28.090495293/ 0x2459f133] [0x0 mhi_dev_send_event] ev.rp = 9b53350 for 1
[ 28.090498887/ 0x2459f176] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.092624356/ 0x245a90e0] [0x0 mhi_dev_send_event] event sent:
[ 28.092626595/ 0x245a910a] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc010
[ 28.092628418/ 0x245a912d] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.092629929/ 0x245a9149] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.092631439/ 0x245a9166] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.092632897/ 0x245a9182] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.092653106/ 0x245a9308] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.092656647/ 0x245a934b] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.092658991/ 0x245a9377] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.092661022/ 0x245a939e] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.092662481/ 0x245a93ba] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.092664616/ 0x245a93e4] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.092666283/ 0x245a9403] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:2 wp:7
[ 28.092669304/ 0x245a943d] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc000
[ 28.092671595/ 0x245a9468] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 7, end 0
[ 28.092673939/ 0x245a9496] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd070 <<-- host 0x100058cc070, size 16
[ 28.092711491/ 0x245a9768] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:2 with wr:0
[ 28.092714720/ 0x245a97a6] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 28.092716595/ 0x245a97c9] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:2
[ 28.092734720/ 0x245a9925] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.092737376/ 0x245a9959] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c80000, size 52
[ 28.092768731/ 0x245a9bb3] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.092780345/ 0x245a9c92] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.094867376/ 0x245b3919] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.094869251/ 0x245b393c] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x35, new-offset 0x36
[ 28.094872168/ 0x245b3974] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.094873731/ 0x245b3992] [0x0 mhi_dev_add_element] rd_ofset 54
[ 28.094875241/ 0x245b39af] [0x0 mhi_dev_add_element] type 34
[ 28.094876751/ 0x245b39cc] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53350, size 16
[ 28.097003210/ 0x245bd94a] [0x0 mhi_dev_send_event] ev.rp = 9b53360 for 1
[ 28.097006647/ 0x245bd98b] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.099131231/ 0x245c78e4] [0x0 mhi_dev_send_event] event sent:
[ 28.099133574/ 0x245c7910] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc020
[ 28.099135397/ 0x245c7932] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.099136908/ 0x245c794f] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.099138262/ 0x245c7969] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.099139720/ 0x245c7985] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.099162793/ 0x245c7b44] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.099166283/ 0x245c7b83] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.099168574/ 0x245c7bb0] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.099170501/ 0x245c7bd4] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.099172012/ 0x245c7bf0] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.099174147/ 0x245c7c1a] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.099175762/ 0x245c7c39] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:3 wp:0
[ 28.099178679/ 0x245c7c71] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc010
[ 28.099180918/ 0x245c7c9c] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 0, end 1
[ 28.099183158/ 0x245c7cc7] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd000 <<-- host 0x100058cc000, size 16
[ 28.099220137/ 0x245c7f8e] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:3 with wr:1
[ 28.099223470/ 0x245c7fcd] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 28.099225345/ 0x245c7ff1] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:3
[ 28.099232324/ 0x245c8078] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.099241387/ 0x245c8126] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.099249512/ 0x245c81c2] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.099252793/ 0x245c8200] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.099255033/ 0x245c822b] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.099256908/ 0x245c824f] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.099258366/ 0x245c826b] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.099260501/ 0x245c8294] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.099262116/ 0x245c82b4] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:3 wp:1
[ 28.099264981/ 0x245c82eb] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc020
[ 28.099267376/ 0x245c8318] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 1, end 2
[ 28.099269772/ 0x245c8347] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd010 <<-- host 0x100058cc010, size 16
[ 28.099290866/ 0x245c84db] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.099293314/ 0x245c850a] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c90000, size 52
[ 28.100288314/ 0x245ccfab] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:3 with wr:2
[ 28.100292116/ 0x245ccff3] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 28.100294095/ 0x245cd019] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:3
[ 28.101449304/ 0x245d26bd] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.101451179/ 0x245d26e1] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x36, new-offset 0x37
[ 28.101454095/ 0x245d2719] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.101455658/ 0x245d2737] [0x0 mhi_dev_add_element] rd_ofset 55
[ 28.101457116/ 0x245d2753] [0x0 mhi_dev_add_element] type 34
[ 28.101458627/ 0x245d2770] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53360, size 16
[ 28.103584460/ 0x245dc6e5] [0x0 mhi_dev_send_event] ev.rp = 9b53370 for 1
[ 28.103587585/ 0x245dc71d] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.105712324/ 0x245e6678] [0x0 mhi_dev_send_event] event sent:
[ 28.105714460/ 0x245e66a1] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc030
[ 28.105716283/ 0x245e66c3] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.105717845/ 0x245e66e1] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.105719252/ 0x245e66fc] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.105720658/ 0x245e6717] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.105752220/ 0x245e6975] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.105754772/ 0x245e69a7] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ca0000, size 52
[ 28.105869356/ 0x245e7240] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.105881179/ 0x245e7322] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.107909356/ 0x245f0b3e] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.107911179/ 0x245f0b61] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x37, new-offset 0x38
[ 28.107914095/ 0x245f0b99] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.107915762/ 0x245f0bb9] [0x0 mhi_dev_add_element] rd_ofset 56
[ 28.107917272/ 0x245f0bd6] [0x0 mhi_dev_add_element] type 34
[ 28.107918783/ 0x245f0bf3] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53370, size 16
[ 28.110047064/ 0x245fab97] [0x0 mhi_dev_send_event] ev.rp = 9b53380 for 1
[ 28.110050345/ 0x245fabd1] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.112174616/ 0x24604b25] [0x0 mhi_dev_send_event] event sent:
[ 28.112177324/ 0x24604b58] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc040
[ 28.112179147/ 0x24604b7a] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.112180762/ 0x24604b99] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.112182168/ 0x24604bb4] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.112183574/ 0x24604bcf] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.112206491/ 0x24604d88] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.112209981/ 0x24604dcb] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.112212377/ 0x24604df8] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.112214408/ 0x24604e1f] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.112215866/ 0x24604e3b] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.112218054/ 0x24604e65] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.112219668/ 0x24604e84] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:5 wp:2
[ 28.112222533/ 0x24604ebb] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc030
[ 28.112224824/ 0x24604ee6] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 2, end 3
[ 28.112227481/ 0x24604f1a] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd020 <<-- host 0x100058cc020, size 16
[ 28.112267689/ 0x2460521e] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:5 with wr:3
[ 28.112270814/ 0x2460525a] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 28.112272793/ 0x24605280] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:5
[ 28.112291699/ 0x246053eb] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.112294095/ 0x24605419] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cb0000, size 52
[ 28.112316283/ 0x246055c5] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.112327689/ 0x2460569f] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.114424460/ 0x2460f3e0] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.114426127/ 0x2460f400] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x38, new-offset 0x39
[ 28.114429095/ 0x2460f439] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.114430658/ 0x2460f457] [0x0 mhi_dev_add_element] rd_ofset 57
[ 28.114432168/ 0x2460f474] [0x0 mhi_dev_add_element] type 34
[ 28.114433679/ 0x2460f491] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53380, size 16
[ 28.116567324/ 0x24619499] [0x0 mhi_dev_send_event] ev.rp = 9b53390 for 1
[ 28.116572429/ 0x246194fc] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.118700137/ 0x2462348e] [0x0 mhi_dev_send_event] event sent:
[ 28.118702272/ 0x246234b6] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc050
[ 28.118704043/ 0x246234d8] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.118705502/ 0x246234f4] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.118706908/ 0x2462350f] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.118708522/ 0x2462352e] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.118734512/ 0x24623723] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.118738418/ 0x2462376c] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.118740918/ 0x2462379d] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.118743002/ 0x246237c4] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.118744460/ 0x246237e0] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.118746960/ 0x24623810] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.118748731/ 0x24623832] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:6 wp:3
[ 28.118751856/ 0x2462386e] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc040
[ 28.118754252/ 0x2462389c] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 3, end 4
[ 28.118756856/ 0x246238ce] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd030 <<-- host 0x100058cc030, size 16
[ 28.118799408/ 0x24623c00] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:6 with wr:4
[ 28.118802637/ 0x24623c3d] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cc0000
[ 28.118804720/ 0x24623c65] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:6
[ 28.118812949/ 0x24623d05] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.118822793/ 0x24623dc1] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.118830449/ 0x24623e53] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.118833679/ 0x24623e91] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.118835866/ 0x24623ebb] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.118837741/ 0x24623edf] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.118839199/ 0x24623efb] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.118841439/ 0x24623f26] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.118843054/ 0x24623f46] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:6 wp:4
[ 28.118845970/ 0x24623f7d] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc050
[ 28.118848210/ 0x24623fa8] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 4, end 5
[ 28.118850554/ 0x24623fd5] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd040 <<-- host 0x100058cc040, size 16
[ 28.118886543/ 0x24624288] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.118889616/ 0x246242c3] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cc0000, size 52
[ 28.119931179/ 0x246290e3] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:6 with wr:5
[ 28.119934929/ 0x2462912a] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cc0000
[ 28.119936908/ 0x2462914f] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:6
[ 28.121043418/ 0x2462e44c] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.121045710/ 0x2462e478] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x39, new-offset 0x3a
[ 28.121048835/ 0x2462e4b5] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.121050658/ 0x2462e4d7] [0x0 mhi_dev_add_element] rd_ofset 58
[ 28.121052116/ 0x2462e4f3] [0x0 mhi_dev_add_element] type 34
[ 28.121054252/ 0x2462e51c] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53390, size 16
[ 28.123182689/ 0x246384c3] [0x0 mhi_dev_send_event] ev.rp = 9b533a0 for 1
[ 28.123187949/ 0x24638523] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.125314824/ 0x246424a8] [0x0 mhi_dev_send_event] event sent:
[ 28.125317429/ 0x246424da] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc060
[ 28.125319199/ 0x246424fb] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.125320970/ 0x2464251d] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.125322637/ 0x2464253d] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.125324356/ 0x2464255e] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.125375554/ 0x24642935] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.125378314/ 0x2464296b] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cd0000, size 52
[ 28.125452689/ 0x24642eff] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.125466231/ 0x24643003] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.127537272/ 0x2464cb56] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.127539304/ 0x2464cb7d] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x3a, new-offset 0x3b
[ 28.127542481/ 0x2464cbba] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.127544304/ 0x2464cbdd] [0x0 mhi_dev_add_element] rd_ofset 59
[ 28.127545970/ 0x2464cbfd] [0x0 mhi_dev_add_element] type 34
[ 28.127547481/ 0x2464cc1a] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b533a0, size 16
[ 28.129671752/ 0x24656b6e] [0x0 mhi_dev_send_event] ev.rp = 9b533b0 for 1
[ 28.129674929/ 0x24656baa] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.131799825/ 0x24660b09] [0x0 mhi_dev_send_event] event sent:
[ 28.131803366/ 0x24660b4b] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc070
[ 28.131805189/ 0x24660b6e] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.131806960/ 0x24660b90] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.131808575/ 0x24660baf] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.131810085/ 0x24660bcc] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.131832741/ 0x24660d81] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.131836491/ 0x24660dc7] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.131839252/ 0x24660dfc] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.131841491/ 0x24660e27] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.131842950/ 0x24660e43] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.131845241/ 0x24660e6f] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.131846908/ 0x24660e8f] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:0 wp:5
[ 28.131850241/ 0x24660ed0] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc060
[ 28.131852793/ 0x24660f00] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 5, end 6
[ 28.131855502/ 0x24660f34] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd050 <<-- host 0x100058cc050, size 16
[ 28.131903054/ 0x246612c6] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:0 with wr:6
[ 28.131906752/ 0x2466130c] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ce0000
[ 28.131908627/ 0x24661330] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:0
[ 28.131939095/ 0x24661579] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.131949356/ 0x2466163f] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.131957533/ 0x246616db] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.131960658/ 0x24661717] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.131963106/ 0x24661746] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.131965033/ 0x2466176b] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.131966491/ 0x24661787] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.131968627/ 0x246617b1] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.131970241/ 0x246617d0] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:0 wp:6
[ 28.131973158/ 0x24661807] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc070
[ 28.131975762/ 0x24661839] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 6, end 7
[ 28.131978158/ 0x24661867] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd060 <<-- host 0x100058cc060, size 16
[ 28.131991908/ 0x2466196f] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.131994877/ 0x246619a8] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ce0000, size 52
[ 28.132989356/ 0x2466643f] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:0 with wr:7
[ 28.132993002/ 0x24666485] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ce0000
[ 28.132994981/ 0x246664aa] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:0
[ 28.134150606/ 0x2466bb56] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.134152429/ 0x2466bb79] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x3b, new-offset 0x3c
[ 28.134155606/ 0x2466bbb6] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.134157116/ 0x2466bbd3] [0x0 mhi_dev_add_element] rd_ofset 60
[ 28.134158783/ 0x2466bbf3] [0x0 mhi_dev_add_element] type 34
[ 28.134160554/ 0x2466bc15] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b533b0, size 16
[ 28.136285397/ 0x24675b74] [0x0 mhi_dev_send_event] ev.rp = 9b533c0 for 1
[ 28.136288939/ 0x24675bb6] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.138411804/ 0x2467faef] [0x0 mhi_dev_send_event] event sent:
[ 28.138414095/ 0x2467fb1a] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc000
[ 28.138415970/ 0x2467fb3d] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.138417533/ 0x2467fb5b] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.138418939/ 0x2467fb76] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.138420397/ 0x2467fb92] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.138458054/ 0x2467fe65] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.138460866/ 0x2467fe9c] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c80000, size 52
[ 28.138575033/ 0x2468072c] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.138586647/ 0x2468080b] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.140619720/ 0x2468a086] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.140621543/ 0x2468a0a8] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x3c, new-offset 0x3d
[ 28.140624616/ 0x2468a0e3] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.140626127/ 0x2468a100] [0x0 mhi_dev_add_element] rd_ofset 61
[ 28.140627637/ 0x2468a11d] [0x0 mhi_dev_add_element] type 34
[ 28.140629147/ 0x2468a13a] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b533c0, size 16
[ 28.142756700/ 0x246940ce] [0x0 mhi_dev_send_event] ev.rp = 9b533d0 for 1
[ 28.142760241/ 0x24694110] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.144885085/ 0x2469e06e] [0x0 mhi_dev_send_event] event sent:
[ 28.144887325/ 0x2469e098] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc010
[ 28.144889147/ 0x2469e0ba] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.144890762/ 0x2469e0d9] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.144892116/ 0x2469e0f3] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.144893731/ 0x2469e112] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.144915189/ 0x2469e2af] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.144918627/ 0x2469e2f1] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.144920970/ 0x2469e31d] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.144923054/ 0x2469e345] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.144924668/ 0x2469e364] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.144926960/ 0x2469e390] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.144928575/ 0x2469e3b0] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:2 wp:7
[ 28.144931595/ 0x2469e3ea] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc000
[ 28.144933887/ 0x2469e415] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 7, end 0
[ 28.144936752/ 0x2469e44c] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd070 <<-- host 0x100058cc070, size 16
[ 28.144979720/ 0x2469e786] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:2 with wr:0
[ 28.144982793/ 0x2469e7c0] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 28.144984668/ 0x2469e7e4] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:2
[ 28.144992637/ 0x2469e87e] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.145002741/ 0x2469e940] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.145010762/ 0x2469e9d9] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.145014200/ 0x2469ea1e] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.145016752/ 0x2469ea4c] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.145018887/ 0x2469ea75] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.145020293/ 0x2469ea90] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.145022429/ 0x2469eab9] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.145024043/ 0x2469ead9] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:2 wp:0
[ 28.145026960/ 0x2469eb10] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc010
[ 28.145029252/ 0x2469eb3c] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 0, end 1
[ 28.145031595/ 0x2469eb6a] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd000 <<-- host 0x100058cc000, size 16
[ 28.145055033/ 0x2469ed2b] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.145057377/ 0x2469ed58] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c90000, size 52
[ 28.146044772/ 0x246a3768] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:2 with wr:1
[ 28.146048679/ 0x246a37b2] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 28.146050658/ 0x246a37d8] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:2
[ 28.147213106/ 0x246a8f06] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.147214877/ 0x246a8f28] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x3d, new-offset 0x3e
[ 28.147217741/ 0x246a8f5f] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.147219304/ 0x246a8f7d] [0x0 mhi_dev_add_element] rd_ofset 62
[ 28.147220814/ 0x246a8f9a] [0x0 mhi_dev_add_element] type 34
[ 28.147222429/ 0x246a8fb9] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b533d0, size 16
[ 28.149348991/ 0x246b2f38] [0x0 mhi_dev_send_event] ev.rp = 9b533e0 for 1
[ 28.149352325/ 0x246b2f78] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.151481127/ 0x246bcf22] [0x0 mhi_dev_send_event] event sent:
[ 28.151483835/ 0x246bcf54] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc020
[ 28.151485606/ 0x246bcf77] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.151487220/ 0x246bcf94] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.151488627/ 0x246bcfb0] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.151490189/ 0x246bcfce] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.151526179/ 0x246bd282] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.151528783/ 0x246bd2b3] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ca0000, size 52
[ 28.151587377/ 0x246bd719] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.151600033/ 0x246bd80c] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.153684408/ 0x246c745f] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.153686335/ 0x246c7484] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x3e, new-offset 0x3f
[ 28.153689304/ 0x246c74bd] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.153690814/ 0x246c74da] [0x0 mhi_dev_add_element] rd_ofset 63
[ 28.153692377/ 0x246c74f8] [0x0 mhi_dev_add_element] type 34
[ 28.153693991/ 0x246c7517] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b533e0, size 16
[ 28.155819304/ 0x246d147e] [0x0 mhi_dev_send_event] ev.rp = 9b533f0 for 1
[ 28.155822793/ 0x246d14c0] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.157948054/ 0x246db427] [0x0 mhi_dev_send_event] event sent:
[ 28.157950554/ 0x246db455] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc030
[ 28.157952481/ 0x246db47a] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.157953939/ 0x246db496] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.157955293/ 0x246db4b0] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.157956908/ 0x246db4ce] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.157977481/ 0x246db65b] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.157980970/ 0x246db69d] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.157983418/ 0x246db6cc] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.157985450/ 0x246db6f3] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.157986960/ 0x246db710] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.157989095/ 0x246db739] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.157990710/ 0x246db758] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:4 wp:1
[ 28.157993731/ 0x246db792] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc020
[ 28.157996023/ 0x246db7be] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 1, end 2
[ 28.157998679/ 0x246db7f1] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd010 <<-- host 0x100058cc010, size 16
[ 28.158038262/ 0x246dbaea] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:4 with wr:2
[ 28.158041648/ 0x246dbb2b] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 28.158043523/ 0x246dbb4e] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:4
[ 28.158050606/ 0x246dbbd6] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.158060814/ 0x246dbc9b] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.158068262/ 0x246dbd2a] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.158071648/ 0x246dbd6a] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.158073991/ 0x246dbd97] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.158076023/ 0x246dbdbe] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.158077533/ 0x246dbdda] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.158079668/ 0x246dbe04] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.158081283/ 0x246dbe23] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:4 wp:2
[ 28.158084148/ 0x246dbe5a] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc030
[ 28.158086439/ 0x246dbe86] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 2, end 3
[ 28.158088627/ 0x246dbeb0] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd020 <<-- host 0x100058cc020, size 16
[ 28.158109095/ 0x246dc039] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.158111491/ 0x246dc067] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cb0000, size 52
[ 28.159103783/ 0x246e0ad5] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:4 with wr:3
[ 28.159107637/ 0x246e0b1e] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 28.159109616/ 0x246e0b43] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:4
[ 28.160267741/ 0x246e621f] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.160269460/ 0x246e6240] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x3f, new-offset 0x0
[ 28.160272429/ 0x246e6279] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.160273939/ 0x246e6296] [0x0 mhi_dev_add_element] rd_ofset 0
[ 28.160275450/ 0x246e62b2] [0x0 mhi_dev_add_element] type 34
[ 28.160277064/ 0x246e62d2] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b533f0, size 16
[ 28.162404252/ 0x246f025e] [0x0 mhi_dev_send_event] ev.rp = 9b53000 for 1
[ 28.162407898/ 0x246f02a2] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.164532637/ 0x246fa1ff] [0x0 mhi_dev_send_event] event sent:
[ 28.164534981/ 0x246fa22a] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc040
[ 28.164536908/ 0x246fa24f] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.164538523/ 0x246fa26e] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.164540137/ 0x246fa28d] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.164541595/ 0x246fa2a9] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.164576595/ 0x246fa549] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.164578991/ 0x246fa577] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cc0000, size 52
[ 28.164683054/ 0x246fad48] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.164695554/ 0x246fae37] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.166733679/ 0x24704711] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.166735398/ 0x24704732] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x0, new-offset 0x1
[ 28.166738158/ 0x24704767] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.166739668/ 0x24704784] [0x0 mhi_dev_add_element] rd_ofset 1
[ 28.166741127/ 0x247047a0] [0x0 mhi_dev_add_element] type 34
[ 28.166742585/ 0x247047bd] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53000, size 16
[ 28.168868262/ 0x2470e72b] [0x0 mhi_dev_send_event] ev.rp = 9b53010 for 1
[ 28.168871283/ 0x2470e764] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.170999148/ 0x247186fc] [0x0 mhi_dev_send_event] event sent:
[ 28.171001387/ 0x24718725] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc050
[ 28.171003158/ 0x24718747] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.171004668/ 0x24718763] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.171006075/ 0x2471877f] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.171007533/ 0x2471879b] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.171028106/ 0x24718927] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.171031648/ 0x2471896a] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.171033835/ 0x24718994] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.171035866/ 0x247189bb] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.171037377/ 0x247189d8] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.171039616/ 0x24718a03] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.171041231/ 0x24718a22] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:6 wp:3
[ 28.171044148/ 0x24718a5b] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc040
[ 28.171046543/ 0x24718a87] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 3, end 4
[ 28.171048835/ 0x24718ab4] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd030 <<-- host 0x100058cc030, size 16
[ 28.171088575/ 0x24718db0] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:6 with wr:4
[ 28.171092116/ 0x24718df3] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 28.171094148/ 0x24718e1a] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:6
[ 28.171104148/ 0x24718edb] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.171113106/ 0x24718f87] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.171120345/ 0x24719012] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.171123470/ 0x2471904e] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.171125762/ 0x24719079] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.171127793/ 0x247190a0] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.171129200/ 0x247190bb] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.171131335/ 0x247190e5] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.171132950/ 0x24719104] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:6 wp:4
[ 28.171135970/ 0x2471913d] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc050
[ 28.171138210/ 0x24719168] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 4, end 5
[ 28.171140398/ 0x24719192] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd040 <<-- host 0x100058cc040, size 16
[ 28.171161595/ 0x24719329] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.171164356/ 0x2471935e] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cd0000, size 52
[ 28.172153106/ 0x2471dd88] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:6 with wr:5
[ 28.172157064/ 0x2471ddd2] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 28.172158991/ 0x2471ddf7] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:6
[ 28.173320710/ 0x24723518] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.173322533/ 0x2472353b] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x1, new-offset 0x2
[ 28.173325502/ 0x24723574] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.173327012/ 0x24723591] [0x0 mhi_dev_add_element] rd_ofset 2
[ 28.173328470/ 0x247235af] [0x0 mhi_dev_add_element] type 34
[ 28.173330085/ 0x247235cc] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53010, size 16
[ 28.175464043/ 0x2472d5dc] [0x0 mhi_dev_send_event] ev.rp = 9b53020 for 1
[ 28.175470293/ 0x2472d650] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.177597950/ 0x247375e7] [0x0 mhi_dev_send_event] event sent:
[ 28.177600345/ 0x24737612] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc060
[ 28.177602273/ 0x24737636] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.177604043/ 0x24737658] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.177605606/ 0x24737676] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.177607325/ 0x24737697] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.177653158/ 0x24737a07] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.177656075/ 0x24737a40] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ce0000, size 52
[ 28.177689512/ 0x24737cc2] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.177703523/ 0x24737dcf] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.179812116/ 0x24741bf3] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.179814408/ 0x24741c1f] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x2, new-offset 0x3
[ 28.179817585/ 0x24741c5c] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.179819095/ 0x24741c79] [0x0 mhi_dev_add_element] rd_ofset 3
[ 28.179820762/ 0x24741c99] [0x0 mhi_dev_add_element] type 34
[ 28.179822429/ 0x24741cb9] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53020, size 16
[ 28.181948887/ 0x2474bc37] [0x0 mhi_dev_send_event] ev.rp = 9b53030 for 1
[ 28.181952950/ 0x2474bc83] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.184077429/ 0x24755bda] [0x0 mhi_dev_send_event] event sent:
[ 28.184079721/ 0x24755c06] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc070
[ 28.184081700/ 0x24755c2b] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.184083210/ 0x24755c48] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.184084616/ 0x24755c63] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.184086127/ 0x24755c80] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.184107950/ 0x24755e25] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.184111804/ 0x24755e6e] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.184114356/ 0x24755e9e] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.184116491/ 0x24755ec7] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.184118002/ 0x24755ee4] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.184120346/ 0x24755f11] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.184121960/ 0x24755f30] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:0 wp:5
[ 28.184125033/ 0x24755f6b] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc060
[ 28.184127533/ 0x24755f9b] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 5, end 6
[ 28.184130189/ 0x24755fce] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd050 <<-- host 0x100058cc050, size 16
[ 28.184172325/ 0x247562f8] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:0 with wr:6
[ 28.184175346/ 0x24756332] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 28.184177429/ 0x24756358] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:0
[ 28.184184825/ 0x247563e7] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.184194668/ 0x247564a5] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.184202793/ 0x24756541] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.184206023/ 0x2475657e] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.184208262/ 0x247565a9] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.184210189/ 0x247565ce] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.184211596/ 0x247565e9] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.184213731/ 0x24756612] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.184215346/ 0x24756631] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:0 wp:6
[ 28.184218262/ 0x2475666a] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc070
[ 28.184220658/ 0x24756696] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 6, end 7
[ 28.184222846/ 0x247566c1] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd060 <<-- host 0x100058cc060, size 16
[ 28.184252221/ 0x247568f5] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.184254721/ 0x24756925] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c80000, size 52
[ 28.185301648/ 0x2475b7ab] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:0 with wr:7
[ 28.185305450/ 0x2475b7f3] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 28.185307377/ 0x2475b818] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:0
[ 28.186398523/ 0x247609ef] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.186400554/ 0x24760a14] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x3, new-offset 0x4
[ 28.186403471/ 0x24760a4d] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.186405137/ 0x24760a6d] [0x0 mhi_dev_add_element] rd_ofset 4
[ 28.186406543/ 0x24760a88] [0x0 mhi_dev_add_element] type 34
[ 28.186408158/ 0x24760aa7] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53030, size 16
[ 28.188533210/ 0x2476aa09] [0x0 mhi_dev_send_event] ev.rp = 9b53040 for 1
[ 28.188536543/ 0x2476aa49] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.190661700/ 0x247749ad] [0x0 mhi_dev_send_event] event sent:
[ 28.190664252/ 0x247749dc] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc000
[ 28.190666075/ 0x247749ff] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.190667533/ 0x24774a1b] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.190669043/ 0x24774a39] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.190670762/ 0x24774a58] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.190709200/ 0x24774d3b] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.190712273/ 0x24774d76] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c90000, size 52
[ 28.190755085/ 0x247750ad] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.190766596/ 0x2477518c] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.192867637/ 0x2477ef1d] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.192869616/ 0x2477ef43] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x4, new-offset 0x5
[ 28.192872637/ 0x2477ef7d] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.192874304/ 0x2477ef9d] [0x0 mhi_dev_add_element] rd_ofset 5
[ 28.192875710/ 0x2477efb8] [0x0 mhi_dev_add_element] type 34
[ 28.192877221/ 0x2477efd5] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53040, size 16
[ 28.195001960/ 0x24788f31] [0x0 mhi_dev_send_event] ev.rp = 9b53050 for 1
[ 28.195005137/ 0x24788f6e] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.197127637/ 0x24792e9f] [0x0 mhi_dev_send_event] event sent:
[ 28.197129877/ 0x24792ec9] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc010
[ 28.197131752/ 0x24792eec] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.197133418/ 0x24792f0c] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.197134825/ 0x24792f27] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.197136439/ 0x24792f46] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.197156543/ 0x247930c9] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.197160502/ 0x24793114] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.197162898/ 0x24793142] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.197164981/ 0x2479316a] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.197166491/ 0x24793187] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.197168627/ 0x247931b0] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.197170293/ 0x247931d0] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:2 wp:7
[ 28.197173210/ 0x24793208] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc000
[ 28.197175398/ 0x24793232] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 7, end 0
[ 28.197178106/ 0x24793266] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd070 <<-- host 0x100058cc070, size 16
[ 28.197220033/ 0x2479358f] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:2 with wr:0
[ 28.197223523/ 0x247935cf] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ca0000
[ 28.197225450/ 0x247935f3] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:2
[ 28.197244096/ 0x2479375a] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.197246648/ 0x2479378a] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ca0000, size 52
[ 28.197270241/ 0x24793950] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.197280346/ 0x24793a12] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.199385554/ 0x2479d7f5] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.199387533/ 0x2479d81b] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x5, new-offset 0x6
[ 28.199390606/ 0x2479d856] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.199392116/ 0x2479d873] [0x0 mhi_dev_add_element] rd_ofset 6
[ 28.199393679/ 0x2479d891] [0x0 mhi_dev_add_element] type 34
[ 28.199395398/ 0x2479d8b2] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53050, size 16
[ 28.201524721/ 0x247a7867] [0x0 mhi_dev_send_event] ev.rp = 9b53060 for 1
[ 28.201529148/ 0x247a78ba] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.203655710/ 0x247b183a] [0x0 mhi_dev_send_event] event sent:
[ 28.203658106/ 0x247b1867] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc020
[ 28.203659981/ 0x247b188a] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.203661648/ 0x247b18a9] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.203663054/ 0x247b18c5] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.203664616/ 0x247b18e3] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.203692637/ 0x247b1aff] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.203696283/ 0x247b1b43] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.203698731/ 0x247b1b72] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.203700814/ 0x247b1b9a] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.203702377/ 0x247b1bb8] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.203704773/ 0x247b1be6] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.203706387/ 0x247b1c06] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:3 wp:0
[ 28.203709721/ 0x247b1c45] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc010
[ 28.203712012/ 0x247b1c71] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 0, end 1
[ 28.203714460/ 0x247b1ca0] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd000 <<-- host 0x100058cc000, size 16
[ 28.203756543/ 0x247b1fc9] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:3 with wr:1
[ 28.203759616/ 0x247b2003] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 28.203761491/ 0x247b2027] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:3
[ 28.203772012/ 0x247b20f2] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.203785033/ 0x247b21ec] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.203793887/ 0x247b2296] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.203797325/ 0x247b22d8] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.203799616/ 0x247b2303] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.203801491/ 0x247b2327] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.203802950/ 0x247b2343] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.203805085/ 0x247b236c] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.203806700/ 0x247b238b] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:3 wp:1
[ 28.203809721/ 0x247b23c5] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc020
[ 28.203812064/ 0x247b23f2] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 1, end 2
[ 28.203814304/ 0x247b241d] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd010 <<-- host 0x100058cc010, size 16
[ 28.203843314/ 0x247b264a] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.203846231/ 0x247b2682] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cb0000, size 52
[ 28.204849668/ 0x247b71c5] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:3 with wr:2
[ 28.204853575/ 0x247b7210] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 28.204855502/ 0x247b7234] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:3
[ 28.206003158/ 0x247bc848] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.206005033/ 0x247bc86a] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x6, new-offset 0x7
[ 28.206007898/ 0x247bc8a2] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.206009408/ 0x247bc8bf] [0x0 mhi_dev_add_element] rd_ofset 7
[ 28.206010866/ 0x247bc8db] [0x0 mhi_dev_add_element] type 34
[ 28.206012377/ 0x247bc8f8] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53060, size 16
[ 28.208136596/ 0x247c684a] [0x0 mhi_dev_send_event] ev.rp = 9b53070 for 1
[ 28.208139929/ 0x247c688a] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.210264877/ 0x247d07e9] [0x0 mhi_dev_send_event] event sent:
[ 28.210267898/ 0x247d0822] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc030
[ 28.210269669/ 0x247d0844] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.210271283/ 0x247d0862] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.210272689/ 0x247d087e] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.210274252/ 0x247d089c] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.210308627/ 0x247d0b31] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.210311700/ 0x247d0b6b] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cc0000, size 52
[ 28.210382898/ 0x247d10c3] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.210394773/ 0x247d11a8] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.212466127/ 0x247dad01] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.212467898/ 0x247dad22] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x7, new-offset 0x8
[ 28.212470814/ 0x247dad5a] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.212472325/ 0x247dad77] [0x0 mhi_dev_add_element] rd_ofset 8
[ 28.212473731/ 0x247dad92] [0x0 mhi_dev_add_element] type 34
[ 28.212475554/ 0x247dadb5] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53070, size 16
[ 28.214600189/ 0x247e4d0f] [0x0 mhi_dev_send_event] ev.rp = 9b53080 for 1
[ 28.214603471/ 0x247e4d4d] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.216725762/ 0x247eec7a] [0x0 mhi_dev_send_event] event sent:
[ 28.216727794/ 0x247eeca0] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc040
[ 28.216729564/ 0x247eecc2] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.216731179/ 0x247eece1] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.216732585/ 0x247eecfc] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.216734096/ 0x247eed19] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.216757169/ 0x247eeed5] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.216760971/ 0x247eef1d] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.216763210/ 0x247eef48] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.216765189/ 0x247eef6e] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.216766804/ 0x247eef8d] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.216768991/ 0x247eefb7] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.216770710/ 0x247eefd8] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:5 wp:2
[ 28.216773627/ 0x247ef010] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc030
[ 28.216776075/ 0x247ef03f] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 2, end 3
[ 28.216778783/ 0x247ef073] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd020 <<-- host 0x100058cc020, size 16
[ 28.216821023/ 0x247ef39f] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:5 with wr:3
[ 28.216824356/ 0x247ef3de] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 28.216826283/ 0x247ef403] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:5
[ 28.216833679/ 0x247ef491] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.216843991/ 0x247ef558] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.216851544/ 0x247ef5e8] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.216854773/ 0x247ef626] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.216857221/ 0x247ef655] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.216859096/ 0x247ef679] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.216860554/ 0x247ef695] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.216862689/ 0x247ef6be] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.216864252/ 0x247ef6dc] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:5 wp:3
[ 28.216867116/ 0x247ef714] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc040
[ 28.216869408/ 0x247ef73f] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 3, end 4
[ 28.216871596/ 0x247ef769] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd030 <<-- host 0x100058cc030, size 16
[ 28.216893314/ 0x247ef90a] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.216896075/ 0x247ef93f] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cd0000, size 52
[ 28.217886596/ 0x247f438b] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:5 with wr:4
[ 28.217890189/ 0x247f43d1] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 28.217892429/ 0x247f43f9] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:5
[ 28.219049773/ 0x247f9ac6] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.219051491/ 0x247f9ae7] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x8, new-offset 0x9
[ 28.219054304/ 0x247f9b1d] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.219055814/ 0x247f9b3a] [0x0 mhi_dev_add_element] rd_ofset 9
[ 28.219057273/ 0x247f9b56] [0x0 mhi_dev_add_element] type 34
[ 28.219058939/ 0x247f9b76] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53080, size 16
[ 28.221188939/ 0x24803b38] [0x0 mhi_dev_send_event] ev.rp = 9b53090 for 1
[ 28.221193106/ 0x24803b87] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.223320919/ 0x2480db1e] [0x0 mhi_dev_send_event] event sent:
[ 28.223323575/ 0x2480db50] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc050
[ 28.223325450/ 0x2480db73] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.223327012/ 0x2480db90] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.223328523/ 0x2480dbae] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.223329981/ 0x2480dbca] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.223362898/ 0x2480de42] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.223365554/ 0x2480de75] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ce0000, size 52
[ 28.223501127/ 0x2480e8a2] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.223514460/ 0x2480e9a1] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.225522950/ 0x24818043] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.225524773/ 0x24818066] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x9, new-offset 0xa
[ 28.225527585/ 0x2481809c] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.225529096/ 0x248180b9] [0x0 mhi_dev_add_element] rd_ofset 10
[ 28.225530606/ 0x248180d6] [0x0 mhi_dev_add_element] type 34
[ 28.225532169/ 0x248180f4] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53090, size 16
[ 28.227659148/ 0x2482207d] [0x0 mhi_dev_send_event] ev.rp = 9b530a0 for 1
[ 28.227662377/ 0x248220b8] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.229788158/ 0x2482c029] [0x0 mhi_dev_send_event] event sent:
[ 28.229790606/ 0x2482c057] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc060
[ 28.229792377/ 0x2482c078] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.229794044/ 0x2482c098] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.229795450/ 0x2482c0b3] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.229796908/ 0x2482c0cf] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.229819721/ 0x2482c286] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.229823366/ 0x2482c2cb] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.229825658/ 0x2482c2f7] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.229827741/ 0x2482c31f] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.229829200/ 0x2482c33b] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.229831335/ 0x2482c365] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.229832950/ 0x2482c384] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:4
[ 28.229835919/ 0x2482c3bc] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc050
[ 28.229838314/ 0x2482c3ea] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 4, end 5
[ 28.229840658/ 0x2482c417] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd040 <<-- host 0x100058cc040, size 16
[ 28.229882377/ 0x2482c739] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:5
[ 28.229886075/ 0x2482c77f] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 28.229887950/ 0x2482c7a3] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 28.229895294/ 0x2482c830] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.229905502/ 0x2482c8f4] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.229913158/ 0x2482c988] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.229916648/ 0x2482c9ca] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.229919096/ 0x2482c9f9] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.229921179/ 0x2482ca21] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.229922637/ 0x2482ca3d] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.229924721/ 0x2482ca66] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.229926335/ 0x2482ca84] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:5
[ 28.229929252/ 0x2482cabc] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc060
[ 28.229931648/ 0x2482caea] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 5, end 6
[ 28.229933835/ 0x2482cb14] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd050 <<-- host 0x100058cc050, size 16
[ 28.229954825/ 0x2482cca7] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.229957481/ 0x2482ccda] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c80000, size 52
[ 28.230953262/ 0x2483178a] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:6
[ 28.230957221/ 0x248317d5] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 28.230959148/ 0x248317fb] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 28.232111700/ 0x24836e6c] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.232113575/ 0x24836e8f] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0xa, new-offset 0xb
[ 28.232116387/ 0x24836ec5] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.232118054/ 0x24836ee5] [0x0 mhi_dev_add_element] rd_ofset 11
[ 28.232119564/ 0x24836f02] [0x0 mhi_dev_add_element] type 34
[ 28.232121127/ 0x24836f20] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b530a0, size 16
[ 28.234245814/ 0x24840e7b] [0x0 mhi_dev_send_event] ev.rp = 9b530b0 for 1
[ 28.234249148/ 0x24840eba] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.236371231/ 0x2484ade3] [0x0 mhi_dev_send_event] event sent:
[ 28.236373367/ 0x2484ae0c] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc070
[ 28.236375242/ 0x2484ae2f] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.236376752/ 0x2484ae4c] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.236378210/ 0x2484ae68] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.236379825/ 0x2484ae86] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.236413002/ 0x2484b104] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.236415762/ 0x2484b139] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c90000, size 52
[ 28.236499096/ 0x2484b77a] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.236510502/ 0x2484b855] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.238569148/ 0x248552ba] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.238570867/ 0x248552db] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0xb, new-offset 0xc
[ 28.238573679/ 0x24855311] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.238575189/ 0x2485532e] [0x0 mhi_dev_add_element] rd_ofset 12
[ 28.238576700/ 0x2485534b] [0x0 mhi_dev_add_element] type 34
[ 28.238578210/ 0x2485536b] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b530b0, size 16
[ 28.240708367/ 0x2485f332] [0x0 mhi_dev_send_event] ev.rp = 9b530c0 for 1
[ 28.240714304/ 0x2485f39e] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.242846492/ 0x2486938c] [0x0 mhi_dev_send_event] event sent:
[ 28.242850502/ 0x248693d4] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc000
[ 28.242852689/ 0x248693fe] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.242854460/ 0x24869420] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.242855971/ 0x2486943d] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.242857481/ 0x2486945a] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.242885971/ 0x2486967e] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.242890398/ 0x248696d2] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.242893106/ 0x24869706] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.242895294/ 0x24869730] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.242896856/ 0x2486974e] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.242899252/ 0x2486977d] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.242900867/ 0x2486979c] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:6
[ 28.242903887/ 0x248697d5] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc070
[ 28.242911648/ 0x2486986a] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 6, end 7
[ 28.242914564/ 0x248698a2] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd060 <<-- host 0x100058cc060, size 16
[ 28.242976752/ 0x24869d4d] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:7
[ 28.242980346/ 0x24869d92] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ca0000
[ 28.242982377/ 0x24869db8] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 28.243016231/ 0x2486a042] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.243019408/ 0x2486a07f] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ca0000, size 52
[ 28.243049356/ 0x2486a2c3] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.243062742/ 0x2486a3c0] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.248282794/ 0x24882b41] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.248285294/ 0x24882b70] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0xc, new-offset 0xd
[ 28.248288627/ 0x24882bb1] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.248290450/ 0x24882bd3] [0x0 mhi_dev_add_element] rd_ofset 13
[ 28.248292377/ 0x24882bf8] [0x0 mhi_dev_add_element] type 34
[ 28.248294512/ 0x24882c21] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b530c0, size 16
[ 28.253541752/ 0x2489b5ad] [0x0 mhi_dev_send_event] ev.rp = 9b530d0 for 1
[ 28.253547273/ 0x2489b617] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.255674096/ 0x248a559a] [0x0 mhi_dev_send_event] event sent:
[ 28.255676648/ 0x248a55ca] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc010
[ 28.255678523/ 0x248a55ee] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.255680242/ 0x248a560f] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.255681908/ 0x248a562f] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.255683627/ 0x248a564f] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.255716752/ 0x248a58cd] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.255720814/ 0x248a591a] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.255723523/ 0x248a594e] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.255725658/ 0x248a5977] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.255727273/ 0x248a5996] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.255730033/ 0x248a59ce] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.255732169/ 0x248a59f5] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:2 wp:7
[ 28.255735606/ 0x248a5a36] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc000
[ 28.255738106/ 0x248a5a66] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 7, end 0
[ 28.255741387/ 0x248a5aa5] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd070 <<-- host 0x100058cc070, size 16
[ 28.255798679/ 0x248a5ef2] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:2 with wr:0
[ 28.255802585/ 0x248a5f3c] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 28.255804773/ 0x248a5f66] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:2
[ 28.255849096/ 0x248a62b9] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.255861596/ 0x248a63a9] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.255870502/ 0x248a6454] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.255873887/ 0x248a6495] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.255876335/ 0x248a64c4] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.255878575/ 0x248a64ef] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.255880189/ 0x248a650e] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.255882481/ 0x248a653a] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.255884096/ 0x248a6559] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:2 wp:0
[ 28.255887117/ 0x248a6593] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc010
[ 28.255889617/ 0x248a65c3] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 0, end 1
[ 28.255891804/ 0x248a65ed] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd000 <<-- host 0x100058cc000, size 16
[ 28.255913158/ 0x248a6787] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.255917012/ 0x248a67d1] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cb0000, size 52
[ 28.256867950/ 0x248aaf25] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:2 with wr:1
[ 28.256872169/ 0x248aaf74] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 28.256874044/ 0x248aaf98] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:2
[ 28.258075762/ 0x248b09ba] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.258077898/ 0x248b09e2] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0xd, new-offset 0xe
[ 28.258081179/ 0x248b0a21] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.258082689/ 0x248b0a3e] [0x0 mhi_dev_add_element] rd_ofset 14
[ 28.258084252/ 0x248b0a5c] [0x0 mhi_dev_add_element] type 34
[ 28.258085919/ 0x248b0a7c] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b530d0, size 16
[ 28.260212481/ 0x248ba9fc] [0x0 mhi_dev_send_event] ev.rp = 9b530e0 for 1
[ 28.260216492/ 0x248baa48] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.262341335/ 0x248c49a5] [0x0 mhi_dev_send_event] event sent:
[ 28.262343367/ 0x248c49cc] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc020
[ 28.262345398/ 0x248c49f2] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.262347012/ 0x248c4a11] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.262348523/ 0x248c4a2e] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.262350242/ 0x248c4a4f] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.262392221/ 0x248c4d75] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.262394929/ 0x248c4da9] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cc0000, size 52
[ 28.262503262/ 0x248c55ca] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.262515189/ 0x248c56ae] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.264548835/ 0x248cef34] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.264550658/ 0x248cef57] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0xe, new-offset 0xf
[ 28.264553471/ 0x248cef8d] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.264554981/ 0x248cefaa] [0x0 mhi_dev_add_element] rd_ofset 15
[ 28.264556492/ 0x248cefc7] [0x0 mhi_dev_add_element] type 34
[ 28.264558262/ 0x248cefeb] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b530e0, size 16
[ 28.266682585/ 0x248d8f3e] [0x0 mhi_dev_send_event] ev.rp = 9b530f0 for 1
[ 28.266685606/ 0x248d8f76] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.268808471/ 0x248e2eae] [0x0 mhi_dev_send_event] event sent:
[ 28.268810658/ 0x248e2ed8] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc030
[ 28.268812533/ 0x248e2efc] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.268814200/ 0x248e2f1b] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.268815606/ 0x248e2f36] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.268817273/ 0x248e2f56] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.268837169/ 0x248e30d5] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.268840815/ 0x248e311a] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.268843315/ 0x248e314a] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.268845450/ 0x248e3173] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.268846960/ 0x248e3190] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.268849096/ 0x248e31b9] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.268850867/ 0x248e31db] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:4 wp:1
[ 28.268853940/ 0x248e3216] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc020
[ 28.268856127/ 0x248e3240] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 1, end 2
[ 28.268858783/ 0x248e3273] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd010 <<-- host 0x100058cc010, size 16
[ 28.268899669/ 0x248e3585] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:4 with wr:2
[ 28.268903419/ 0x248e35cc] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 28.268905710/ 0x248e35f8] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:4
[ 28.268931387/ 0x248e37e5] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.268933992/ 0x248e3817] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cd0000, size 52
[ 28.269015137/ 0x248e3e2e] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.269025815/ 0x248e3efb] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.271077481/ 0x248ed8da] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.271079252/ 0x248ed8fc] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0xf, new-offset 0x10
[ 28.271082273/ 0x248ed936] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.271083835/ 0x248ed954] [0x0 mhi_dev_add_element] rd_ofset 16
[ 28.271085346/ 0x248ed971] [0x0 mhi_dev_add_element] type 34
[ 28.271087012/ 0x248ed991] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b530f0, size 16
[ 28.273215867/ 0x248f793d] [0x0 mhi_dev_send_event] ev.rp = 9b53100 for 1
[ 28.273219617/ 0x248f7983] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.275345242/ 0x249018f1] [0x0 mhi_dev_send_event] event sent:
[ 28.275347690/ 0x2490191f] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc040
[ 28.275349512/ 0x24901941] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.275351179/ 0x24901961] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.275352585/ 0x2490197c] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.275354044/ 0x24901998] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.275378887/ 0x24901b76] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.275382429/ 0x24901bb9] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.275384773/ 0x24901be6] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.275386908/ 0x24901c0f] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.275388523/ 0x24901c2e] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.275390658/ 0x24901c57] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.275392429/ 0x24901c79] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:5 wp:2
[ 28.275395450/ 0x24901cb3] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc030
[ 28.275397690/ 0x24901cde] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 2, end 3
[ 28.275400242/ 0x24901d0f] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd020 <<-- host 0x100058cc020, size 16
[ 28.275439148/ 0x24901ffb] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:5 with wr:3
[ 28.275442637/ 0x2490203e] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ce0000
[ 28.275444565/ 0x24902062] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:5
[ 28.275471440/ 0x24902266] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.275473940/ 0x24902296] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ce0000, size 52
[ 28.275512846/ 0x24902583] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.275525450/ 0x24902674] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.277614304/ 0x2490c31d] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.277616023/ 0x2490c33e] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x10, new-offset 0x11
[ 28.277618940/ 0x2490c376] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.277620450/ 0x2490c393] [0x0 mhi_dev_add_element] rd_ofset 17
[ 28.277621960/ 0x2490c3b0] [0x0 mhi_dev_add_element] type 34
[ 28.277623575/ 0x2490c3cf] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53100, size 16
[ 28.279750606/ 0x24916358] [0x0 mhi_dev_send_event] ev.rp = 9b53110 for 1
[ 28.279754096/ 0x2491639a] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.281883940/ 0x24920358] [0x0 mhi_dev_send_event] event sent:
[ 28.281886804/ 0x2492038e] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc050
[ 28.281888627/ 0x249203b0] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.281890137/ 0x249203cd] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.281891544/ 0x249203e8] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.281893002/ 0x24920403] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.281913002/ 0x24920585] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.281916544/ 0x249205c9] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.281918940/ 0x249205f6] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.281920919/ 0x2492061c] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.281922429/ 0x24920639] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.281924565/ 0x24920662] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.281926179/ 0x24920681] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:6 wp:3
[ 28.281929096/ 0x249206b9] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc040
[ 28.281931335/ 0x249206e4] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 3, end 4
[ 28.281933783/ 0x24920713] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd030 <<-- host 0x100058cc030, size 16
[ 28.281973627/ 0x24920a11] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:6 with wr:4
[ 28.281977377/ 0x24920a58] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 28.281979356/ 0x24920a7e] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:6
[ 28.281998315/ 0x24920bea] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.282000919/ 0x24920c1c] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c80000, size 52
[ 28.282064617/ 0x249210e6] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.282077429/ 0x249211da] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.284132846/ 0x2492ac01] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.284134617/ 0x2492ac22] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x11, new-offset 0x12
[ 28.284137481/ 0x2492ac5a] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.284139304/ 0x2492ac7d] [0x0 mhi_dev_add_element] rd_ofset 18
[ 28.284140762/ 0x2492ac99] [0x0 mhi_dev_add_element] type 34
[ 28.284142273/ 0x2492acb7] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53110, size 16
[ 28.286269721/ 0x24934c47] [0x0 mhi_dev_send_event] ev.rp = 9b53120 for 1
[ 28.286273158/ 0x24934c87] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.288398992/ 0x2493ebf9] [0x0 mhi_dev_send_event] event sent:
[ 28.288401179/ 0x2493ec21] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc060
[ 28.288402950/ 0x2493ec43] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.288404460/ 0x2493ec60] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.288406023/ 0x2493ec7e] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.288407585/ 0x2493ec9c] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.288430294/ 0x2493ee51] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.288433783/ 0x2493ee93] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.288436075/ 0x2493eebf] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.288438158/ 0x2493eee7] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.288439617/ 0x2493ef03] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.288441804/ 0x2493ef2d] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.288443523/ 0x2493ef4e] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:4
[ 28.288446440/ 0x2493ef86] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc050
[ 28.288448679/ 0x2493efb1] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 4, end 5
[ 28.288450867/ 0x2493efdb] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd040 <<-- host 0x100058cc040, size 16
[ 28.288491023/ 0x2493f2df] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:5
[ 28.288494512/ 0x2493f321] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 28.288496440/ 0x2493f346] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 28.288514981/ 0x2493f4aa] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.288517325/ 0x2493f4d7] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c90000, size 52
[ 28.288560033/ 0x2493f80d] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.288571335/ 0x2493f8e5] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.290651231/ 0x249494e2] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.290653106/ 0x24949506] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x12, new-offset 0x13
[ 28.290656023/ 0x2494953e] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.290657585/ 0x2494955c] [0x0 mhi_dev_add_element] rd_ofset 19
[ 28.290659044/ 0x24949578] [0x0 mhi_dev_add_element] type 34
[ 28.290660554/ 0x24949595] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53120, size 16
[ 28.292788210/ 0x2495352a] [0x0 mhi_dev_send_event] ev.rp = 9b53130 for 1
[ 28.292791700/ 0x2495356b] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.294916752/ 0x2495d4ce] [0x0 mhi_dev_send_event] event sent:
[ 28.294918940/ 0x2495d4f6] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc070
[ 28.294920710/ 0x2495d518] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.294922273/ 0x2495d536] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.294923731/ 0x2495d552] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.294925294/ 0x2495d570] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.294945294/ 0x2495d6f1] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.294948888/ 0x2495d735] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.294951283/ 0x2495d763] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.294953419/ 0x2495d78c] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.294954877/ 0x2495d7a8] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.294957013/ 0x2495d7d1] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.294958627/ 0x2495d7f1] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:0 wp:5
[ 28.294961544/ 0x2495d828] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc060
[ 28.294963940/ 0x2495d856] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 5, end 6
[ 28.294966283/ 0x2495d883] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd050 <<-- host 0x100058cc050, size 16
[ 28.295006127/ 0x2495db81] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:0 with wr:6
[ 28.295009408/ 0x2495dbc0] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ca0000
[ 28.295011335/ 0x2495dbe4] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:0
[ 28.295018106/ 0x2495dc66] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.295027950/ 0x2495dd23] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.295036023/ 0x2495ddbf] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.295039356/ 0x2495ddfe] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.295041544/ 0x2495de29] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.295043471/ 0x2495de4d] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.295044929/ 0x2495de69] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.295047065/ 0x2495de92] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.295048627/ 0x2495deb0] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:0 wp:6
[ 28.295051492/ 0x2495dee8] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc070
[ 28.295053783/ 0x2495df13] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 6, end 7
[ 28.295056023/ 0x2495df3e] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd060 <<-- host 0x100058cc060, size 16
[ 28.295075815/ 0x2495e0ba] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.295078575/ 0x2495e0ef] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ca0000, size 52
[ 28.296070763/ 0x24962b5e] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:0 with wr:7
[ 28.296074565/ 0x24962ba2] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ca0000
[ 28.296076648/ 0x24962bca] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:0
[ 28.297234148/ 0x2496829a] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.297236075/ 0x249682bf] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x13, new-offset 0x14
[ 28.297238992/ 0x249682f7] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.297240554/ 0x24968315] [0x0 mhi_dev_add_element] rd_ofset 20
[ 28.297242221/ 0x24968334] [0x0 mhi_dev_add_element] type 34
[ 28.297243679/ 0x24968351] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53130, size 16
[ 28.299369877/ 0x249722ca] [0x0 mhi_dev_send_event] ev.rp = 9b53140 for 1
[ 28.299373419/ 0x2497230c] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.301502117/ 0x2497c2b5] [0x0 mhi_dev_send_event] event sent:
[ 28.301504565/ 0x2497c2e3] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc000
[ 28.301506388/ 0x2497c305] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.301507898/ 0x2497c322] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.301509252/ 0x2497c33c] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.301510710/ 0x2497c358] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.301544408/ 0x2497c5df] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.301546960/ 0x2497c610] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cb0000, size 52
[ 28.301735867/ 0x2497d43e] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.301747481/ 0x2497d51b] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.303703367/ 0x249867cb] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.303705085/ 0x249867ec] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x14, new-offset 0x15
[ 28.303707950/ 0x24986823] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.303709513/ 0x24986841] [0x0 mhi_dev_add_element] rd_ofset 21
[ 28.303711023/ 0x2498685e] [0x0 mhi_dev_add_element] type 34
[ 28.303712585/ 0x2498687c] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53140, size 16
[ 28.305838940/ 0x249907f8] [0x0 mhi_dev_send_event] ev.rp = 9b53150 for 1
[ 28.305842273/ 0x24990837] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.307967065/ 0x2499a794] [0x0 mhi_dev_send_event] event sent:
[ 28.307969252/ 0x2499a7bd] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc010
[ 28.307971075/ 0x2499a7df] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.307972638/ 0x2499a7fc] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.307974044/ 0x2499a818] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.307975450/ 0x2499a833] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.307994721/ 0x2499a9a6] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.307998315/ 0x2499a9ea] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.308000554/ 0x2499aa15] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.308002585/ 0x2499aa3c] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.308004096/ 0x2499aa59] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.308006335/ 0x2499aa85] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.308007950/ 0x2499aaa3] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:2 wp:7
[ 28.308010867/ 0x2499aadc] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc000
[ 28.308013106/ 0x2499ab06] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 7, end 0
[ 28.308015710/ 0x2499ab38] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd070 <<-- host 0x100058cc070, size 16
[ 28.308054721/ 0x2499ae26] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:2 with wr:0
[ 28.308057794/ 0x2499ae61] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cc0000
[ 28.308059721/ 0x2499ae85] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:2
[ 28.308077013/ 0x2499afd1] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.308079460/ 0x2499b000] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cc0000, size 52
[ 28.308198575/ 0x2499b8f2] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.308210190/ 0x2499b9cf] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.310215190/ 0x249a502f] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.310216960/ 0x249a5050] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x15, new-offset 0x16
[ 28.310219877/ 0x249a5088] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.310221388/ 0x249a50a5] [0x0 mhi_dev_add_element] rd_ofset 22
[ 28.310222898/ 0x249a50c2] [0x0 mhi_dev_add_element] type 34
[ 28.310224408/ 0x249a50df] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53150, size 16
[ 28.312352065/ 0x249af077] [0x0 mhi_dev_send_event] ev.rp = 9b53160 for 1
[ 28.312355606/ 0x249af0b7] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.314480658/ 0x249b9019] [0x0 mhi_dev_send_event] event sent:
[ 28.314482846/ 0x249b9041] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc020
[ 28.314484669/ 0x249b9064] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.314486179/ 0x249b9081] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.314487585/ 0x249b909c] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.314489044/ 0x249b90b8] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.314511335/ 0x249b9265] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.314514929/ 0x249b92a9] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.314517273/ 0x249b92d6] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.314519408/ 0x249b92ff] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.314520919/ 0x249b931c] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.314523054/ 0x249b9345] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.314524825/ 0x249b9367] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:3 wp:0
[ 28.314527742/ 0x249b939f] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc010
[ 28.314529981/ 0x249b93ca] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 0, end 1
[ 28.314532325/ 0x249b93f7] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd000 <<-- host 0x100058cc000, size 16
[ 28.314569513/ 0x249b96c3] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:3 with wr:1
[ 28.314573002/ 0x249b9705] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 28.314574929/ 0x249b9729] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:3
[ 28.314591960/ 0x249b9871] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.314594773/ 0x249b98a6] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cd0000, size 52
[ 28.314619460/ 0x249b9a81] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.314630815/ 0x249b9b5b] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.316726596/ 0x249c3889] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.316728263/ 0x249c38a9] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x16, new-offset 0x17
[ 28.316731231/ 0x249c38e2] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.316732742/ 0x249c38ff] [0x0 mhi_dev_add_element] rd_ofset 23
[ 28.316734252/ 0x249c391c] [0x0 mhi_dev_add_element] type 34
[ 28.316735919/ 0x249c393c] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53160, size 16
[ 28.318862950/ 0x249cd8c5] [0x0 mhi_dev_send_event] ev.rp = 9b53170 for 1
[ 28.318866492/ 0x249cd908] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.320995033/ 0x249d78ad] [0x0 mhi_dev_send_event] event sent:
[ 28.320997481/ 0x249d78da] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc030
[ 28.320999252/ 0x249d78fc] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.321000815/ 0x249d791a] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.321002221/ 0x249d7935] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.321003679/ 0x249d7951] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.321023471/ 0x249d7acf] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.321027117/ 0x249d7b13] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.321029356/ 0x249d7b3e] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.321031388/ 0x249d7b65] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.321032846/ 0x249d7b81] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.321035033/ 0x249d7bab] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.321036648/ 0x249d7bca] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:4 wp:1
[ 28.321039565/ 0x249d7c03] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc020
[ 28.321041804/ 0x249d7c2d] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 1, end 2
[ 28.321044148/ 0x249d7c5a] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd010 <<-- host 0x100058cc010, size 16
[ 28.321082533/ 0x249d7f3c] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:4 with wr:2
[ 28.321085606/ 0x249d7f77] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ce0000
[ 28.321087533/ 0x249d7f9b] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:4
[ 28.321105763/ 0x249d80f9] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.321108627/ 0x249d8130] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ce0000, size 52
[ 28.321180971/ 0x249d86a1] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.321193106/ 0x249d8787] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.323238992/ 0x249e20f7] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.323240711/ 0x249e2118] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x17, new-offset 0x18
[ 28.323243731/ 0x249e2152] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.323245398/ 0x249e2172] [0x0 mhi_dev_add_element] rd_ofset 24
[ 28.323246856/ 0x249e218e] [0x0 mhi_dev_add_element] type 34
[ 28.323248627/ 0x249e21b0] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53170, size 16
[ 28.325375294/ 0x249ec132] [0x0 mhi_dev_send_event] ev.rp = 9b53180 for 1
[ 28.325378419/ 0x249ec16d] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.327504461/ 0x249f60e2] [0x0 mhi_dev_send_event] event sent:
[ 28.327506961/ 0x249f6110] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc040
[ 28.327508731/ 0x249f6133] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.327510294/ 0x249f6150] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.327511700/ 0x249f616b] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.327513158/ 0x249f6187] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.327536648/ 0x249f634b] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.327540086/ 0x249f638d] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.327542429/ 0x249f63b9] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.327544461/ 0x249f63e0] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.327545971/ 0x249f63fd] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.327548106/ 0x249f6427] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.327549773/ 0x249f6446] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:5 wp:2
[ 28.327552690/ 0x249f647e] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc030
[ 28.327554929/ 0x249f64a9] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 2, end 3
[ 28.327557169/ 0x249f64d4] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd020 <<-- host 0x100058cc020, size 16
[ 28.327597429/ 0x249f67d9] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:5 with wr:3
[ 28.327600554/ 0x249f6815] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 28.327602429/ 0x249f6839] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:5
[ 28.327620711/ 0x249f6999] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.327623367/ 0x249f69cb] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c80000, size 52
[ 28.327677481/ 0x249f6ddb] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.327689461/ 0x249f6ec1] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.329754304/ 0x24a0099e] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.329756075/ 0x24a009bf] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x18, new-offset 0x19
[ 28.329758992/ 0x24a009f7] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.329760502/ 0x24a00a14] [0x0 mhi_dev_add_element] rd_ofset 25
[ 28.329762013/ 0x24a00a31] [0x0 mhi_dev_add_element] type 34
[ 28.329763523/ 0x24a00a4e] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53180, size 16
[ 28.331893523/ 0x24a0aa10] [0x0 mhi_dev_send_event] ev.rp = 9b53190 for 1
[ 28.331896804/ 0x24a0aa4d] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.334021752/ 0x24a149ae] [0x0 mhi_dev_send_event] event sent:
[ 28.334023992/ 0x24a149d7] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc050
[ 28.334025763/ 0x24a149f9] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.334027273/ 0x24a14a16] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.334028836/ 0x24a14a34] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.334030242/ 0x24a14a4f] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.334049669/ 0x24a14bc4] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.334053211/ 0x24a14c09] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.334055658/ 0x24a14c37] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.334057690/ 0x24a14c5e] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.334059304/ 0x24a14c7d] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.334061440/ 0x24a14ca7] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.334063054/ 0x24a14cc6] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:6 wp:3
[ 28.334066127/ 0x24a14d01] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc040
[ 28.334068419/ 0x24a14d2c] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 3, end 4
[ 28.334070919/ 0x24a14d5c] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd030 <<-- host 0x100058cc030, size 16
[ 28.334109825/ 0x24a15048] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:6 with wr:4
[ 28.334113367/ 0x24a1508b] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 28.334115294/ 0x24a150af] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:6
[ 28.334134252/ 0x24a1521c] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.334136908/ 0x24a1524f] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c90000, size 52
[ 28.334162325/ 0x24a15439] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.334174669/ 0x24a15525] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.336267117/ 0x24a1f213] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.336268836/ 0x24a1f234] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x19, new-offset 0x1a
[ 28.336271752/ 0x24a1f26c] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.336273315/ 0x24a1f28a] [0x0 mhi_dev_add_element] rd_ofset 26
[ 28.336274929/ 0x24a1f2a9] [0x0 mhi_dev_add_element] type 34
[ 28.336276440/ 0x24a1f2c6] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53190, size 16
[ 28.338403263/ 0x24a2924b] [0x0 mhi_dev_send_event] ev.rp = 9b531a0 for 1
[ 28.338406700/ 0x24a2928b] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.340535450/ 0x24a33237] [0x0 mhi_dev_send_event] event sent:
[ 28.340537846/ 0x24a33261] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc060
[ 28.340539617/ 0x24a33283] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.340541179/ 0x24a332a1] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.340542586/ 0x24a332bc] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.340544044/ 0x24a332d8] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.340567013/ 0x24a33492] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.340570658/ 0x24a334d7] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.340573002/ 0x24a33504] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.340574877/ 0x24a33528] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.340576388/ 0x24a33544] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.340578523/ 0x24a3356e] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.340580294/ 0x24a33590] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:4
[ 28.340583158/ 0x24a335c7] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc050
[ 28.340585398/ 0x24a335f2] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 4, end 5
[ 28.340587846/ 0x24a33621] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd040 <<-- host 0x100058cc040, size 16
[ 28.340624669/ 0x24a338e5] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:5
[ 28.340627898/ 0x24a33922] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ca0000
[ 28.340629825/ 0x24a33947] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 28.340648106/ 0x24a33aa6] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.340650554/ 0x24a33ad6] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ca0000, size 52
[ 28.340670815/ 0x24a33c5a] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.340681179/ 0x24a33d22] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.342778367/ 0x24a3da6b] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.342780086/ 0x24a3da8b] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x1a, new-offset 0x1b
[ 28.342782950/ 0x24a3dac4] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.342784513/ 0x24a3dae1] [0x0 mhi_dev_add_element] rd_ofset 27
[ 28.342786023/ 0x24a3dafe] [0x0 mhi_dev_add_element] type 34
[ 28.342787533/ 0x24a3db1b] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b531a0, size 16
[ 28.344911752/ 0x24a47a6e] [0x0 mhi_dev_send_event] ev.rp = 9b531b0 for 1
[ 28.344914877/ 0x24a47aa9] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.347038106/ 0x24a519e7] [0x0 mhi_dev_send_event] event sent:
[ 28.347040190/ 0x24a51a0e] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc070
[ 28.347042221/ 0x24a51a35] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.347043784/ 0x24a51a53] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.347045190/ 0x24a51a70] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.347046752/ 0x24a51a8c] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.347065971/ 0x24a51bfe] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.347069565/ 0x24a51c42] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.347071804/ 0x24a51c6d] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.347073836/ 0x24a51c94] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.347075294/ 0x24a51cb0] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.347077481/ 0x24a51cda] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.347079096/ 0x24a51cf9] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:0 wp:5
[ 28.347082273/ 0x24a51d36] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc060
[ 28.347084513/ 0x24a51d61] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 5, end 6
[ 28.347086856/ 0x24a51d8e] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd050 <<-- host 0x100058cc050, size 16
[ 28.347123940/ 0x24a52056] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:0 with wr:6
[ 28.347127221/ 0x24a52096] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 28.347129148/ 0x24a520ba] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:0
[ 28.347146961/ 0x24a52211] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.347149721/ 0x24a52245] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cb0000, size 52
[ 28.347156075/ 0x24a522bf] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.347164981/ 0x24a5236a] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.349319565/ 0x24a5c502] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.349321440/ 0x24a5c526] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x1b, new-offset 0x1c
[ 28.349324356/ 0x24a5c55e] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.349325919/ 0x24a5c57c] [0x0 mhi_dev_add_element] rd_ofset 28
[ 28.349327377/ 0x24a5c598] [0x0 mhi_dev_add_element] type 34
[ 28.349328940/ 0x24a5c5b6] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b531b0, size 16
[ 28.351518054/ 0x24a669e6] [0x0 mhi_dev_send_event] ev.rp = 9b531c0 for 1
[ 28.351524252/ 0x24a66a5e] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.353655815/ 0x24a70a3f] [0x0 mhi_dev_send_event] event sent:
[ 28.353659513/ 0x24a70a81] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc000
[ 28.353661909/ 0x24a70aaf] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.353663679/ 0x24a70ad1] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.353665242/ 0x24a70aee] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.353666909/ 0x24a70b0f] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.353696804/ 0x24a70d4f] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.353700815/ 0x24a70d9a] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.353703419/ 0x24a70dcc] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.353705554/ 0x24a70df5] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.353707169/ 0x24a70e14] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.353709565/ 0x24a70e42] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.353711179/ 0x24a70e62] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:6
[ 28.353714252/ 0x24a70e9c] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc070
[ 28.353716648/ 0x24a70eca] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 6, end 7
[ 28.353719096/ 0x24a70ef9] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd060 <<-- host 0x100058cc060, size 16
[ 28.353764721/ 0x24a71267] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:7
[ 28.353768679/ 0x24a712b1] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cc0000
[ 28.353770763/ 0x24a712d9] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 28.353778731/ 0x24a71373] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.353789252/ 0x24a7143d] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.353797273/ 0x24a714d6] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.353800502/ 0x24a71514] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.353802898/ 0x24a71542] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.353804877/ 0x24a71568] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.353806336/ 0x24a71584] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.353808471/ 0x24a715ad] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.353810034/ 0x24a715cc] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:7
[ 28.353812950/ 0x24a71603] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc000
[ 28.353815294/ 0x24a71630] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 7, end 0
[ 28.353817638/ 0x24a7165e] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd070 <<-- host 0x100058cc070, size 16
[ 28.353852742/ 0x24a718ff] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.353855867/ 0x24a7193b] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cc0000, size 52
[ 28.354900190/ 0x24a76790] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:0
[ 28.354904148/ 0x24a767db] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cc0000
[ 28.354906127/ 0x24a76800] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 28.356001179/ 0x24a7ba22] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.356003263/ 0x24a7ba49] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x1c, new-offset 0x1d
[ 28.356006440/ 0x24a7ba86] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.356008471/ 0x24a7baad] [0x0 mhi_dev_add_element] rd_ofset 29
[ 28.356010242/ 0x24a7bace] [0x0 mhi_dev_add_element] type 34
[ 28.356011961/ 0x24a7baf0] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b531c0, size 16
[ 28.358139565/ 0x24a85a84] [0x0 mhi_dev_send_event] ev.rp = 9b531d0 for 1
[ 28.358143159/ 0x24a85ac8] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.360272898/ 0x24a8fa85] [0x0 mhi_dev_send_event] event sent:
[ 28.360275606/ 0x24a8fab6] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc010
[ 28.360277481/ 0x24a8fadb] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.360279148/ 0x24a8fafa] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.360280763/ 0x24a8fb19] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.360282221/ 0x24a8fb34] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.360318992/ 0x24a8fdf7] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.360321440/ 0x24a8fe26] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cd0000, size 52
[ 28.360448211/ 0x24a907aa] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.360461388/ 0x24a908a8] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.362478992/ 0x24a99ff7] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.362480659/ 0x24a9a017] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x1d, new-offset 0x1e
[ 28.362483575/ 0x24a9a04f] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.362485242/ 0x24a9a06f] [0x0 mhi_dev_add_element] rd_ofset 30
[ 28.362486856/ 0x24a9a08e] [0x0 mhi_dev_add_element] type 34
[ 28.362488367/ 0x24a9a0ab] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b531d0, size 16
[ 28.364615606/ 0x24aa4038] [0x0 mhi_dev_send_event] ev.rp = 9b531e0 for 1
[ 28.364618940/ 0x24aa4077] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.366744669/ 0x24aadfe6] [0x0 mhi_dev_send_event] event sent:
[ 28.366746856/ 0x24aae00e] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc020
[ 28.366748627/ 0x24aae030] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.366750294/ 0x24aae050] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.366751804/ 0x24aae06d] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.366753367/ 0x24aae08b] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.366776596/ 0x24aae24a] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.366780398/ 0x24aae292] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.366782638/ 0x24aae2bd] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.366784773/ 0x24aae2e6] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.366786284/ 0x24aae303] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.366788575/ 0x24aae32f] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.366790190/ 0x24aae34e] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:3 wp:0
[ 28.366793106/ 0x24aae386] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc010
[ 28.366795346/ 0x24aae3b1] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 0, end 1
[ 28.366797846/ 0x24aae3e1] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd000 <<-- host 0x100058cc000, size 16
[ 28.366840711/ 0x24aae71c] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:3 with wr:1
[ 28.366844200/ 0x24aae75c] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ce0000
[ 28.366846127/ 0x24aae780] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:3
[ 28.366853471/ 0x24aae80e] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.366863002/ 0x24aae8c4] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.366870763/ 0x24aae95a] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.366874044/ 0x24aae998] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.366876336/ 0x24aae9c4] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.366878263/ 0x24aae9e9] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.366879721/ 0x24aaea05] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.366881856/ 0x24aaea2e] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.366883575/ 0x24aaea4f] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:3 wp:1
[ 28.366886440/ 0x24aaea86] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc020
[ 28.366888784/ 0x24aaeab3] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 1, end 2
[ 28.366891023/ 0x24aaeade] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd010 <<-- host 0x100058cc010, size 16
[ 28.366911700/ 0x24aaec6c] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.366914252/ 0x24aaec9c] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ce0000, size 52
[ 28.367906231/ 0x24ab3704] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:3 with wr:2
[ 28.367910034/ 0x24ab374e] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ce0000
[ 28.367912169/ 0x24ab3774] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:3
[ 28.369070554/ 0x24ab8e55] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.369072638/ 0x24ab8e7d] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x1e, new-offset 0x1f
[ 28.369075711/ 0x24ab8eb8] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.369077221/ 0x24ab8ed5] [0x0 mhi_dev_add_element] rd_ofset 31
[ 28.369078784/ 0x24ab8ef3] [0x0 mhi_dev_add_element] type 34
[ 28.369080242/ 0x24ab8f0f] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b531e0, size 16
[ 28.371211440/ 0x24ac2ee8] [0x0 mhi_dev_send_event] ev.rp = 9b531f0 for 1
[ 28.371215086/ 0x24ac2f2d] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.373340346/ 0x24acce92] [0x0 mhi_dev_send_event] event sent:
[ 28.373342534/ 0x24accebb] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc030
[ 28.373344304/ 0x24accedd] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.373345815/ 0x24accefa] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.373347221/ 0x24accf15] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.373348627/ 0x24accf30] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.373381336/ 0x24acd1a4] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.373383836/ 0x24acd1d4] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c80000, size 52
[ 28.373433784/ 0x24acd594] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.373446232/ 0x24acd683] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.375538679/ 0x24ad7371] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.375540502/ 0x24ad7393] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x1f, new-offset 0x20
[ 28.375543367/ 0x24ad73cb] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.375545034/ 0x24ad73eb] [0x0 mhi_dev_add_element] rd_ofset 32
[ 28.375546544/ 0x24ad7408] [0x0 mhi_dev_add_element] type 34
[ 28.375548054/ 0x24ad7425] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b531f0, size 16
[ 28.377673836/ 0x24ae1396] [0x0 mhi_dev_send_event] ev.rp = 9b53200 for 1
[ 28.377677117/ 0x24ae13d4] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.379802221/ 0x24aeb337] [0x0 mhi_dev_send_event] event sent:
[ 28.379804357/ 0x24aeb35f] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc040
[ 28.379806284/ 0x24aeb383] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.379807950/ 0x24aeb3a3] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.379809357/ 0x24aeb3be] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.379810971/ 0x24aeb3dd] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.379834096/ 0x24aeb59a] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.379838002/ 0x24aeb5e5] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.379840398/ 0x24aeb612] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.379842429/ 0x24aeb638] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.379843888/ 0x24aeb655] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.379846023/ 0x24aeb67e] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.379847638/ 0x24aeb69d] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:5 wp:2
[ 28.379850554/ 0x24aeb6d5] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc030
[ 28.379852794/ 0x24aeb700] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 2, end 3
[ 28.379855242/ 0x24aeb72f] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd020 <<-- host 0x100058cc020, size 16
[ 28.379895242/ 0x24aeba31] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:5 with wr:3
[ 28.379898419/ 0x24aeba6c] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 28.379900294/ 0x24aeba90] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:5
[ 28.379907377/ 0x24aebb18] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.379917117/ 0x24aebbd3] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.379925034/ 0x24aebc6e] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.379928367/ 0x24aebcac] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.379930659/ 0x24aebcd7] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.379932586/ 0x24aebcfc] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.379934044/ 0x24aebd18] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.379936179/ 0x24aebd41] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.379937742/ 0x24aebd60] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:5 wp:3
[ 28.379940659/ 0x24aebd97] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc040
[ 28.379942898/ 0x24aebdc2] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 3, end 4
[ 28.379945086/ 0x24aebdec] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd030 <<-- host 0x100058cc030, size 16
[ 28.379965607/ 0x24aebf76] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.379967950/ 0x24aebfa3] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c90000, size 52
[ 28.380964357/ 0x24af0a5f] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:5 with wr:4
[ 28.380968523/ 0x24af0aaf] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c90000
[ 28.380970554/ 0x24af0ad5] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:5
[ 28.382123732/ 0x24af6152] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.382125607/ 0x24af6175] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x20, new-offset 0x21
[ 28.382128627/ 0x24af61b0] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.382130190/ 0x24af61ce] [0x0 mhi_dev_add_element] rd_ofset 33
[ 28.382131700/ 0x24af61eb] [0x0 mhi_dev_add_element] type 34
[ 28.382133367/ 0x24af620b] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53200, size 16
[ 28.384260242/ 0x24b00193] [0x0 mhi_dev_send_event] ev.rp = 9b53210 for 1
[ 28.384263732/ 0x24b001d3] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.386388679/ 0x24b0a133] [0x0 mhi_dev_send_event] event sent:
[ 28.386390919/ 0x24b0a15d] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc050
[ 28.386392742/ 0x24b0a17f] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.386394252/ 0x24b0a19c] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.386395971/ 0x24b0a1bd] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.386397534/ 0x24b0a1db] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.386429357/ 0x24b0a43e] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.386431909/ 0x24b0a46f] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ca0000, size 52
[ 28.386498419/ 0x24b0a96f] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.386510086/ 0x24b0aa4d] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.388587273/ 0x24b14617] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.388589044/ 0x24b14637] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x21, new-offset 0x22
[ 28.388591909/ 0x24b1466f] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.388593471/ 0x24b1468d] [0x0 mhi_dev_add_element] rd_ofset 34
[ 28.388595086/ 0x24b146ac] [0x0 mhi_dev_add_element] type 34
[ 28.388596596/ 0x24b146c9] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53210, size 16
[ 28.390725867/ 0x24b1e67f] [0x0 mhi_dev_send_event] ev.rp = 9b53220 for 1
[ 28.390729721/ 0x24b1e6c6] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.392855294/ 0x24b28632] [0x0 mhi_dev_send_event] event sent:
[ 28.392857534/ 0x24b2865b] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc060
[ 28.392859304/ 0x24b2867d] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.392860867/ 0x24b2869b] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.392862534/ 0x24b286bb] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.392864096/ 0x24b286d9] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.392886648/ 0x24b2888b] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.392890034/ 0x24b288cb] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.392892325/ 0x24b288f7] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.392894357/ 0x24b2891e] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.392895971/ 0x24b2893d] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.392898107/ 0x24b28966] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.392899721/ 0x24b28985] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:4
[ 28.392902794/ 0x24b289c0] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc050
[ 28.392905034/ 0x24b289ea] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 4, end 5
[ 28.392907221/ 0x24b28a15] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd040 <<-- host 0x100058cc040, size 16
[ 28.392946752/ 0x24b28d0d] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:5
[ 28.392950450/ 0x24b28d53] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 28.392952325/ 0x24b28d77] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 28.392970450/ 0x24b28ed3] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.392973002/ 0x24b28f04] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cb0000, size 52
[ 28.393018575/ 0x24b29271] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.393030346/ 0x24b29353] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.395104044/ 0x24b32ed8] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.395105763/ 0x24b32ef9] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x22, new-offset 0x23
[ 28.395108836/ 0x24b32f34] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.395110502/ 0x24b32f54] [0x0 mhi_dev_add_element] rd_ofset 35
[ 28.395112117/ 0x24b32f73] [0x0 mhi_dev_add_element] type 34
[ 28.395113679/ 0x24b32f91] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53220, size 16
[ 28.397240659/ 0x24b3cf19] [0x0 mhi_dev_send_event] ev.rp = 9b53230 for 1
[ 28.397244044/ 0x24b3cf59] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.399369461/ 0x24b46ec2] [0x0 mhi_dev_send_event] event sent:
[ 28.399371752/ 0x24b46eed] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc070
[ 28.399373575/ 0x24b46f0f] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.399375138/ 0x24b46f2d] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.399376544/ 0x24b46f48] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.399378002/ 0x24b46f64] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.399398159/ 0x24b470e9] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.399401804/ 0x24b4712d] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.399404044/ 0x24b47158] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.399405919/ 0x24b4717c] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.399407534/ 0x24b4719b] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.399409669/ 0x24b471c5] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.399411284/ 0x24b471e4] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:0 wp:5
[ 28.399414200/ 0x24b4721c] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc060
[ 28.399416492/ 0x24b47247] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 5, end 6
[ 28.399418836/ 0x24b47274] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd050 <<-- host 0x100058cc050, size 16
[ 28.399456752/ 0x24b4754d] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:0 with wr:6
[ 28.399460294/ 0x24b47590] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cc0000
[ 28.399462221/ 0x24b475b5] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:0
[ 28.399479252/ 0x24b476fc] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.399481909/ 0x24b4772f] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cc0000, size 52
[ 28.399521544/ 0x24b47a2a] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.399533419/ 0x24b47b0e] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.401620190/ 0x24b5178e] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.401622169/ 0x24b517b4] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x23, new-offset 0x24
[ 28.401625086/ 0x24b517ec] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.401626596/ 0x24b51809] [0x0 mhi_dev_add_element] rd_ofset 36
[ 28.401628159/ 0x24b51827] [0x0 mhi_dev_add_element] type 34
[ 28.401629669/ 0x24b51844] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53230, size 16
[ 28.405151492/ 0x24b62070] [0x0 mhi_dev_send_event] ev.rp = 9b53240 for 1
[ 28.405157377/ 0x24b620d8] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.406255607/ 0x24b6733a] [0x0 mhi_dev_send_event] event sent:
[ 28.406259252/ 0x24b6737c] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc000
[ 28.406261336/ 0x24b673a4] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.406263263/ 0x24b673c8] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.406264877/ 0x24b673e8] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.406266492/ 0x24b67407] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.406307482/ 0x24b6771b] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.406311909/ 0x24b67770] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.406315242/ 0x24b677af] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.406317534/ 0x24b677db] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.406319461/ 0x24b67800] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.406322430/ 0x24b6783a] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.406324669/ 0x24b67864] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:6
[ 28.406328159/ 0x24b678a7] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc070
[ 28.406330763/ 0x24b678d9] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 6, end 7
[ 28.406333888/ 0x24b67915] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd060 <<-- host 0x100058cc060, size 16
[ 28.406401909/ 0x24b67e32] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:7
[ 28.406405607/ 0x24b67e77] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 28.406408002/ 0x24b67ea4] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 28.406436909/ 0x24b680d0] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.406448159/ 0x24b681a8] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.406456544/ 0x24b6824e] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.406459982/ 0x24b6828a] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.406462221/ 0x24b682b5] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.406464252/ 0x24b682dc] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.406465815/ 0x24b682fa] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.406468211/ 0x24b68328] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.406469930/ 0x24b6834a] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:7
[ 28.406472846/ 0x24b68382] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc000
[ 28.406475346/ 0x24b683b1] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 7, end 0
[ 28.406477950/ 0x24b683e3] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd070 <<-- host 0x100058cc070, size 16
[ 28.406516648/ 0x24b686ca] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.406520346/ 0x24b68711] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cd0000, size 52
[ 28.407472273/ 0x24b6ce78] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:0
[ 28.407476232/ 0x24b6cec3] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cd0000
[ 28.407478315/ 0x24b6ceea] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 28.408683055/ 0x24b72945] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.408685502/ 0x24b72973] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x24, new-offset 0x25
[ 28.408689148/ 0x24b729ba] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.408691127/ 0x24b729e0] [0x0 mhi_dev_add_element] rd_ofset 37
[ 28.408692794/ 0x24b72a00] [0x0 mhi_dev_add_element] type 34
[ 28.408694617/ 0x24b72a23] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53240, size 16
[ 28.410823471/ 0x24b7c9cf] [0x0 mhi_dev_send_event] ev.rp = 9b53250 for 1
[ 28.410827690/ 0x24b7ca1e] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.412953159/ 0x24b86989] [0x0 mhi_dev_send_event] event sent:
[ 28.412955659/ 0x24b869b8] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc010
[ 28.412957482/ 0x24b869da] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.412959096/ 0x24b869f9] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.412960502/ 0x24b86a14] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.412962169/ 0x24b86a34] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.413005450/ 0x24b86d73] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.413008732/ 0x24b86db2] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ce0000, size 52
[ 28.413105138/ 0x24b874f0] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.413119044/ 0x24b875fc] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.415164513/ 0x24b90f61] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.415166492/ 0x24b90f86] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x25, new-offset 0x26
[ 28.415169565/ 0x24b90fc2] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.415171127/ 0x24b90fe0] [0x0 mhi_dev_add_element] rd_ofset 38
[ 28.415172638/ 0x24b90ffd] [0x0 mhi_dev_add_element] type 34
[ 28.415174148/ 0x24b9101a] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53250, size 16
[ 28.417298471/ 0x24b9af6f] [0x0 mhi_dev_send_event] ev.rp = 9b53260 for 1
[ 28.417301492/ 0x24b9afa8] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.419423523/ 0x24ba4ed0] [0x0 mhi_dev_send_event] event sent:
[ 28.419426023/ 0x24ba4eff] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc020
[ 28.419427794/ 0x24ba4f20] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.419429357/ 0x24ba4f3d] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.419430867/ 0x24ba4f5b] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.419432325/ 0x24ba4f77] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.419458575/ 0x24ba5170] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.419462742/ 0x24ba51bf] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.419465086/ 0x24ba51ec] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.419467117/ 0x24ba5213] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.419468732/ 0x24ba5232] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.419470971/ 0x24ba525d] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.419472742/ 0x24ba527f] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:3 wp:0
[ 28.419475763/ 0x24ba52ba] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc010
[ 28.419478159/ 0x24ba52e7] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 0, end 1
[ 28.419481075/ 0x24ba531f] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd000 <<-- host 0x100058cc000, size 16
[ 28.419523419/ 0x24ba564e] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:3 with wr:1
[ 28.419526596/ 0x24ba568a] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 28.419528680/ 0x24ba56b1] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:3
[ 28.419538940/ 0x24ba5776] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.419552325/ 0x24ba5878] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.419560867/ 0x24ba591c] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.419564252/ 0x24ba595c] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.419566648/ 0x24ba598a] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.419568680/ 0x24ba59b1] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.419570138/ 0x24ba59cc] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.419572377/ 0x24ba59f8] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.419573992/ 0x24ba5a17] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:3 wp:1
[ 28.419576857/ 0x24ba5a4e] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc020
[ 28.419579252/ 0x24ba5a7c] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 1, end 2
[ 28.419581596/ 0x24ba5aa9] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd010 <<-- host 0x100058cc010, size 16
[ 28.419605711/ 0x24ba5c79] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.419608471/ 0x24ba5cad] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c80000, size 52
[ 28.420613888/ 0x24baa817] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:3 with wr:2
[ 28.420618002/ 0x24baa864] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 28.420619982/ 0x24baa88a] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:3
[ 28.421764773/ 0x24bafe66] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.421766648/ 0x24bafe89] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x26, new-offset 0x27
[ 28.421769773/ 0x24bafec6] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.421771440/ 0x24bafee6] [0x0 mhi_dev_add_element] rd_ofset 39
[ 28.421773002/ 0x24baff04] [0x0 mhi_dev_add_element] type 34
[ 28.421774461/ 0x24baff20] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53260, size 16
[ 28.423899825/ 0x24bb9e88] [0x0 mhi_dev_send_event] ev.rp = 9b53270 for 1
[ 28.423903002/ 0x24bb9ec5] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.426026232/ 0x24bc3e03] [0x0 mhi_dev_send_event] event sent:
[ 28.426028471/ 0x24bc3e2e] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc030
[ 28.426030346/ 0x24bc3e51] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.426031857/ 0x24bc3e6d] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.426033471/ 0x24bc3e8d] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.426034930/ 0x24bc3ea9] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.426070086/ 0x24bc414c] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.426072482/ 0x24bc417a] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006c90000, size 52
[ 28.426146961/ 0x24bc4713] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.426158888/ 0x24bc47f6] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.428224825/ 0x24bce2e7] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.428226492/ 0x24bce307] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x27, new-offset 0x28
[ 28.428229409/ 0x24bce33f] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.428230919/ 0x24bce35c] [0x0 mhi_dev_add_element] rd_ofset 40
[ 28.428232430/ 0x24bce379] [0x0 mhi_dev_add_element] type 34
[ 28.428233992/ 0x24bce397] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53270, size 16
[ 28.430363263/ 0x24bd834c] [0x0 mhi_dev_send_event] ev.rp = 9b53280 for 1
[ 28.430367742/ 0x24bd839f] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.432497898/ 0x24be2365] [0x0 mhi_dev_send_event] event sent:
[ 28.432500711/ 0x24be2398] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc040
[ 28.432502638/ 0x24be23bd] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.432504409/ 0x24be23df] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.432505919/ 0x24be23fc] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.432507482/ 0x24be241a] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.432533471/ 0x24be2610] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.432537690/ 0x24be265e] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.432539982/ 0x24be268a] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.432542117/ 0x24be26b3] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.432543575/ 0x24be26cf] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.432545867/ 0x24be26fb] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.432547586/ 0x24be271c] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:5 wp:2
[ 28.432550659/ 0x24be2757] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc030
[ 28.432552846/ 0x24be2781] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 2, end 3
[ 28.432555555/ 0x24be27b5] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd020 <<-- host 0x100058cc020, size 16
[ 28.432596596/ 0x24be2aca] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:5 with wr:3
[ 28.432599721/ 0x24be2b05] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ca0000
[ 28.432601753/ 0x24be2b2c] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:5
[ 28.432629878/ 0x24be2d48] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.432632638/ 0x24be2d7d] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ca0000, size 52
[ 28.432672430/ 0x24be307b] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.432684878/ 0x24be3169] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.434773107/ 0x24bece06] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.434774982/ 0x24bece29] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x28, new-offset 0x29
[ 28.434777846/ 0x24bece61] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.434779409/ 0x24bece7f] [0x0 mhi_dev_add_element] rd_ofset 41
[ 28.434780919/ 0x24bece9b] [0x0 mhi_dev_add_element] type 34
[ 28.434782430/ 0x24beceb9] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53280, size 16
[ 28.436908888/ 0x24bf6e3a] [0x0 mhi_dev_send_event] ev.rp = 9b53290 for 1
[ 28.436912950/ 0x24bf6e83] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.439039253/ 0x24c00dfe] [0x0 mhi_dev_send_event] event sent:
[ 28.439041596/ 0x24c00e29] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc050
[ 28.439043471/ 0x24c00e4d] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.439045138/ 0x24c00e6d] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.439046544/ 0x24c00e88] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.439048107/ 0x24c00ea6] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.439068680/ 0x24c01032] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.439072534/ 0x24c0107b] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.439074878/ 0x24c010a8] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.439076753/ 0x24c010cc] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.439078263/ 0x24c010e9] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.439080503/ 0x24c01115] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.439082117/ 0x24c01133] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:6 wp:3
[ 28.439085086/ 0x24c0116c] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc040
[ 28.439087325/ 0x24c01197] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 3, end 4
[ 28.439089773/ 0x24c011c6] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd030 <<-- host 0x100058cc030, size 16
[ 28.439127898/ 0x24c014a3] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:6 with wr:4
[ 28.439131075/ 0x24c014df] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cb0000
[ 28.439132950/ 0x24c01503] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:6
[ 28.439154409/ 0x24c0169f] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.439156961/ 0x24c016d0] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cb0000, size 52
[ 28.439334461/ 0x24c02422] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.439346805/ 0x24c0250e] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.441291284/ 0x24c0b6e3] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.441293263/ 0x24c0b708] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x29, new-offset 0x2a
[ 28.441296180/ 0x24c0b741] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.441297742/ 0x24c0b75f] [0x0 mhi_dev_add_element] rd_ofset 42
[ 28.441299200/ 0x24c0b77b] [0x0 mhi_dev_add_element] type 34
[ 28.441300711/ 0x24c0b798] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b53290, size 16
[ 28.443427898/ 0x24c15724] [0x0 mhi_dev_send_event] ev.rp = 9b532a0 for 1
[ 28.443431284/ 0x24c15763] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.445557325/ 0x24c1f6d9] [0x0 mhi_dev_send_event] event sent:
[ 28.445559513/ 0x24c1f701] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc060
[ 28.445561388/ 0x24c1f725] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.445562898/ 0x24c1f742] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.445564305/ 0x24c1f75d] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.445565867/ 0x24c1f77b] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.445589930/ 0x24c1f94a] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.445593628/ 0x24c1f990] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.445595971/ 0x24c1f9be] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.445598159/ 0x24c1f9e6] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.445599617/ 0x24c1fa03] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.445601805/ 0x24c1fa2d] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.445603419/ 0x24c1fa4c] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:4
[ 28.445606596/ 0x24c1fa89] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc050
[ 28.445608836/ 0x24c1fab4] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 4, end 5
[ 28.445611388/ 0x24c1fae5] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd040 <<-- host 0x100058cc040, size 16
[ 28.445650242/ 0x24c1fdd0] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:5
[ 28.445653315/ 0x24c1fe0a] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cc0000
[ 28.445655190/ 0x24c1fe2e] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 28.445667221/ 0x24c1ff15] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.445675867/ 0x24c1ffbb] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.445683419/ 0x24c2004d] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.445686700/ 0x24c2008b] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.445689096/ 0x24c200b9] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.445690971/ 0x24c200dd] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.445692430/ 0x24c200f9] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.445694565/ 0x24c20123] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.445696180/ 0x24c20141] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:7 wp:5
[ 28.445699044/ 0x24c20179] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc060
[ 28.445701284/ 0x24c201a3] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 5, end 6
[ 28.445703471/ 0x24c201ce] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd050 <<-- host 0x100058cc050, size 16
[ 28.445724200/ 0x24c2035c] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.445726753/ 0x24c2038c] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cc0000, size 52
[ 28.446715919/ 0x24c24dbe] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:7 with wr:6
[ 28.446719721/ 0x24c24e06] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6cc0000
[ 28.446721753/ 0x24c24e2c] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:7
[ 28.447883211/ 0x24c2a548] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.447884930/ 0x24c2a569] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x2a, new-offset 0x2b
[ 28.447887846/ 0x24c2a5a1] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.447889357/ 0x24c2a5be] [0x0 mhi_dev_add_element] rd_ofset 43
[ 28.447890867/ 0x24c2a5db] [0x0 mhi_dev_add_element] type 34
[ 28.447892378/ 0x24c2a5f8] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b532a0, size 16
[ 28.450033159/ 0x24c34689] [0x0 mhi_dev_send_event] ev.rp = 9b532b0 for 1
[ 28.450037221/ 0x24c346d6] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.452162117/ 0x24c3e635] [0x0 mhi_dev_send_event] event sent:
[ 28.452164617/ 0x24c3e663] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc070
[ 28.452166544/ 0x24c3e688] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.452168055/ 0x24c3e6a5] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.452169461/ 0x24c3e6c0] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.452170919/ 0x24c3e6db] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.452203003/ 0x24c3e944] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.452205450/ 0x24c3e973] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006cd0000, size 52
[ 28.452265450/ 0x24c3edf5] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.452277117/ 0x24c3eed4] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.454359825/ 0x24c48b08] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.454361596/ 0x24c48b28] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x2b, new-offset 0x2c
[ 28.454364617/ 0x24c48b63] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.454366180/ 0x24c48b81] [0x0 mhi_dev_add_element] rd_ofset 44
[ 28.454367690/ 0x24c48b9e] [0x0 mhi_dev_add_element] type 34
[ 28.454369357/ 0x24c48bbe] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b532b0, size 16
[ 28.456493836/ 0x24c52b16] [0x0 mhi_dev_send_event] ev.rp = 9b532c0 for 1
[ 28.456496909/ 0x24c52b50] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.458620034/ 0x24c5ca8d] [0x0 mhi_dev_send_event] event sent:
[ 28.458622430/ 0x24c5cab9] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc000
[ 28.458624253/ 0x24c5cadc] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.458625763/ 0x24c5caf9] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.458627169/ 0x24c5cb14] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.458628628/ 0x24c5cb30] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.458651180/ 0x24c5cce2] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.458654982/ 0x24c5cd2a] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.458657273/ 0x24c5cd56] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.458659148/ 0x24c5cd79] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.458660711/ 0x24c5cd98] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.458663003/ 0x24c5cdc4] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.458664617/ 0x24c5cde3] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:6
[ 28.458667534/ 0x24c5ce1c] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc070
[ 28.458669773/ 0x24c5ce46] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 6, end 7
[ 28.458672117/ 0x24c5ce73] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd060 <<-- host 0x100058cc060, size 16
[ 28.458711648/ 0x24c5d16c] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:7
[ 28.458714982/ 0x24c5d1ab] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ce0000
[ 28.458716909/ 0x24c5d1cf] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 28.458723732/ 0x24c5d252] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.458733419/ 0x24c5d30c] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.458741701/ 0x24c5d3ad] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.458745138/ 0x24c5d3ed] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.458747482/ 0x24c5d41a] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.458749409/ 0x24c5d43e] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.458750815/ 0x24c5d45a] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.458753003/ 0x24c5d484] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.458754565/ 0x24c5d4a2] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:1 wp:7
[ 28.458757430/ 0x24c5d4d9] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc000
[ 28.458759669/ 0x24c5d504] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 7, end 0
[ 28.458762013/ 0x24c5d531] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd070 <<-- host 0x100058cc070, size 16
[ 28.458788628/ 0x24c5d731] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 28.458791180/ 0x24c5d761] [0x0 mhi_transfer_device_to_host_ipa] device 0x8ba00000 ---> host 0x10006ce0000, size 52
[ 28.459839148/ 0x24c625fc] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:1 with wr:0
[ 28.459842951/ 0x24c62643] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6ce0000
[ 28.459844930/ 0x24c62669] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:1
[ 28.460950815/ 0x24c6795a] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 28.460952638/ 0x24c6797d] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x2c, new-offset 0x2d
[ 28.460955711/ 0x24c679b8] [0x0 mhi_dev_add_element] adding element to ring_id:1
[ 28.460957378/ 0x24c679d8] [0x0 mhi_dev_add_element] rd_ofset 45
[ 28.460959044/ 0x24c679f8] [0x0 mhi_dev_add_element] type 34
[ 28.460960659/ 0x24c67a17] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b532c0, size 16
[ 28.463092065/ 0x24c719f5] [0x0 mhi_dev_send_event] ev.rp = 9b532d0 for 1
[ 28.463097482/ 0x24c71a5b] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 28.465225919/ 0x24c7ba01] [0x0 mhi_dev_send_event] event sent:
[ 28.465228471/ 0x24c7ba2e] [0x0 mhi_dev_send_event] evnt ptr : 0x58cc010
[ 28.465230555/ 0x24c7ba55] [0x0 mhi_dev_send_event] evnt len : 0x34
[ 28.465232065/ 0x24c7ba72] [0x0 mhi_dev_send_event] evnt code :0x2
[ 28.465233576/ 0x24c7ba8f] [0x0 mhi_dev_send_event] evnt type :0x22
[ 28.465235138/ 0x24c7baad] [0x0 mhi_dev_send_event] evnt chid :0x15
[ 28.465321648/ 0x24c7c12c] [0x0 mhi_dev_isr] mhi irq triggered
[ 28.465334826/ 0x24c7c229] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 28.465345138/ 0x24c7c2ed] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 28.465348628/ 0x24c7c330] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 28.465351180/ 0x24c7c361] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 28.465353211/ 0x24c7c388] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 28.465355034/ 0x24c7c3ab] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 28.465357430/ 0x24c7c3da] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 28.465359044/ 0x24c7c3f9] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:2 wp:0
[ 28.465362221/ 0x24c7c435] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc010
[ 28.465364826/ 0x24c7c467] [0x0 mhi_dev_cache_ring] caching ring_id:28, start 0, end 1
[ 28.465367326/ 0x24c7c497] [0x0 mhi_dev_read_from_host_ipa] device 0x695f676e8b4dd000 <<-- host 0x100058cc000, size 16
[ 28.465414513/ 0x24c7c822] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:2 with wr:1
[ 28.465417794/ 0x24c7c861] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 28.465420398/ 0x24c7c892] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:2
[ 30.965477646/ 0x27a438ee] [0x0 mhi_dev_isr] mhi irq triggered
[ 30.965516500/ 0x27a43bcf] [0x0 mhi_dev_scheduler] processing ctrl interrupt with 5
[ 30.965520979/ 0x27a43c1e] [0x0 mhi_dev_scheduler] BHI_IMGTXDB = 0x0
[ 30.965523739/ 0x27a43c55] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x500, reset:0
[ 30.965553166/ 0x27a43e87] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 30.967816187/ 0x27a4e841] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_M3_STATE
[ 30.967826812/ 0x27a4e90d] [0x0 mhi_dev_notify_sm_event] EXIT
[ 30.967833271/ 0x27a4e989] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 30.975129625/ 0x27a70cca] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_M3_STATE event, current states: M0 & D0_STATE
[ 30.975140979/ 0x27a70d9d] [0x0 mhi_sm_prepare_suspend] Switching event:5
[ 30.975143375/ 0x27a70dcb] [0x0 mhi_sm_prepare_suspend] ENTRY
[ 30.975145198/ 0x27a70dee] [0x0 mhi_sm_prepare_suspend] Switching state from 2 state with event:5
[ 30.975152333/ 0x27a70e77] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e7980370, size 4
[ 30.976274104/ 0x27a762a9] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e798039c, size 4
[ 30.978486031/ 0x27a80889] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e79807e8, size 4
[ 30.980691708/ 0x27a8adf5] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e7980814, size 4
[ 31.006306604/ 0x27b02f09] [0x0 mhi_sm_mmio_set_mhistatus] ENTRY
[ 31.006309417/ 0x27b02f3f] [0x0 mhi_sm_mmio_set_mhistatus] set MHISTATUS.MHISTATE to M3 state
[ 31.006313531/ 0x27b02f8e] [0x0 mhi_sm_mmio_set_mhistatus] EXIT
[ 31.006317854/ 0x27b02fe1] [0x0 mhi_dev_send_multiple_tr_events] Flushing 0 cmpl events of cmd ring
[ 31.006323896/ 0x27b03056] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 31.006326656/ 0x27b0308a] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x2d, new-offset 0x2e
[ 31.006330354/ 0x27b030d1] [0x0 mhi_dev_add_element] evnt ptr : 0x200000005
[ 31.006332750/ 0x27b030ff] [0x0 mhi_dev_add_element] evnt len : 0x0
[ 31.006334417/ 0x27b0311f] [0x0 mhi_dev_add_element] evnt code :0x5
[ 31.006336187/ 0x27b03141] [0x0 mhi_dev_add_element] evnt type :0x20
[ 31.006337802/ 0x27b03160] [0x0 mhi_dev_add_element] evnt ch_id :0x0
[ 31.006340615/ 0x27b03196] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b532d0, size 16
[ 31.006362229/ 0x27b03335] [0x0 mhi_dev_send_multiple_tr_events] Caching rp 9b532e0 for rd offset 46
[ 31.006404990/ 0x27b0366a] [0x0 mhi_dev_send_multiple_tr_events] ev.rp = 9b532e0 for 1
[ 31.006407750/ 0x27b0369f] [0x0 mhi_dev_send_multiple_tr_events] RP phy addr = 0x8b9db170 for ring rd offset 46
[ 31.006410458/ 0x27b036d3] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 31.006447542/ 0x27b0399b] [0x0 mhi_dev_schedule_msi_ipa] Sending MSI 1 to 0xfee30040 as data = 0x1 for cmd ack ereq flush_num 0
[ 31.006451292/ 0x27b039e3] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100fee30040, size 4
[ 31.006457906/ 0x27b03a62] [0x0 mhi_sm_prepare_suspend] Disable IPA with ipa_dma_disable()
[ 31.008896240/ 0x27b0f142] [0x0 mhi_dev_sm_pcie_handler] ENTRY
[ 31.008898948/ 0x27b0f176] [0x0 mhi_dev_sm_pcie_handler] received: EP_PCIE_PM_D3_HOT_EVENT
[ 31.008904521/ 0x27b0f1e2] [0x0 mhi_dev_sm_pcie_handler] Disable MHI IRQ during D3 HOT
[ 31.009172021/ 0x27b105f1] [0x0 mhi_dev_sm_pcie_handler] Hold wake for D3_HOT event
[ 31.009180250/ 0x27b1068f] [0x0 mhi_dev_sm_pcie_handler] EXIT
[ 31.015986604/ 0x27b3050b] [0x0 mhi_dev_event_buf_completion_cb] Event buf dma completed for flush req 0
[ 31.015994833/ 0x27b305a7] [0x0 mhi_dev_event_rd_offset_completion_cb] Rd offset dma completed for flush req 0
[ 31.015999052/ 0x27b305f8] [0x0 mhi_dev_cmd_event_msi_cb] MSI completed for flush req 0
[ 31.016066187/ 0x27b30b05] [0x0 mhi_sm_prepare_suspend] IPA disable fail cnt:0
[ 31.040149729/ 0x27ba194d] [0x0 mhi_sm_prepare_suspend] IPA DMA successfully disabled
[ 31.040157542/ 0x27ba19db] [0x0 mhi_sm_prepare_suspend] EXIT
[ 31.040162125/ 0x27ba1a33] [0x0 mhi_dev_pm_relax] releasing mhi wakelock
[ 31.040165927/ 0x27ba1a7c] [0x0 mhi_sm_dev_event_manager] EXIT
[ 31.040172906/ 0x27ba1b01] [0x0 mhi_sm_pcie_event_manager] ENTRY
[ 31.045538219/ 0x27bbad68] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D3_HOT_EVENT event, current states: M3 and D0_STATE
[ 31.045544521/ 0x27bbade1] [0x0 mhi_sm_pcie_event_manager] Release wake for D3_HOT event
[ 31.045547229/ 0x27bbae15] [0x0 mhi_sm_pcie_event_manager] EXIT
[ 31.785479679/ 0x2894750f] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 31.785490096/ 0x289475cc] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 31.785494211/ 0x2894761b] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 31.785498273/ 0x28947669] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 31.785501971/ 0x289476b0] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 31.785506034/ 0x289476fe] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 31.785509940/ 0x28947749] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 31.785513690/ 0x28947791] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 31.785517596/ 0x289477dc] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 31.785521606/ 0x28947829] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 31.785525356/ 0x28947871] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 31.785529211/ 0x289478bb] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 31.785533065/ 0x28947905] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 31.785989054/ 0x28949b41] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 31.785995825/ 0x28949bba] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 31.785999888/ 0x28949c08] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 31.786003690/ 0x28949c51] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 31.786007388/ 0x28949c98] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 31.786011190/ 0x28949ce1] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 31.786014992/ 0x28949d2a] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 31.786018898/ 0x28949d75] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 31.786022648/ 0x28949dbd] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 31.786026554/ 0x28949e08] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 31.786030304/ 0x28949e51] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 31.786034107/ 0x28949e99] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 31.786037909/ 0x28949ee2] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 31.786507544/ 0x2894c224] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 31.786514732/ 0x2894c2a5] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 31.786519054/ 0x2894c2f8] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 31.786522961/ 0x2894c343] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 31.786526659/ 0x2894c38a] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 31.786530409/ 0x2894c3d2] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 31.786534211/ 0x2894c41b] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 31.786538065/ 0x2894c465] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 31.786542075/ 0x2894c4b2] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 31.786545982/ 0x2894c4fd] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 31.786549784/ 0x2894c546] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 31.786553690/ 0x2894c591] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 31.786557492/ 0x2894c5da] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 31.787008117/ 0x2894e7b0] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 31.787014784/ 0x2894e826] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 31.787018898/ 0x2894e875] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 31.787022752/ 0x2894e8bf] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 31.787026659/ 0x2894e90a] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 31.787030565/ 0x2894e955] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 31.787034367/ 0x2894e99e] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 31.787038169/ 0x2894e9e7] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 31.787041971/ 0x2894ea30] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 31.787045773/ 0x2894ea79] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 31.787049523/ 0x2894eac1] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 31.787053273/ 0x2894eb09] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 31.787057075/ 0x2894eb52] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 31.787510044/ 0x28950d54] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 31.787516659/ 0x28950dca] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 31.787520617/ 0x28950e16] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 31.787524419/ 0x28950e5f] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 31.787528117/ 0x28950ea6] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 31.787531919/ 0x28950eef] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 31.787535721/ 0x28950f38] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 31.787539523/ 0x28950f81] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 31.787543325/ 0x28950fca] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 31.787547075/ 0x28951012] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 31.787550825/ 0x2895105b] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 31.787554575/ 0x289510a2] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 31.787558482/ 0x289510ed] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 31.788011190/ 0x289532e6] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 31.788017232/ 0x28953355] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 31.788021190/ 0x289533a1] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 31.788025044/ 0x289533eb] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 31.788028846/ 0x28953434] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 31.788032596/ 0x2895347c] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 31.788036450/ 0x289534c6] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 31.788040461/ 0x28953513] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 31.788044367/ 0x2895355e] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 31.788048117/ 0x289535a6] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 31.788051971/ 0x289535f0] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 31.788055721/ 0x28953638] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 31.788059679/ 0x28953684] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 31.788517388/ 0x289558df] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 31.788524263/ 0x2895595c] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 31.788528117/ 0x289559a7] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 31.788532075/ 0x289559f2] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 31.788535773/ 0x28955a39] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 31.788539471/ 0x28955a80] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 31.788543325/ 0x28955aca] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 31.788547179/ 0x28955b14] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 31.788551138/ 0x28955b60] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 31.788555044/ 0x28955bab] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 31.788558846/ 0x28955bf4] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 31.788562700/ 0x28955c3e] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 31.788566502/ 0x28955c87] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 32.628727807/ 0x298b80a3] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 32.628732547/ 0x298b80fb] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 32.651925776/ 0x29924c84] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 32.651941192/ 0x29924da1] [0x0 mhi_dev_notify_sm_event] EXIT
[ 32.651948484/ 0x29924e2f] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 32.651986557/ 0x29925108] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 32.651992495/ 0x2992517a] [0x0 mhi_sm_wakeup_host] ENTRY
[ 32.661669265/ 0x2995273e] [0x0 mhi_sm_wakeup_host] EXIT
[ 32.661674265/ 0x2995279d] [0x0 mhi_sm_dev_event_manager] EXIT
[ 33.616261768/ 0x2aacd1b6] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 33.616271560/ 0x2aacd26a] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 33.616275935/ 0x2aacd2bc] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 33.616279893/ 0x2aacd308] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 33.616283591/ 0x2aacd34f] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 33.616287758/ 0x2aacd39f] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 33.616291664/ 0x2aacd3ea] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 33.616295623/ 0x2aacd436] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 33.616299685/ 0x2aacd484] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 33.616303695/ 0x2aacd4d1] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 33.616307445/ 0x2aacd519] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 33.616311352/ 0x2aacd564] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 33.616315206/ 0x2aacd5af] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 33.616437602/ 0x2aacdedd] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 33.616443435/ 0x2aacdf4c] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 33.616447341/ 0x2aacdf97] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 33.616451195/ 0x2aacdfe1] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 33.616454893/ 0x2aace028] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 33.616458591/ 0x2aace06f] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 33.616462706/ 0x2aace0be] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 33.616466508/ 0x2aace107] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 33.616470310/ 0x2aace150] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 33.616474060/ 0x2aace198] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 33.616477914/ 0x2aace1e2] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 33.616481716/ 0x2aace22b] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 33.616485518/ 0x2aace274] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 33.616589320/ 0x2aacea3f] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 33.616594008/ 0x2aacea97] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 33.616597966/ 0x2aaceae3] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 33.616601768/ 0x2aaceb2c] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 33.616605466/ 0x2aaceb74] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 33.616609216/ 0x2aacebbb] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 33.616613018/ 0x2aacec04] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 33.616616820/ 0x2aacec4d] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 33.616620779/ 0x2aacec99] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 33.616624529/ 0x2aacece1] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 33.616628383/ 0x2aaced2b] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 33.616632185/ 0x2aaced74] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 33.616636039/ 0x2aacedbe] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 33.616734685/ 0x2aacf52a] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 33.616739893/ 0x2aacf588] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 33.616743852/ 0x2aacf5d4] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 33.616747706/ 0x2aacf61e] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 33.616751404/ 0x2aacf666] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 33.616755154/ 0x2aacf6ad] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 33.616758956/ 0x2aacf6f6] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 33.616762758/ 0x2aacf73f] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 33.616766560/ 0x2aacf788] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 33.616770310/ 0x2aacf7d0] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 33.616774112/ 0x2aacf819] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 33.616777914/ 0x2aacf862] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 33.616781873/ 0x2aacf8ae] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 33.616878487/ 0x2aacffee] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 33.616882914/ 0x2aad0042] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 33.616886925/ 0x2aad008f] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 33.616890779/ 0x2aad00d9] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 33.616894529/ 0x2aad0121] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 33.616898227/ 0x2aad0168] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 33.616902029/ 0x2aad01b1] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 33.616905883/ 0x2aad01fb] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 33.616909633/ 0x2aad0243] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 33.616913539/ 0x2aad028e] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 33.616917445/ 0x2aad02d9] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 33.616921300/ 0x2aad0324] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 33.616925102/ 0x2aad036c] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 33.617030779/ 0x2aad0b5e] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 33.617035883/ 0x2aad0bbb] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 33.617039789/ 0x2aad0c06] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 33.617043591/ 0x2aad0c4f] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 33.617047393/ 0x2aad0c98] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 33.617051143/ 0x2aad0ce0] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 33.617054998/ 0x2aad0d2a] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 33.617058852/ 0x2aad0d74] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 33.617062758/ 0x2aad0dbf] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 33.617066560/ 0x2aad0e08] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 33.617070362/ 0x2aad0e51] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 33.617074112/ 0x2aad0e99] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 33.617077914/ 0x2aad0ee2] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 33.617179320/ 0x2aad167e] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 33.617184112/ 0x2aad16d9] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 33.617188123/ 0x2aad1726] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 33.617191873/ 0x2aad176e] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 33.617195623/ 0x2aad17b6] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 33.617199320/ 0x2aad17fd] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 33.617203123/ 0x2aad1846] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 33.617206977/ 0x2aad1890] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 33.617210831/ 0x2aad18da] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 33.617214633/ 0x2aad1923] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 33.617218435/ 0x2aad196c] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 33.617222185/ 0x2aad19b4] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 33.617225987/ 0x2aad19fd] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 35.070565627/ 0x2c56e27e] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 35.110121565/ 0x2c62792c] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 35.110126148/ 0x2c627980] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 35.114465627/ 0x2c63bef6] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 35.114477919/ 0x2c63bfe2] [0x0 mhi_dev_notify_sm_event] EXIT
[ 35.114486460/ 0x2c63c088] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 35.122076773/ 0x2c65f9d1] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 35.122088023/ 0x2c65faa4] [0x0 mhi_sm_wakeup_host] ENTRY
[ 35.132481721/ 0x2c69062d] [0x0 mhi_sm_wakeup_host] EXIT
[ 35.132486356/ 0x2c690684] [0x0 mhi_sm_dev_event_manager] EXIT
[ 36.410844694/ 0x2ddf8b70] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 36.410855683/ 0x2ddf8c37] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 36.410860110/ 0x2ddf8c8c] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 36.410864121/ 0x2ddf8cd9] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 36.410867819/ 0x2ddf8d20] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 36.410871673/ 0x2ddf8d6a] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 36.410875631/ 0x2ddf8db6] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 36.410879485/ 0x2ddf8e00] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 36.410883391/ 0x2ddf8e4b] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 36.410887454/ 0x2ddf8e99] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 36.410891204/ 0x2ddf8ee1] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 36.410895110/ 0x2ddf8f2c] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 36.410899016/ 0x2ddf8f77] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 36.413941152/ 0x2de073ae] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 36.413951725/ 0x2de0746c] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 36.413956464/ 0x2de074c6] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 36.413960423/ 0x2de07512] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 36.413964069/ 0x2de07558] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 36.413967975/ 0x2de075a3] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 36.413972037/ 0x2de075f1] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 36.413975787/ 0x2de07639] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 36.413979641/ 0x2de07683] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 36.413983808/ 0x2de076d3] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 36.413987506/ 0x2de0771a] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 36.413991360/ 0x2de07764] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 36.413995266/ 0x2de077af] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 36.416850214/ 0x2de14dd7] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 36.416861100/ 0x2de14e9f] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 36.416865423/ 0x2de14ef3] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 36.416869433/ 0x2de14f3f] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 36.416873652/ 0x2de14f90] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 36.416877558/ 0x2de14fdb] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 36.416881621/ 0x2de15029] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 36.416885527/ 0x2de15074] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 36.416889589/ 0x2de150c2] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 36.416893600/ 0x2de1510f] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 36.416897402/ 0x2de15158] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 36.416901308/ 0x2de151a3] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 36.416905214/ 0x2de151ee] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 36.419264329/ 0x2de202eb] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 36.419275579/ 0x2de203b5] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 36.419280058/ 0x2de2040b] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 36.419283964/ 0x2de20456] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 36.419287662/ 0x2de2049d] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 36.419291569/ 0x2de204e8] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 36.419295475/ 0x2de20533] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 36.419299277/ 0x2de2057c] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 36.419303183/ 0x2de205c7] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 36.419307246/ 0x2de20615] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 36.419310996/ 0x2de2065d] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 36.419314902/ 0x2de206a8] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 36.419318808/ 0x2de206f3] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 36.428301464/ 0x2de4a8b3] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 36.428312089/ 0x2de4a973] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 36.428316621/ 0x2de4a9c9] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 36.428320527/ 0x2de4aa14] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 36.428324225/ 0x2de4aa5b] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 36.428328079/ 0x2de4aaa5] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 36.428332037/ 0x2de4aaf1] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 36.428335839/ 0x2de4ab3a] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 36.428339694/ 0x2de4ab84] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 36.428343704/ 0x2de4abd1] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 36.428347506/ 0x2de4ac1a] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 36.428351412/ 0x2de4ac65] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 36.428355319/ 0x2de4acb0] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 36.430755996/ 0x2de560c8] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 36.430766569/ 0x2de56188] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 36.430771256/ 0x2de561e2] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 36.430775371/ 0x2de56231] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 36.430779121/ 0x2de56279] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 36.430782975/ 0x2de562c3] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 36.430787089/ 0x2de56312] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 36.430790996/ 0x2de5635d] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 36.430795006/ 0x2de563aa] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 36.430799017/ 0x2de563f7] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 36.430802819/ 0x2de56440] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 36.430806725/ 0x2de5648b] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 36.430810631/ 0x2de564d6] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 36.434903496/ 0x2de697d6] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 36.434913496/ 0x2de69890] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 36.434917923/ 0x2de698e2] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 36.434921881/ 0x2de6992e] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 36.434925579/ 0x2de69975] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 36.434929381/ 0x2de699be] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 36.434933652/ 0x2de69a10] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 36.434937558/ 0x2de69a5c] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 36.434941673/ 0x2de69aaa] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 36.434945683/ 0x2de69af7] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 36.434949537/ 0x2de69b41] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 36.434953444/ 0x2de69b8c] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 36.434957402/ 0x2de69bd8] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 37.522997249/ 0x2f255ee2] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 37.600313760/ 0x2f3c0593] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 37.600318447/ 0x2f3c05ec] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 37.661693916/ 0x2f4e012a] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 37.661717718/ 0x2f4e02df] [0x0 mhi_dev_notify_sm_event] EXIT
[ 37.661726989/ 0x2f4e0391] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 37.664027458/ 0x2f4eb019] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 37.664033447/ 0x2f4eb08c] [0x0 mhi_sm_wakeup_host] ENTRY
[ 37.674919072/ 0x2f51e0fc] [0x0 mhi_sm_wakeup_host] EXIT
[ 37.674926260/ 0x2f51e182] [0x0 mhi_sm_dev_event_manager] EXIT
[ 38.803276159/ 0x309c73cb] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 38.803285586/ 0x309c7475] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 38.803289753/ 0x309c74c5] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 38.803293920/ 0x309c7515] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 38.803297670/ 0x309c755d] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 38.803301524/ 0x309c75a7] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 38.803305482/ 0x309c75f3] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 38.803309336/ 0x309c763d] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 38.803313295/ 0x309c7689] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 38.803317305/ 0x309c76d6] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 38.803321107/ 0x309c771f] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 38.803325013/ 0x309c776a] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 38.803328920/ 0x309c77b5] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 39.930374652/ 0x31e6a82c] [0x0 mhi_ctrl_state_info] idx:0, ctrl:1
[ 39.930384808/ 0x31e6a8e9] [0x0 mhi_ctrl_state_info] idx:12, ctrl:0
[ 39.930389756/ 0x31e6a945] [0x0 mhi_ctrl_state_info] idx:13, ctrl:0
[ 39.930393767/ 0x31e6a992] [0x0 mhi_ctrl_state_info] idx:4, ctrl:0
[ 39.930397465/ 0x31e6a9d9] [0x0 mhi_ctrl_state_info] idx:5, ctrl:0
[ 39.930401475/ 0x31e6aa26] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 39.930405433/ 0x31e6aa72] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 39.930409444/ 0x31e6aabf] [0x0 mhi_ctrl_state_info] idx:20, ctrl:1
[ 39.930413506/ 0x31e6ab0d] [0x0 mhi_ctrl_state_info] idx:21, ctrl:1
[ 39.930417517/ 0x31e6ab5a] [0x0 mhi_ctrl_state_info] idx:32, ctrl:0
[ 39.930421319/ 0x31e6aba3] [0x0 mhi_ctrl_state_info] idx:33, ctrl:0
[ 39.930425225/ 0x31e6abee] [0x0 mhi_ctrl_state_info] idx:36, ctrl:0
[ 39.930429131/ 0x31e6ac39] [0x0 mhi_ctrl_state_info] idx:37, ctrl:0
[ 40.084487830/ 0x3213ceab] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 40.210979080/ 0x3238dd7e] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 40.210983976/ 0x3238ddd6] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 40.264381580/ 0x324882a8] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 40.264384497/ 0x324882e0] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 40.306153612/ 0x3254bf9c] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 40.306176528/ 0x3254c147] [0x0 mhi_dev_notify_sm_event] EXIT
[ 40.306187310/ 0x3254c218] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 40.306226945/ 0x3254c512] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 40.306232883/ 0x3254c581] [0x0 mhi_sm_wakeup_host] ENTRY
[ 40.315836945/ 0x325795d0] [0x0 mhi_sm_wakeup_host] EXIT
[ 40.315842101/ 0x32579633] [0x0 mhi_sm_dev_event_manager] EXIT
[ 41.264731792/ 0x336d94ec] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 41.264735438/ 0x336d9532] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 42.264948930/ 0x34929d35] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 42.264952420/ 0x34929d78] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 42.720250025/ 0x351800d7] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 42.740162265/ 0x351dd637] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 42.740168567/ 0x351dd6ae] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 42.740199661/ 0x351dd906] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 42.740212317/ 0x351dd9f6] [0x0 mhi_dev_notify_sm_event] EXIT
[ 42.740222317/ 0x351ddab7] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 42.746284973/ 0x351fa16a] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 42.746290807/ 0x351fa1d9] [0x0 mhi_sm_wakeup_host] ENTRY
[ 42.757225546/ 0x3522d5fe] [0x0 mhi_sm_wakeup_host] EXIT
[ 42.757233880/ 0x3522d694] [0x0 mhi_sm_dev_event_manager] EXIT
[ 43.265209350/ 0x35b7a8bd] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 43.265212110/ 0x35b7a8f2] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 44.265424926/ 0x36dcb0e8] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 44.265427790/ 0x36dcb11f] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 45.150969772/ 0x37e020de] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 45.172092168/ 0x37e650fe] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 45.172105449/ 0x37e651f6] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 45.172151804/ 0x37e65574] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 45.172175502/ 0x37e65739] [0x0 mhi_dev_notify_sm_event] EXIT
[ 45.172189564/ 0x37e65847] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 45.178237377/ 0x37e81ddc] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 45.178253158/ 0x37e81f0a] [0x0 mhi_sm_wakeup_host] ENTRY
[ 45.189238106/ 0x37eb56ea] [0x0 mhi_sm_wakeup_host] EXIT
[ 45.189241752/ 0x37eb572b] [0x0 mhi_sm_dev_event_manager] EXIT
[ 45.267046335/ 0x3802228b] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 45.267058210/ 0x38022370] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 46.267445036/ 0x39273873] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 46.267457015/ 0x39273959] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 47.268650195/ 0x3a4c8ad7] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 47.268661654/ 0x3a4c8bb2] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 47.580979780/ 0x3aa80b9e] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 47.593790092/ 0x3aabcc50] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 47.593801446/ 0x3aabcd29] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 47.598211967/ 0x3aad17fc] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 47.598235978/ 0x3aad19c1] [0x0 mhi_dev_notify_sm_event] EXIT
[ 47.598262332/ 0x3aad1bbc] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 47.605584571/ 0x3aaf40f2] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 47.605607436/ 0x3aaf429c] [0x0 mhi_sm_wakeup_host] ENTRY
[ 47.616207488/ 0x3ab25d9b] [0x0 mhi_sm_wakeup_host] EXIT
[ 47.616211863/ 0x3ab25ded] [0x0 mhi_sm_dev_event_manager] EXIT
[ 48.269852959/ 0x3b71dd0b] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 48.269864209/ 0x3b71dde3] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 49.271164108/ 0x3c973761] [0x0 mhi_ctrl_state_info] idx:14, ctrl:0
[ 49.271176087/ 0x3c973847] [0x0 mhi_ctrl_state_info] idx:15, ctrl:0
[ 50.010986714/ 0x3d6ff624] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 50.039524318/ 0x3d78527f] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 50.039561246/ 0x3d78552a] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 50.039624996/ 0x3d7859f7] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 50.039663746/ 0x3d785cdb] [0x0 mhi_dev_notify_sm_event] EXIT
[ 50.039689423/ 0x3d785ec8] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 50.046273485/ 0x3d7a4c91] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 50.046281141/ 0x3d7a4d1f] [0x0 mhi_sm_wakeup_host] ENTRY
[ 50.056337964/ 0x3d7d3f63] [0x0 mhi_sm_wakeup_host] EXIT
[ 50.056341923/ 0x3d7d3fae] [0x0 mhi_sm_dev_event_manager] EXIT
[ 52.450970628/ 0x403accef] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 52.463595315/ 0x403e7fb8] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 52.463608180/ 0x403e80a7] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 52.468121618/ 0x403fd330] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 52.468136930/ 0x403fd450] [0x0 mhi_dev_notify_sm_event] EXIT
[ 52.468145055/ 0x403fd4ed] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 52.475496045/ 0x4041fc3f] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 52.475505628/ 0x4041fcf6] [0x0 mhi_sm_wakeup_host] ENTRY
[ 52.485894066/ 0x40450818] [0x0 mhi_sm_wakeup_host] EXIT
[ 52.485897555/ 0x4045085a] [0x0 mhi_sm_dev_event_manager] EXIT
[ 54.881027719/ 0x4302bb32] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 54.893505010/ 0x430662f8] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 54.893525115/ 0x43066470] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 54.898176990/ 0x4307c157] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 54.898200635/ 0x4307c31b] [0x0 mhi_dev_notify_sm_event] EXIT
[ 54.898213448/ 0x4307c410] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 54.905679021/ 0x4309f3fd] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 54.905688604/ 0x4309f4ae] [0x0 mhi_sm_wakeup_host] ENTRY
[ 54.915830635/ 0x430ced59] [0x0 mhi_sm_wakeup_host] EXIT
[ 54.915835375/ 0x430cedb0] [0x0 mhi_sm_dev_event_manager] EXIT
[ 57.310983872/ 0x45caa1ed] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 57.323804237/ 0x45ce6374] [0x0 mhi_dev_write_channel] Wakeup by ch_id:21
[ 57.323925330/ 0x45ce6c78] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 57.328176684/ 0x45cfab62] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_CORE_WAKEUP
[ 57.328214289/ 0x45cfae25] [0x0 mhi_dev_notify_sm_event] EXIT
[ 57.328233247/ 0x45cfaf90] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 57.335650382/ 0x45d1dbd5] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_CORE_WAKEUP event, current states: M3 & D3_HOT_STATE
[ 57.335659080/ 0x45d1dc77] [0x0 mhi_sm_wakeup_host] ENTRY
[ 57.345776424/ 0x45d4d346] [0x0 mhi_sm_wakeup_host] EXIT
[ 57.345780330/ 0x45d4d38f] [0x0 mhi_sm_dev_event_manager] EXIT
[ 59.740974661/ 0x48928b3c] [0x0 mhi_dev_write_channel] Failed to wake up core
[ 90.129581993/ 0x6b5974b4] [0x0 mhi_dev_sm_pcie_handler] ENTRY
[ 90.129591472/ 0x6b59756c] [0x0 mhi_dev_sm_pcie_handler] received: EP_PCIE_PM_D0_EVENT
[ 90.129610951/ 0x6b5976e3] [0x0 mhi_dev_sm_pcie_handler] Enable MHI IRQ during D0
[ 90.129618764/ 0x6b597777] [0x0 mhi_dev_sm_pcie_handler] Hold wake for D0 change event
[ 90.129651107/ 0x6b5979e6] [0x0 mhi_dev_sm_pcie_handler] EXIT
[ 90.129717878/ 0x6b597ee8] [0x0 mhi_sm_pcie_event_manager] ENTRY
[ 90.129796003/ 0x6b5984c6] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D0_EVENT event, current states: M3 and D3_HOT_STATE
[ 90.129821837/ 0x6b5986b3] [0x0 mhi_sm_pcie_event_manager] Release wake for D0 change event
[ 90.129837514/ 0x6b5987df] [0x0 mhi_sm_pcie_event_manager] EXIT
[ 90.142567930/ 0x6b5d42a8] [0x0 mhi_dev_isr] acquiring mhi wakelock in ISR
[ 90.142599597/ 0x6b5d4509] [0x0 mhi_dev_isr] mhi irq triggered
[ 90.142693764/ 0x6b5d4c20] [0x0 mhi_dev_scheduler] processing ctrl interrupt with 5
[ 90.142705951/ 0x6b5d4d02] [0x0 mhi_dev_scheduler] BHI_IMGTXDB = 0x0
[ 90.142714910/ 0x6b5d4dae] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x200, reset:0
[ 90.142773816/ 0x6b5d521b] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 90.145035795/ 0x6b5dfbc0] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_M0_STATE
[ 90.145070951/ 0x6b5dfe62] [0x0 mhi_dev_notify_sm_event] Got M0, wait until resume is done
[ 90.145091108/ 0x6b5dffe6] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 90.152062566/ 0x6b600aca] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_M0_STATE event, current states: M3 & D0_STATE
[ 90.152092462/ 0x6b600cff] [0x0 mhi_sm_prepare_resume] ENTRY
[ 90.152330274/ 0x6b601ed3] [0x0 mhi_pcie_config_db_routing] Event rings 0x6 => er_base 0x4, er_end 5
[ 90.152365899/ 0x6b60217f] [0x0 mhi_sm_mmio_set_mhistatus] ENTRY
[ 90.152373868/ 0x6b60221b] [0x0 mhi_sm_mmio_set_mhistatus] set MHISTATUS.MHISTATE to M0 state
[ 90.152384389/ 0x6b6022e3] [0x0 mhi_sm_mmio_set_mhistatus] EXIT
[ 90.170311420/ 0x6b656362] [0x0 mhi_dev_send_multiple_tr_events] Flushing 0 cmpl events of cmd ring
[ 90.170317253/ 0x6b6563d4] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:1, local wr_ofst 44
[ 90.170319962/ 0x6b656406] [0x0 mhi_dev_cache_ring] new wr_offset 44
[ 90.170322253/ 0x6b656432] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x2e, new-offset 0x2f
[ 90.170325847/ 0x6b656477] [0x0 mhi_dev_add_element] evnt ptr : 0x9a0b1082f52
[ 90.170328295/ 0x6b6564a6] [0x0 mhi_dev_add_element] evnt len : 0x0
[ 90.170329910/ 0x6b6564c5] [0x0 mhi_dev_add_element] evnt code :0x2
[ 90.170331681/ 0x6b6564e6] [0x0 mhi_dev_add_element] evnt type :0x20
[ 90.170333295/ 0x6b656506] [0x0 mhi_dev_add_element] evnt ch_id :0x0
[ 90.170336108/ 0x6b65653c] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b532e0, size 16
[ 90.170352983/ 0x6b656680] [0x0 mhi_dev_send_multiple_tr_events] Caching rp 9b532f0 for rd offset 47
[ 90.170392201/ 0x6b656971] [0x0 mhi_dev_send_multiple_tr_events] ev.rp = 9b532f0 for 1
[ 90.170394806/ 0x6b6569a3] [0x0 mhi_dev_send_multiple_tr_events] RP phy addr = 0x8b9db178 for ring rd offset 47
[ 90.170397670/ 0x6b6569da] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 90.170433556/ 0x6b656c8b] [0x0 mhi_dev_schedule_msi_ipa] Sending MSI 1 to 0xfee30040 as data = 0x1 for cmd ack ereq flush_num 0
[ 90.170437201/ 0x6b656cd1] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100fee30040, size 4
[ 90.170446472/ 0x6b656d83] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e7980370, size 4
[ 90.170484233/ 0x6b657059] [0x0 mhi_dev_event_buf_completion_cb] Event buf dma completed for flush req 0
[ 90.170490535/ 0x6b6570d1] [0x0 mhi_dev_event_rd_offset_completion_cb] Rd offset dma completed for flush req 0
[ 90.170495170/ 0x6b65712a] [0x0 mhi_dev_cmd_event_msi_cb] MSI completed for flush req 0
[ 90.172583816/ 0x6b660dd1] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e798039c, size 4
[ 90.174713972/ 0x6b66ad95] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e79807e8, size 4
[ 90.176838556/ 0x6b674ced] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x100e7980814, size 4
[ 90.178972201/ 0x6b67ecf3] [0x0 mhi_sm_prepare_resume] EXIT
[ 90.178975795/ 0x6b67ed36] [0x0 mhi_sm_dev_event_manager] EXIT
[ 90.178985743/ 0x6b67edf8] [0x0 mhi_dev_notify_sm_event] EXIT
[ 90.178990535/ 0x6b67ee52] [0x0 mhi_dev_check_channel_interrupt] processing id: 0, ch interrupt 0x200000
[ 90.179007201/ 0x6b67ef94] [0x0 mhi_dev_isr] mhi irq triggered
[ 90.179018347/ 0x6b67f067] [0x0 mhi_dev_process_ring] Before wr update ring_id:0 rp:6 wp:6
[ 90.179022618/ 0x6b67f0ba] [0x0 mhi_dev_update_wr_offset] ring_id:0 wr_offset from db 0x1c68060
[ 90.179025483/ 0x6b67f0f0] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 6
[ 90.179027618/ 0x6b67f119] [0x0 mhi_dev_cache_ring] new wr_offset 6
[ 90.179029441/ 0x6b67f13c] [0x0 mhi_dev_process_ring] After wp update ring_id:0 rp:6 with wr:6
[ 90.179032670/ 0x6b67f17a] [0x0 mhi_dev_process_ring_pending] processing ring_id:28
[ 90.179035066/ 0x6b67f1a8] [0x0 mhi_dev_process_ring] Before wr update ring_id:28 rp:2 wp:1
[ 90.179038451/ 0x6b67f1e9] [0x0 mhi_dev_update_wr_offset] ring_id:28 wr_offset from db 0x58cc010
[ 90.179040847/ 0x6b67f218] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:28, local wr_ofst 1
[ 90.179042774/ 0x6b67f23c] [0x0 mhi_dev_cache_ring] new wr_offset 1
[ 90.179044337/ 0x6b67f259] [0x0 mhi_dev_process_ring] After wp update ring_id:28 rp:2 with wr:1
[ 90.179047097/ 0x6b67f28f] [0x0 mhi_dev_process_ring_element] TRE data buff ptr : 0x6c80000
[ 90.179049389/ 0x6b67f2bb] [0x0 mhi_dev_process_ring_element] TRE len : 0xffff, rd_offset:2
[ 90.179060847/ 0x6b67f399] [0x0 mhi_dev_scheduler] processing ctrl interrupt with 5
[ 90.179063608/ 0x6b67f3cc] [0x0 mhi_dev_scheduler] BHI_IMGTXDB = 0x0
[ 90.179066056/ 0x6b67f3fb] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x202, reset:1
[ 90.179068556/ 0x6b67f42c] [0x0 mhi_dev_scheduler] processing mhi device reset
[ 90.179080535/ 0x6b67f512] [0x0 mhi_ctrl_state_info] idx:21, ctrl:2
[ 90.192450951/ 0x6b6bdfe4] [0x0 mhi_dev_flush_transfer_completion_events] ch_id:20 closed with 1 writes pending
[ 90.192494128/ 0x6b6be319] [0x0 mhi_dev_close_channel] Failed to flush read completions to host
[ 90.214205639/ 0x6b723f8d] [0x0 mhi_dev_close_channel] 0 pending flush for ch_id:20
[ 90.214230170/ 0x6b72414e] [0x0 mhi_dev_close_channel] MEM_ALLOC:ch:20 size:56 CLNT_HANDLE
[ 90.214236056/ 0x6b7241bc] [0x0 mhi_dev_flush_transfer_completion_events] ch_id:21 closed with 1 writes pending
[ 90.214273816/ 0x6b724495] [0x0 mhi_dev_close_channel] Failed to flush read completions to host
[ 90.221811316/ 0x6b7479f2] [0x0 mhi_dev_close_channel] 0 pending flush for ch_id:21
[ 90.221832306/ 0x6b747b75] [0x0 mhi_dev_close_channel] MEM_ALLOC:ch:21 size:56 CLNT_HANDLE
[ 90.221840066/ 0x6b747c0c] [0x0 mhi_ctrl_state_info] idx:46, ctrl:2
[ 90.221843920/ 0x6b747c53] [0x0 mhi_ctrl_state_info] idx:47, ctrl:1
[ 90.221846785/ 0x6b747c8a] [0x0 mhi_ctrl_state_info] idx:46, ctrl:2
[ 90.250186212/ 0x6b7cca13] [0x0 mhi_dev_flush_transfer_completion_events] ch_id:46 closed with 1 writes pending
[ 90.250231264/ 0x6b7ccd62] [0x0 mhi_dev_close_channel] Failed to flush read completions to host
[ 90.256655639/ 0x6b7eaf33] [0x0 mhi_dev_close_channel] 0 pending flush for ch_id:46
[ 90.256661056/ 0x6b7eaf9c] [0x0 mhi_dev_close_channel] MEM_ALLOC:ch:46 size:56 CLNT_HANDLE
[ 90.256664181/ 0x6b7eafd7] [0x0 mhi_dev_flush_transfer_completion_events] ch_id:47 closed with 1 writes pending
[ 90.272946056/ 0x6b837507] [0x0 mhi_dev_close_channel] Failed to flush read completions to host
[ 90.272981472/ 0x6b8377a4] [0x0 mhi_dev_close_channel] 0 pending flush for ch_id:47
[ 90.272986993/ 0x6b83780d] [0x0 mhi_dev_close_channel] MEM_ALLOC:ch:47 size:56 CLNT_HANDLE
[ 90.273040743/ 0x6b837c16] [0x0 mhi_ctrl_state_info] idx:47, ctrl:2
[ 90.273043504/ 0x6b837c4b] [0x0 mhi_ctrl_state_info] idx:47, ctrl:2
[ 90.273045327/ 0x6b837c6d] [0x0 mhi_ctrl_state_info] idx:46, ctrl:2
[ 90.576563453/ 0x6bdc685a] [0x0 mhi_dev_sm_exit] ENTRY
[ 91.423930226/ 0x6cd4a8cf] [0x0 mhi_dev_abort] Register a PCIe callback during re-init
[ 91.423975591/ 0x6cd4ac35] [0x0 mhi_dev_sm_init] ENTRY
[ 91.424245278/ 0x6cd4c06d] [0x0 mhi_dev_sm_init] EXIT
[ 91.424249289/ 0x6cd4c0ba] [0x0 mhi_dev_sm_set_ready] ENTRY
[ 91.424254080/ 0x6cd4c116] [0x0 mhi_sm_mmio_set_mhistatus] ENTRY
[ 91.424257101/ 0x6cd4c150] [0x0 mhi_sm_mmio_set_mhistatus] set MHISTATUS to READY mode
[ 91.424261111/ 0x6cd4c19d] [0x0 mhi_sm_mmio_set_mhistatus] EXIT
[ 91.424263716/ 0x6cd4c1cf] [0x0 mhi_dev_sm_set_ready] EXIT
[ 91.424266476/ 0x6cd4c204] [0x0 mhi_dev_reinit] Wait for PCIe linkup
[ 91.431033872/ 0x6cd6bd93] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 91.473643976/ 0x6ce33957] [0x0 mhi_dev_sm_pcie_handler] ENTRY
[ 91.473650539/ 0x6ce339d6] [0x0 mhi_dev_sm_pcie_handler] received: EP_PCIE_PM_D3_HOT_EVENT
[ 91.473662622/ 0x6ce33abf] [0x0 mhi_dev_sm_pcie_handler] Disable MHI IRQ during D3 HOT
[ 91.473955382/ 0x6ce350b2] [0x0 mhi_dev_sm_pcie_handler] Hold wake for D3_HOT event
[ 91.473980643/ 0x6ce35298] [0x0 mhi_dev_sm_pcie_handler] EXIT
[ 91.474040434/ 0x6ce35715] [0x0 mhi_sm_pcie_event_manager] ENTRY
[ 91.474100278/ 0x6ce35b92] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D3_HOT_EVENT event, current states: READY and D0_STATE
[ 91.474116580/ 0x6ce35cca] [0x0 mhi_sm_pcie_event_manager] Release wake for D3_HOT event
[ 91.474127101/ 0x6ce35d93] [0x0 mhi_sm_pcie_event_manager] EXIT
[ 91.550914810/ 0x6cf9dcc8] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 91.670921841/ 0x6d1d054e] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 91.747774550/ 0x6d338926] [0x0 mhi_dev_sm_pcie_handler] ENTRY
[ 91.747784342/ 0x6d3389e2] [0x0 mhi_dev_sm_pcie_handler] received: EP_PCIE_PM_D3_COLD_EVENT
[ 91.747797779/ 0x6d338ae5] [0x0 mhi_dev_sm_pcie_handler] Hold wake for D3_COLD event
[ 91.747820435/ 0x6d338c97] [0x0 mhi_dev_sm_pcie_handler] EXIT
[ 91.747963196/ 0x6d339750] [0x0 mhi_sm_pcie_event_manager] ENTRY
[ 91.748044394/ 0x6d339d67] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D3_COLD_EVENT event, current states: READY and D3_HOT_STATE
[ 91.749135383/ 0x6d33ef36] [0x0 mhi_sm_pcie_event_manager] Release wake for D3_COLD event
[ 91.749160019/ 0x6d33f113] [0x0 mhi_sm_pcie_event_manager] EXIT
[ 91.795815644/ 0x6d419c39] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 91.910692519/ 0x7a6dd6a2] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 92.034316582/ 0x7a920e69] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 92.151044707/ 0x7ab4411f] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 92.270244239/ 0x7ad72d0d] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 92.390879187/ 0x7afa84b9] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 92.475274760/ 0x8f8e7fa4] [0x0 mhi_dev_sm_pcie_handler] ENTRY
[ 92.475278875/ 0x8f8e7ff4] [0x0 mhi_dev_sm_pcie_handler] received: EP_PCIE_PM_RST_DEAST_EVENT
[ 92.475285437/ 0x8f8e8071] [0x0 mhi_dev_sm_pcie_handler] Hold wake for perst deassert event
[ 92.475289604/ 0x8f8e80c1] [0x0 mhi_sm_pcie_event_manager] ENTRY
[ 92.475307729/ 0x8f8e821e] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_RST_DEAST_EVENT event, current states: READY and D3_COLD_STATE
[ 92.475372104/ 0x8f8e86f0] [0x0 mhi_dev_sm_pcie_handler] ENTRY
[ 92.475374239/ 0x8f8e871a] [0x0 mhi_dev_sm_pcie_handler] received: EP_PCIE_PM_D3_COLD_EVENT
[ 92.475377729/ 0x8f8e875e] [0x0 mhi_dev_sm_pcie_handler] Hold wake for D3_COLD event
[ 92.475385021/ 0x8f8e87e9] [0x0 mhi_dev_sm_pcie_handler] EXIT
[ 92.475475229/ 0x8f8e8eaf] [0x0 mhi_sm_pcie_event_manager] ENTRY
[ 92.478337468/ 0x8f8f6559] [0x0 mhi_sm_pcie_event_manager] Enable MHI IRQ during PCIe DEAST
[ 92.516083041/ 0x8f9a7448] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 92.542046375/ 0x8fa20f83] [0x0 mhi_sm_pcie_event_manager] Release wake for perst deassert event
[ 92.542058667/ 0x8fa2106f] [0x0 mhi_sm_pcie_event_manager] EXIT
[ 92.542061896/ 0x8fa210ae] [0x0 mhi_dev_sm_pcie_handler] EXIT
[ 92.542070854/ 0x8fa21159] [0x0 mhi_dev_sm_pcie_handler] ENTRY
[ 92.542073927/ 0x8fa21194] [0x0 mhi_dev_sm_pcie_handler] received: EP_PCIE_PM_RST_DEAST_EVENT
[ 92.542079708/ 0x8fa21204] [0x0 mhi_dev_sm_pcie_handler] Hold wake for perst deassert event
[ 92.542084500/ 0x8fa2125f] [0x0 mhi_sm_pcie_event_manager] ENTRY
[ 92.550548354/ 0x8fa48d29] [0x0 mhi_dev_sm_pcie_handler] ENTRY
[ 92.550550854/ 0x8fa48d5a] [0x0 mhi_dev_sm_pcie_handler] received: EP_PCIE_PM_D0_EVENT
[ 92.550555073/ 0x8fa48daa] [0x0 mhi_dev_sm_pcie_handler] Hold wake for D0 change event
[ 92.550563250/ 0x8fa48e47] [0x0 mhi_dev_sm_pcie_handler] EXIT
[ 92.550574552/ 0x8fa48f21] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_RST_DEAST_EVENT event, current states: READY and D0_STATE
[ 92.550583771/ 0x8fa48fd2] [0x0 mhi_sm_pcie_event_manager] Nothing to do, already in D0 state
[ 92.550588042/ 0x8fa49023] [0x0 mhi_sm_pcie_event_manager] EXIT
[ 92.550590385/ 0x8fa49050] [0x0 mhi_dev_sm_pcie_handler] EXIT
[ 92.561593979/ 0x8fa7c99e] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D3_COLD_EVENT event, current states: READY and D0_STATE
[ 92.561611375/ 0x8fa7cae3] [0x0 mhi_sm_pcie_event_manager] Release wake for D3_COLD event
[ 92.561615385/ 0x8fa7cb30] [0x0 mhi_sm_pcie_event_manager] EXIT
[ 92.561618615/ 0x8fa7cb6e] [0x0 mhi_sm_pcie_event_manager] ENTRY
[ 92.572147833/ 0x8faae124] [0x0 mhi_sm_pcie_event_manager] Handling EP_PCIE_PM_D0_EVENT event, current states: READY and D3_COLD_STATE
[ 92.582932521/ 0x8fae09fd] [0x0 mhi_sm_pcie_event_manager] EP_PCIE_PM_D0_EVENT: illegal in current MHI state: READY and D3_COLD_STATE
[ 92.582943042/ 0x8fae0ac4] [0x0 mhi_sm_handle_syserr] ENTRY
[ 92.582950594/ 0x8fae0b58] [0x0 mhi_sm_handle_syserr] Start handling SYSERR, MHI state: READY and D3_COLD_STATE
[ 92.582962885/ 0x8fae0c40] [0x0 mhi_sm_mmio_set_mhistatus] ENTRY
[ 92.582965646/ 0x8fae0c75] [0x0 mhi_sm_mmio_set_mhistatus] set MHISTATUS to SYSTEM ERROR mode
[ 92.582970333/ 0x8fae0ccf] [0x0 mhi_sm_mmio_set_mhistatus] EXIT
[ 92.582975594/ 0x8fae0d35] [0x0 mhi_dev_send_multiple_tr_events] Flushing 0 cmpl events of cmd ring
[ 92.582982885/ 0x8fae0dc1] [0x0 mhi_dev_cache_ring] not caching event ring_id:1
[ 92.582986635/ 0x8fae0e08] [0x0 mhi_dev_add_element] Writing 1 elements in ring_id:1 ring old-offset 0x2f, new-offset 0x30
[ 92.582992052/ 0x8fae0e71] [0x0 mhi_dev_add_element] evnt ptr : 0xb143f0f8b0d80bac
[ 92.582995542/ 0x8fae0eb3] [0x0 mhi_dev_add_element] evnt len : 0x0
[ 92.582998146/ 0x8fae0ee5] [0x0 mhi_dev_add_element] evnt code :0xff
[ 92.583000802/ 0x8fae0f18] [0x0 mhi_dev_add_element] evnt type :0x20
[ 92.583003354/ 0x8fae0f4a] [0x0 mhi_dev_add_element] evnt ch_id :0x0
[ 92.583007260/ 0x8fae0f94] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b532f0, size 16
[ 92.583033250/ 0x8fae1188] [0x0 mhi_dev_send_multiple_tr_events] Caching rp 9b53300 for rd offset 48
[ 92.583077365/ 0x8fae14da] [0x0 mhi_dev_send_multiple_tr_events] ev.rp = 9b53300 for 1
[ 92.583081427/ 0x8fae1525] [0x0 mhi_dev_send_multiple_tr_events] RP phy addr = 0x8b9db180 for ring rd offset 48
[ 92.583085490/ 0x8fae1572] [0x0 mhi_dev_write_to_host_ipa] device 0x8b9c0000 --> host 0x10009b5201c, size 8
[ 92.602647677/ 0x8fb3d0a0] [0x0 mhi_dev_event_buf_completion_cb] Event buf dma completed for flush req 0
[ 92.602658563/ 0x8fb3d16e] [0x0 mhi_dev_event_rd_offset_completion_cb] Rd offset dma completed for flush req 0
[ 92.609634083/ 0x8fb5dc9a] [0x0 mhi_dev_schedule_msi_ipa] Error retrieving pcie msi logic
[ 92.616522886/ 0x8fb7e141] [0x0 mhi_dev_send_multiple_tr_events] error sending in msi
[ 92.623031011/ 0x8fb9c963] [0x0 mhi_dev_flush_cmd_completion_events] failed to send compl evts
[ 92.630219344/ 0x8fbbe47e] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 92.630230125/ 0x8fbbe54c] [0x0 mhi_sm_handle_syserr] Failed to send SYSTEM ERROR state change event to host
[ 92.630239969/ 0x8fbbe60b] [0x0 mhi_sm_handle_syserr] /n/n/nError ON DEVICE !!!!/n/n/n
[ 92.751940855/ 0x8fdf8d9e] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 92.786792053/ 0x8fe9c372] [0x0 mhi_sm_handle_syserr] EXIT
[ 92.791669657/ 0x8feb3146] [0x0 mhi_sm_pcie_event_manager] Failed switching to SYSERR state
[ 92.791677261/ 0x8feb31d4] [0x0 mhi_sm_pcie_event_manager] EXIT
[ 92.870820022/ 0x900261aa] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 92.990825126/ 0x90258a0e] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 93.110825231/ 0x9048b20f] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 93.230818512/ 0x906bd994] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 93.350180284/ 0x908ed1a8] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 93.470322003/ 0x90b20456] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 93.590870805/ 0x90d5557d] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 93.710837941/ 0x90f87b07] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 93.830826223/ 0x911ba223] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 93.950838410/ 0x913ecb0f] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 94.070830963/ 0x9161f27e] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 94.190191328/ 0x9184ea7e] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 94.310755599/ 0x91a83ccd] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 94.430206901/ 0x91cb3bb2] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 94.550179454/ 0x91ee6199] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 94.670265861/ 0x9211901c] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 94.790823621/ 0x9234e1ef] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 94.910829924/ 0x92580a6b] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 95.030840080/ 0x927b3334] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 95.150829612/ 0x929e5a67] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 95.270832946/ 0x92c182a2] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 95.390827529/ 0x92e4aa3c] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 95.510831124/ 0x9307d284] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 95.630038520/ 0x932abf11] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 95.750179458/ 0x934df198] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 95.870026750/ 0x93710e26] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 95.990754250/ 0x93946cb3] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 96.110840084/ 0x93b79b2e] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 96.230838261/ 0x93dac30a] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 96.350836334/ 0x93fdeae4] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 96.470839929/ 0x9421132a] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 96.590833731/ 0x94443ab3] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 96.710833211/ 0x946762a9] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 96.830297273/ 0x948a6279] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 96.950828680/ 0x94adb250] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 97.070039149/ 0x94d09f1d] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 97.190186597/ 0x94f3d221] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 97.310839671/ 0x95172b24] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 97.430835661/ 0x953a52d7] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 97.550837692/ 0x955d7afd] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 97.670860141/ 0x9580a4ad] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 97.790873422/ 0x95a3cdaa] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 97.910826495/ 0x95c6f227] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 98.030832433/ 0x95ea1a9a] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 98.150208007/ 0x960d13c6] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 98.270839934/ 0x96306b29] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 98.390835872/ 0x965392dd] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 98.510834622/ 0x9676bac2] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 98.630840404/ 0x9699e333] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 98.750835092/ 0x96bd0acd] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 98.870196134/ 0x96e002d8] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 98.990837020/ 0x97035af1] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 99.110826343/ 0x97268225] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 99.230826291/ 0x9749aa25] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 99.350039469/ 0x976c9723] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 99.470839261/ 0x978ffb1e] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 99.590839157/ 0x97b3231b] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 99.710863272/ 0x97d64cec] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 99.830871033/ 0x97f97581] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 99.950840147/ 0x981c9b30] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 100.070832283/ 0x983fc296] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 100.190042857/ 0x9862af5c] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 100.310825617/ 0x98861217] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 100.430833378/ 0x98a93aad] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 100.550049628/ 0x98cc27e4] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 100.670830983/ 0x98ef8a7e] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 100.790826713/ 0x9912b22c] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 100.910190202/ 0x9935aa68] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 101.030837495/ 0x995902fb] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 101.150838589/ 0x997c2b0f] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 101.270825308/ 0x999f5210] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 101.390821402/ 0x99c279c5] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 101.510821402/ 0x99e5a1c7] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 101.630832080/ 0x9a08ca92] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 101.750832080/ 0x9a2bf294] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 101.870193174/ 0x9a4eeaa1] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 101.990752185/ 0x9a723c8a] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 102.110837550/ 0x9a956afb] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 102.230833488/ 0x9ab892ad] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 102.350844634/ 0x9adbbb85] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 102.470830989/ 0x9afee27e] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 102.590824322/ 0x9b2209fd] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 102.710821250/ 0x9b4531c3] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 102.830839219/ 0x9b685b1c] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 102.950837813/ 0x9b8b8301] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 103.070839845/ 0x9baeab29] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 103.190188282/ 0x9bd1a247] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 103.310834585/ 0x9bf4fac5] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 103.430828491/ 0x9c18224f] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 103.550826148/ 0x9c3b4a22] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 103.670829325/ 0x9c5e725e] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 103.790816774/ 0x9c81996d] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 103.910826982/ 0x9ca4c232] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 104.030839170/ 0x9cc7eb1b] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 104.150838337/ 0x9ceb130a] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 104.270839900/ 0x9d0e3b29] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 104.390842505/ 0x9d31635a] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 104.510842193/ 0x9d548b55] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 104.630839276/ 0x9d77b31c] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 104.750839954/ 0x9d9adb2b] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 104.870204069/ 0x9dbdd376] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 104.990825111/ 0x9de12a0c] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 105.110824903/ 0x9e045208] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 105.230834695/ 0x9e277ac5] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 105.350836362/ 0x9e4aa2e4] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 105.470844383/ 0x9e6dcb7e] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 105.590842925/ 0x9e90f364] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 105.710837457/ 0x9eb41afb] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 105.830833030/ 0x9ed742a5] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 105.950870582/ 0x9efa6d75] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 106.070816104/ 0x9f1d915f] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 106.190217771/ 0x9f408c79] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 106.310813240/ 0x9f63e12a] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 106.430838292/ 0x9f870b09] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 106.550839855/ 0x9faa3327] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 106.670839647/ 0x9fcd5b23] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 106.790828085/ 0x9ff08245] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 106.910189544/ 0xa0137a5c] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 107.030838398/ 0xa036d30c] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 107.150837878/ 0xa059fb02] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 107.270821784/ 0xa07d21ce] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 107.390828920/ 0xa0a04a57] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 107.510828087/ 0xa0c37248] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 107.630831733/ 0xa0e69a8d] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 107.750835536/ 0xa109c2d6] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 107.870177099/ 0xa12cb96c] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 107.990878662/ 0xa150160f] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 108.110832620/ 0xa1733a9e] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 108.230819964/ 0xa19661a9] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 108.350838038/ 0xa1b98b04] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 108.470180017/ 0xa1dc81a2] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 108.590817570/ 0xa1ffd97d] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 108.710819028/ 0xa2230198] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 108.830817883/ 0xa2462981] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 108.950837519/ 0xa26952fb] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 109.070872467/ 0xa28c7d97] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 109.190336530/ 0xa2af7d67] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 109.310831478/ 0xa2d2ca87] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 109.430838614/ 0xa2f5f311] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 109.550840073/ 0xa3191b2d] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 109.670030906/ 0xa33c0674] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 109.790816636/ 0xa35f696a] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 109.910813615/ 0xa3829130] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 110.030838928/ 0xa3a5bb16] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 110.150871689/ 0xa3c8e58a] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 110.270840700/ 0xa3ec0b38] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 110.390832784/ 0xa40f32a0] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 110.510840023/ 0xa4325b2d] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 110.630833826/ 0xa45582b4] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 110.750837212/ 0xa478aaf5] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 110.870018670/ 0xa49b9591] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 110.990816535/ 0xa4bef968] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 111.110179869/ 0xa4e1f1a2] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 111.230824974/ 0xa5054a0a] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 111.350840443/ 0xa5287333] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 111.470836485/ 0xa54b9ae7] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 111.590833985/ 0xa56ec2b6] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x0, reset:0
[ 111.710834142/ 0xa591eabc] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x2, reset:1
[ 111.710864142/ 0xa591ece1] [0x0 mhi_dev_enable] Cleared reset while waiting for M0
[ 111.830835965/ 0xa5b512dd] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x200, reset:0
[ 111.830866017/ 0xa5b51506] [0x0 mhi_dev_enable] state:2
[ 111.830885340/ 0xa5b51675] [0x0 mhi_dev_cache_host_cfg] Number of Event rings : 4, HW Event rings : 2
[ 111.830902944/ 0xa5b517ca] [0x0 mhi_dev_ring_init] initializing all rings
[ 111.830935236/ 0xa5b51a34] [0x0 mhi_dev_read_from_host_ipa] device 0xb08fa0b48b9d5000 <<-- host 0x10009a1f000, size 44
[ 111.831186225/ 0xa5b52d14] [0x0 mhi_dev_read_from_host_ipa] device 0xb084d9308b9d6000 <<-- host 0x10009a28000, size 176
[ 111.831259142/ 0xa5b53283] [0x0 mhi_dev_cache_host_cfg] cmd ring_base:0x997c000, rp:0x997c000, wp:0x997c000
[ 111.831276746/ 0xa5b533d1] [0x0 mhi_dev_cache_host_cfg] ev ring_base:0x9a29000, rp:0x9a29000, wp:0x9a297f0
[ 111.831294142/ 0xa5b5351f] [0x0 mhi_dev_cache_ring] nothing to cache for ring_id:0, local wr_ofst 0
[ 111.831305340/ 0xa5b535f5] [0x0 mhi_dev_cache_ring] new wr_offset 0
[ 111.831314194/ 0xa5b5369f] [0x0 mhi_ring_start] ctx ring_base:0x997c000, rp:0x997c000, wp:0x997c000
[ 111.831519246/ 0xa5b54600] [0x0 mhi_pcie_config_db_routing] Event rings 0x4 => er_base 0x2, er_end 3
[ 111.831554715/ 0xa5b548a9] [0x0 mhi_hwc_init] Event rings 0x4 => er_base 0x2, er_end 3
[ 111.831566902/ 0xa5b54994] [0x0 mhi_hwc_init] MMIO Addr 0x1c03000, MSI config: U:0x0 L: 0xfee30040 D: 0x0
[ 111.848506538/ 0xa5ba400b] [0x0 mhi_dev_isr] mhi irq triggered
[ 111.848554350/ 0xa5ba439e] [0x0 mhi_hwc_cb] HW ch uC is ready event=0x0
[ 111.848639871/ 0xa5ba4a08] [0x0 mhi_enable_int] Enable ctrl and cmdb interrupts
[ 111.848647371/ 0xa5ba4a98] [0x0 mhi_hwc_cb] Device in M0 State
[ 111.848669663/ 0xa5ba4c48] [0x0 mhi_dev_scheduler] processing ctrl interrupt with 5
[ 111.848676538/ 0xa5ba4cc8] [0x0 mhi_dev_scheduler] BHI_IMGTXDB = 0x0
[ 111.848682423/ 0xa5ba4d39] [0x0 mhi_dev_mmio_get_mhi_state] MHICTRL is 0x200, reset:0
[ 111.848726069/ 0xa5ba5081] [0x0 mhi_dev_notify_sm_event] ENTRY
[ 111.857471330/ 0xa5bce070] [0x0 mhi_dev_notify_sm_event] received: MHI_DEV_EVENT_M0_STATE
[ 111.857502059/ 0xa5bce2b6] [0x0 mhi_dev_notify_sm_event] Got M0, wait until resume is done
[ 111.857515705/ 0xa5bce3b9] [0x0 mhi_sm_dev_event_manager] ENTRY
[ 111.857871694/ 0xa5bcfe6f] [0x0 mhi_sm_dev_event_manager] Handling MHI_DEV_EVENT_M0_STATE event, current states: SYSTEM ERROR & D3_COLD_STATE
[ 111.857887996/ 0xa5bcffa5] [0x0 mhi_sm_dev_event_manager] syserr occurred, Ignoring MHI_DEV_EVENT_M0_STATE
[ 111.857895028/ 0xa5bd002b] [0x0 mhi_sm_dev_event_manager] EXIT
[ 111.857952684/ 0xa5bd0482] [0x0 mhi_dev_notify_sm_event] EXIT
~ # \r~ # cat /sys/kernel/debug/ipc_logging/mhi/log^[[J\r~ # ^[[Jcat /sys/kernel/debug/ipc_logging/mhi-uci/log
[ 0.190727448/ 0x46c2eae] [mhi_uci_init] Setting up [ 382.753559] debug_log: buffer size 992 < 1020
[ 382.757713] debug_log: buffer size 992 < 1020
channel attributes.
[ 0.190771302/ 0x46c31e9] [mhi_uci_init] Initializing clients
[ 0.190773906/ 0x46c321a] [mhi_uci_init] Registering for MHI events.
[ 0.190776093/ 0x46c3241] [mhi_register_client] Registering ch_id:1.
[ 0.190780625/ 0x46c3298] [mhi_register_client] Registering ch_id:3.
[ 0.190781875/ 0x46c32b0] [mhi_register_client] Registering ch_id:5.
[ 0.190783281/ 0x46c32cb] [mhi_register_client] Registering ch_id:11.
[ 0.190785625/ 0x46c32f8] [mhi_register_client] Registering ch_id:13.
[ 0.190786823/ 0x46c330f] [mhi_register_client] Registering ch_id:15.
[ 0.190788020/ 0x46c3325] [mhi_register_client] Registering ch_id:17.
[ 0.190789166/ 0x46c333c] [mhi_register_client] Registering ch_id:19.
[ 0.190790312/ 0x46c3352] [mhi_register_client] Registering ch_id:21.
[ 0.190792395/ 0x46c3379] [mhi_register_client] Registering ch_id:33.
[ 0.190793593/ 0x46c3391] [mhi_register_client] Registering ch_id:37.
[ 0.190795625/ 0x46c33b8] [mhi_uci_init] Allocating char devices.
[ 0.190800416/ 0x46c3414] [mhi_uci_init] Creating class
[ 0.190863593/ 0x46c38d4] [mhi_uci_init] Setting up device nodes.
[ 0.191059166/ 0x46c477d] [uci_device_create] Created device with class 0x(ptrval) and ctrl number 262144001
[ 0.191173385/ 0x46c500e] [uci_device_create] Created device with class 0x(ptrval) and ctrl number 262144002
[ 0.191272239/ 0x46c5778] [uci_device_create] Created device with class 0x(ptrval) and ctrl number 262144005
[ 0.191355833/ 0x46c5dbd] [uci_device_create] Created device with class 0x(ptrval) and ctrl number 262144006
[ 0.191417395/ 0x46c625b] [uci_device_create] Created device with class 0x(ptrval) and ctrl number 262144007
[ 0.191496614/ 0x46c684c] [uci_device_create] Created device with class 0x(ptrval) and ctrl number 262144008
[ 17.115751770/ 0x17caaf6d] [mhi_uci_chan_state_notify] Invalid ch_id:100
[ 17.145486978/ 0x17d36592] [mhi_uci_chan_state_notify] Invalid ch_id:101
[ 22.474006474/ 0x1dec7c88] [mhi_state_uevent] Calling notify for ch_id:12
[ 22.474011734/ 0x1dec7cec] [mhi_state_uevent] Calling notify for ch_id:13
[ 22.474015849/ 0x1dec7d3b] [mhi_state_uevent] Calling notify for ch_id:4
[ 22.474019547/ 0x1dec7d82] [mhi_state_uevent] Calling notify for ch_id:5
[ 22.474023349/ 0x1dec7dcb] [mhi_state_uevent] Calling notify for ch_id:14
[ 22.474027307/ 0x1dec7e17] [mhi_state_uevent] Calling notify for ch_id:15
[ 22.474031266/ 0x1dec7e63] [mhi_state_uevent] Calling notify for ch_id:20
[ 22.474035328/ 0x1dec7eb1] [mhi_state_uevent] Calling notify for ch_id:21
[ 22.474039443/ 0x1dec7f00] [mhi_state_uevent] Calling notify for ch_id:32
[ 22.474043401/ 0x1dec7f4c] [mhi_state_uevent] Calling notify for ch_id:33
[ 22.474047359/ 0x1dec7f98] [mhi_state_uevent] Calling notify for ch_id:36
[ 22.474051161/ 0x1dec7fe1] [mhi_state_uevent] Calling notify for ch_id:37
[ 31.785487856/ 0x289475a1] [mhi_state_uevent] Calling notify for ch_id:12
[ 31.785492804/ 0x28947600] [mhi_state_uevent] Calling notify for ch_id:13
[ 31.785496919/ 0x2894764f] [mhi_state_uevent] Calling notify for ch_id:4
[ 31.785500773/ 0x28947699] [mhi_state_uevent] Calling notify for ch_id:5
[ 31.785504784/ 0x289476e6] [mhi_state_uevent] Calling notify for ch_id:14
[ 31.785508690/ 0x28947731] [mhi_state_uevent] Calling notify for ch_id:15
[ 31.785512492/ 0x2894777a] [mhi_state_uevent] Calling notify for ch_id:20
[ 31.785516190/ 0x289477c1] [mhi_state_uevent] Calling notify for ch_id:21
[ 31.785520200/ 0x2894780e] [mhi_state_uevent] Calling notify for ch_id:32
[ 31.785524106/ 0x28947859] [mhi_state_uevent] Calling notify for ch_id:33
[ 31.785528013/ 0x289478a3] [mhi_state_uevent] Calling notify for ch_id:36
[ 31.785531711/ 0x289478eb] [mhi_state_uevent] Calling notify for ch_id:37
[ 31.785993950/ 0x28949b98] [mhi_state_uevent] Calling notify for ch_id:12
[ 31.785998482/ 0x28949bed] [mhi_state_uevent] Calling notify for ch_id:13
[ 31.786002492/ 0x28949c39] [mhi_state_uevent] Calling notify for ch_id:4
[ 31.786006190/ 0x28949c81] [mhi_state_uevent] Calling notify for ch_id:5
[ 31.786009888/ 0x28949cc8] [mhi_state_uevent] Calling notify for ch_id:14
[ 31.786013742/ 0x28949d12] [mhi_state_uevent] Calling notify for ch_id:15
[ 31.786017544/ 0x28949d5b] [mhi_state_uevent] Calling notify for ch_id:20
[ 31.786021398/ 0x28949da5] [mhi_state_uevent] Calling notify for ch_id:21
[ 31.786025200/ 0x28949dee] [mhi_state_uevent] Calling notify for ch_id:32
[ 31.786029107/ 0x28949e39] [mhi_state_uevent] Calling notify for ch_id:33
[ 31.786032857/ 0x28949e81] [mhi_state_uevent] Calling notify for ch_id:36
[ 31.786036659/ 0x28949eca] [mhi_state_uevent] Calling notify for ch_id:37
[ 31.786512804/ 0x2894c281] [mhi_state_uevent] Calling notify for ch_id:12
[ 31.786517596/ 0x2894c2dc] [mhi_state_uevent] Calling notify for ch_id:13
[ 31.786521711/ 0x2894c32b] [mhi_state_uevent] Calling notify for ch_id:4
[ 31.786525461/ 0x2894c373] [mhi_state_uevent] Calling notify for ch_id:5
[ 31.786529107/ 0x2894c3b9] [mhi_state_uevent] Calling notify for ch_id:14
[ 31.786532961/ 0x2894c402] [mhi_state_uevent] Calling notify for ch_id:15
[ 31.786536815/ 0x2894c44d] [mhi_state_uevent] Calling notify for ch_id:20
[ 31.786540721/ 0x2894c498] [mhi_state_uevent] Calling notify for ch_id:21
[ 31.786544627/ 0x2894c4e3] [mhi_state_uevent] Calling notify for ch_id:32
[ 31.786548534/ 0x2894c52e] [mhi_state_uevent] Calling notify for ch_id:33
[ 31.786552440/ 0x2894c579] [mhi_state_uevent] Calling notify for ch_id:36
[ 31.786556242/ 0x2894c5c1] [mhi_state_uevent] Calling notify for ch_id:37
[ 31.787013169/ 0x2894e80a] [mhi_state_uevent] Calling notify for ch_id:12
[ 31.787017648/ 0x2894e85d] [mhi_state_uevent] Calling notify for ch_id:13
[ 31.787021554/ 0x2894e8a7] [mhi_state_uevent] Calling notify for ch_id:4
[ 31.787025461/ 0x2894e8f3] [mhi_state_uevent] Calling notify for ch_id:5
[ 31.787029263/ 0x2894e93c] [mhi_state_uevent] Calling notify for ch_id:14
[ 31.787033117/ 0x2894e986] [mhi_state_uevent] Calling notify for ch_id:15
[ 31.787036919/ 0x2894e9cf] [mhi_state_uevent] Calling notify for ch_id:20
[ 31.787040721/ 0x2894ea18] [mhi_state_uevent] Calling notify for ch_id:21
[ 31.787044523/ 0x2894ea61] [mhi_state_uevent] Calling notify for ch_id:32
[ 31.787048325/ 0x2894eaa9] [mhi_state_uevent] Calling notify for ch_id:33
[ 31.787052075/ 0x2894eaf2] [mhi_state_uevent] Calling notify for ch_id:36
[ 31.787055825/ 0x2894eb3a] [mhi_state_uevent] Calling notify for ch_id:37
[ 31.787514627/ 0x28950da4] [mhi_state_uevent] Calling notify for ch_id:12
[ 31.787519315/ 0x28950dfd] [mhi_state_uevent] Calling notify for ch_id:13
[ 31.787523169/ 0x28950e47] [mhi_state_uevent] Calling notify for ch_id:4
[ 31.787526919/ 0x28950e8f] [mhi_state_uevent] Calling notify for ch_id:5
[ 31.787530669/ 0x28950ed7] [mhi_state_uevent] Calling notify for ch_id:14
[ 31.787534471/ 0x28950f20] [mhi_state_uevent] Calling notify for ch_id:15
[ 31.787538325/ 0x28950f6a] [mhi_state_uevent] Calling notify for ch_id:20
[ 31.787542075/ 0x28950fb2] [mhi_state_uevent] Calling notify for ch_id:21
[ 31.787545825/ 0x28950ffa] [mhi_state_uevent] Calling notify for ch_id:32
[ 31.787549575/ 0x28951042] [mhi_state_uevent] Calling notify for ch_id:33
[ 31.787553377/ 0x2895108b] [mhi_state_uevent] Calling notify for ch_id:36
[ 31.787557127/ 0x289510d3] [mhi_state_uevent] Calling notify for ch_id:37
[ 31.788015565/ 0x28953335] [mhi_state_uevent] Calling notify for ch_id:12
[ 31.788019888/ 0x28953388] [mhi_state_uevent] Calling notify for ch_id:13
[ 31.788023794/ 0x289533d3] [mhi_state_uevent] Calling notify for ch_id:4
[ 31.788027492/ 0x2895341a] [mhi_state_uevent] Calling notify for ch_id:5
[ 31.788031294/ 0x28953463] [mhi_state_uevent] Calling notify for ch_id:14
[ 31.788035200/ 0x289534ae] [mhi_state_uevent] Calling notify for ch_id:15
[ 31.788039211/ 0x289534fb] [mhi_state_uevent] Calling notify for ch_id:20
[ 31.788043117/ 0x28953546] [mhi_state_uevent] Calling notify for ch_id:21
[ 31.788046919/ 0x2895358f] [mhi_state_uevent] Calling notify for ch_id:32
[ 31.788050721/ 0x289535d8] [mhi_state_uevent] Calling notify for ch_id:33
[ 31.788054523/ 0x28953621] [mhi_state_uevent] Calling notify for ch_id:36
[ 31.788058325/ 0x2895366a] [mhi_state_uevent] Calling notify for ch_id:37
[ 31.788522492/ 0x2895593a] [mhi_state_uevent] Calling notify for ch_id:12
[ 31.788526867/ 0x2895598e] [mhi_state_uevent] Calling notify for ch_id:13
[ 31.788530721/ 0x289559d8] [mhi_state_uevent] Calling notify for ch_id:4
[ 31.788534575/ 0x28955a22] [mhi_state_uevent] Calling notify for ch_id:5
[ 31.788538221/ 0x28955a68] [mhi_state_uevent] Calling notify for ch_id:14
[ 31.788542075/ 0x28955ab2] [mhi_state_uevent] Calling notify for ch_id:15
[ 31.788545929/ 0x28955afc] [mhi_state_uevent] Calling notify for ch_id:20
[ 31.788549732/ 0x28955b45] [mhi_state_uevent] Calling notify for ch_id:21
[ 31.788553690/ 0x28955b90] [mhi_state_uevent] Calling notify for ch_id:32
[ 31.788557596/ 0x28955bdc] [mhi_state_uevent] Calling notify for ch_id:33
[ 31.788561450/ 0x28955c26] [mhi_state_uevent] Calling notify for ch_id:36
[ 31.788565252/ 0x28955c6f] [mhi_state_uevent] Calling notify for ch_id:37
[ 33.616269268/ 0x2aacd23c] [mhi_state_uevent] Calling notify for ch_id:12
[ 33.616274477/ 0x2aacd2a0] [mhi_state_uevent] Calling notify for ch_id:13
[ 33.616278643/ 0x2aacd2f0] [mhi_state_uevent] Calling notify for ch_id:4
[ 33.616282393/ 0x2aacd338] [mhi_state_uevent] Calling notify for ch_id:5
[ 33.616286508/ 0x2aacd387] [mhi_state_uevent] Calling notify for ch_id:14
[ 33.616290414/ 0x2aacd3d2] [mhi_state_uevent] Calling notify for ch_id:15
[ 33.616294373/ 0x2aacd41e] [mhi_state_uevent] Calling notify for ch_id:20
[ 33.616298279/ 0x2aacd469] [mhi_state_uevent] Calling notify for ch_id:21
[ 33.616302341/ 0x2aacd4b7] [mhi_state_uevent] Calling notify for ch_id:32
[ 33.616306195/ 0x2aacd501] [mhi_state_uevent] Calling notify for ch_id:33
[ 33.616310102/ 0x2aacd54c] [mhi_state_uevent] Calling notify for ch_id:36
[ 33.616313852/ 0x2aacd594] [mhi_state_uevent] Calling notify for ch_id:37
[ 33.616441456/ 0x2aacdf2b] [mhi_state_uevent] Calling notify for ch_id:12
[ 33.616446091/ 0x2aacdf7f] [mhi_state_uevent] Calling notify for ch_id:13
[ 33.616449945/ 0x2aacdfc9] [mhi_state_uevent] Calling notify for ch_id:4
[ 33.616453643/ 0x2aace010] [mhi_state_uevent] Calling notify for ch_id:5
[ 33.616457341/ 0x2aace057] [mhi_state_uevent] Calling notify for ch_id:14
[ 33.616461456/ 0x2aace0a5] [mhi_state_uevent] Calling notify for ch_id:15
[ 33.616465258/ 0x2aace0ef] [mhi_state_uevent] Calling notify for ch_id:20
[ 33.616469008/ 0x2aace137] [mhi_state_uevent] Calling notify for ch_id:21
[ 33.616472810/ 0x2aace180] [mhi_state_uevent] Calling notify for ch_id:32
[ 33.616476612/ 0x2aace1c9] [mhi_state_uevent] Calling notify for ch_id:33
[ 33.616480466/ 0x2aace213] [mhi_state_uevent] Calling notify for ch_id:36
[ 33.616484268/ 0x2aace25c] [mhi_state_uevent] Calling notify for ch_id:37
[ 33.616592498/ 0x2aacea7a] [mhi_state_uevent] Calling notify for ch_id:12
[ 33.616596664/ 0x2aaceaca] [mhi_state_uevent] Calling notify for ch_id:13
[ 33.616600518/ 0x2aaceb14] [mhi_state_uevent] Calling notify for ch_id:4
[ 33.616604268/ 0x2aaceb5c] [mhi_state_uevent] Calling notify for ch_id:5
[ 33.616607914/ 0x2aaceba2] [mhi_state_uevent] Calling notify for ch_id:14
[ 33.616611768/ 0x2aacebec] [mhi_state_uevent] Calling notify for ch_id:15
[ 33.616615623/ 0x2aacec35] [mhi_state_uevent] Calling notify for ch_id:20
[ 33.616619477/ 0x2aacec80] [mhi_state_uevent] Calling notify for ch_id:21
[ 33.616623279/ 0x2aacecc9] [mhi_state_uevent] Calling notify for ch_id:32
[ 33.616627133/ 0x2aaced13] [mhi_state_uevent] Calling notify for ch_id:33
[ 33.616630935/ 0x2aaced5c] [mhi_state_uevent] Calling notify for ch_id:36
[ 33.616634737/ 0x2aaceda5] [mhi_state_uevent] Calling notify for ch_id:37
[ 33.616738331/ 0x2aacf56a] [mhi_state_uevent] Calling notify for ch_id:12
[ 33.616742602/ 0x2aacf5bc] [mhi_state_uevent] Calling notify for ch_id:13
[ 33.616746456/ 0x2aacf606] [mhi_state_uevent] Calling notify for ch_id:4
[ 33.616750206/ 0x2aacf64e] [mhi_state_uevent] Calling notify for ch_id:5
[ 33.616753852/ 0x2aacf694] [mhi_state_uevent] Calling notify for ch_id:14
[ 33.616757706/ 0x2aacf6de] [mhi_state_uevent] Calling notify for ch_id:15
[ 33.616761508/ 0x2aacf727] [mhi_state_uevent] Calling notify for ch_id:20
[ 33.616765310/ 0x2aacf770] [mhi_state_uevent] Calling notify for ch_id:21
[ 33.616769060/ 0x2aacf7b8] [mhi_state_uevent] Calling notify for ch_id:32
[ 33.616772862/ 0x2aacf801] [mhi_state_uevent] Calling notify for ch_id:33
[ 33.616776664/ 0x2aacf84a] [mhi_state_uevent] Calling notify for ch_id:36
[ 33.616780466/ 0x2aacf893] [mhi_state_uevent] Calling notify for ch_id:37
[ 33.616881352/ 0x2aad0024] [mhi_state_uevent] Calling notify for ch_id:12
[ 33.616885623/ 0x2aad0076] [mhi_state_uevent] Calling notify for ch_id:13
[ 33.616889529/ 0x2aad00c1] [mhi_state_uevent] Calling notify for ch_id:4
[ 33.616893279/ 0x2aad0109] [mhi_state_uevent] Calling notify for ch_id:5
[ 33.616896977/ 0x2aad0150] [mhi_state_uevent] Calling notify for ch_id:14
[ 33.616900779/ 0x2aad0199] [mhi_state_uevent] Calling notify for ch_id:15
[ 33.616904633/ 0x2aad01e3] [mhi_state_uevent] Calling notify for ch_id:20
[ 33.616908383/ 0x2aad022b] [mhi_state_uevent] Calling notify for ch_id:21
[ 33.616912289/ 0x2aad0276] [mhi_state_uevent] Calling notify for ch_id:32
[ 33.616916143/ 0x2aad02c0] [mhi_state_uevent] Calling notify for ch_id:33
[ 33.616919945/ 0x2aad0309] [mhi_state_uevent] Calling notify for ch_id:36
[ 33.616923852/ 0x2aad0354] [mhi_state_uevent] Calling notify for ch_id:37
[ 33.617034477/ 0x2aad0ba0] [mhi_state_uevent] Calling notify for ch_id:12
[ 33.617038539/ 0x2aad0bee] [mhi_state_uevent] Calling notify for ch_id:13
[ 33.617042341/ 0x2aad0c37] [mhi_state_uevent] Calling notify for ch_id:4
[ 33.617046195/ 0x2aad0c81] [mhi_state_uevent] Calling notify for ch_id:5
[ 33.617049893/ 0x2aad0cc7] [mhi_state_uevent] Calling notify for ch_id:14
[ 33.617053748/ 0x2aad0d12] [mhi_state_uevent] Calling notify for ch_id:15
[ 33.617057602/ 0x2aad0d5c] [mhi_state_uevent] Calling notify for ch_id:20
[ 33.617061508/ 0x2aad0da7] [mhi_state_uevent] Calling notify for ch_id:21
[ 33.617065310/ 0x2aad0df0] [mhi_state_uevent] Calling notify for ch_id:32
[ 33.617069112/ 0x2aad0e39] [mhi_state_uevent] Calling notify for ch_id:33
[ 33.617072914/ 0x2aad0e81] [mhi_state_uevent] Calling notify for ch_id:36
[ 33.617076664/ 0x2aad0ec9] [mhi_state_uevent] Calling notify for ch_id:37
[ 33.617182602/ 0x2aad16bc] [mhi_state_uevent] Calling notify for ch_id:12
[ 33.617186820/ 0x2aad170d] [mhi_state_uevent] Calling notify for ch_id:13
[ 33.617190675/ 0x2aad1756] [mhi_state_uevent] Calling notify for ch_id:4
[ 33.617194373/ 0x2aad179e] [mhi_state_uevent] Calling notify for ch_id:5
[ 33.617198070/ 0x2aad17e4] [mhi_state_uevent] Calling notify for ch_id:14
[ 33.617201873/ 0x2aad182e] [mhi_state_uevent] Calling notify for ch_id:15
[ 33.617205727/ 0x2aad1878] [mhi_state_uevent] Calling notify for ch_id:20
[ 33.617209529/ 0x2aad18c1] [mhi_state_uevent] Calling notify for ch_id:21
[ 33.617213383/ 0x2aad190b] [mhi_state_uevent] Calling notify for ch_id:32
[ 33.617217133/ 0x2aad1953] [mhi_state_uevent] Calling notify for ch_id:33
[ 33.617220987/ 0x2aad199c] [mhi_state_uevent] Calling notify for ch_id:36
[ 33.617224737/ 0x2aad19e5] [mhi_state_uevent] Calling notify for ch_id:37
[ 36.410853548/ 0x2ddf8c0f] [mhi_state_uevent] Calling notify for ch_id:12
[ 36.410858600/ 0x2ddf8c6f] [mhi_state_uevent] Calling notify for ch_id:13
[ 36.410862871/ 0x2ddf8cc1] [mhi_state_uevent] Calling notify for ch_id:4
[ 36.410866569/ 0x2ddf8d08] [mhi_state_uevent] Calling notify for ch_id:5
[ 36.410870371/ 0x2ddf8d51] [mhi_state_uevent] Calling notify for ch_id:14
[ 36.410874329/ 0x2ddf8d9d] [mhi_state_uevent] Calling notify for ch_id:15
[ 36.410878183/ 0x2ddf8de7] [mhi_state_uevent] Calling notify for ch_id:20
[ 36.410882037/ 0x2ddf8e31] [mhi_state_uevent] Calling notify for ch_id:21
[ 36.410886048/ 0x2ddf8e7e] [mhi_state_uevent] Calling notify for ch_id:32
[ 36.410889954/ 0x2ddf8ec9] [mhi_state_uevent] Calling notify for ch_id:33
[ 36.410893860/ 0x2ddf8f14] [mhi_state_uevent] Calling notify for ch_id:36
[ 36.410897662/ 0x2ddf8f5c] [mhi_state_uevent] Calling notify for ch_id:37
[ 36.413949381/ 0x2de07442] [mhi_state_uevent] Calling notify for ch_id:12
[ 36.413954902/ 0x2de074a8] [mhi_state_uevent] Calling notify for ch_id:13
[ 36.413959173/ 0x2de074fa] [mhi_state_uevent] Calling notify for ch_id:4
[ 36.413962923/ 0x2de07541] [mhi_state_uevent] Calling notify for ch_id:5
[ 36.413966725/ 0x2de0758b] [mhi_state_uevent] Calling notify for ch_id:14
[ 36.413970787/ 0x2de075d8] [mhi_state_uevent] Calling notify for ch_id:15
[ 36.413974537/ 0x2de07621] [mhi_state_uevent] Calling notify for ch_id:20
[ 36.413978287/ 0x2de07669] [mhi_state_uevent] Calling notify for ch_id:21
[ 36.413982298/ 0x2de076b6] [mhi_state_uevent] Calling notify for ch_id:32
[ 36.413986308/ 0x2de07703] [mhi_state_uevent] Calling notify for ch_id:33
[ 36.413990162/ 0x2de0774d] [mhi_state_uevent] Calling notify for ch_id:36
[ 36.413993860/ 0x2de07794] [mhi_state_uevent] Calling notify for ch_id:37
[ 36.416858756/ 0x2de14e72] [mhi_state_uevent] Calling notify for ch_id:12
[ 36.416864016/ 0x2de14ed7] [mhi_state_uevent] Calling notify for ch_id:13
[ 36.416868183/ 0x2de14f27] [mhi_state_uevent] Calling notify for ch_id:4
[ 36.416872454/ 0x2de14f79] [mhi_state_uevent] Calling notify for ch_id:5
[ 36.416876256/ 0x2de14fc2] [mhi_state_uevent] Calling notify for ch_id:14
[ 36.416880371/ 0x2de15011] [mhi_state_uevent] Calling notify for ch_id:15
[ 36.416884329/ 0x2de1505d] [mhi_state_uevent] Calling notify for ch_id:20
[ 36.416888183/ 0x2de150a7] [mhi_state_uevent] Calling notify for ch_id:21
[ 36.416892246/ 0x2de150f5] [mhi_state_uevent] Calling notify for ch_id:32
[ 36.416896152/ 0x2de15140] [mhi_state_uevent] Calling notify for ch_id:33
[ 36.416900058/ 0x2de1518b] [mhi_state_uevent] Calling notify for ch_id:36
[ 36.416903808/ 0x2de151d3] [mhi_state_uevent] Calling notify for ch_id:37
[ 36.419273444/ 0x2de2038c] [mhi_state_uevent] Calling notify for ch_id:12
[ 36.419278652/ 0x2de203f0] [mhi_state_uevent] Calling notify for ch_id:13
[ 36.419282766/ 0x2de2043e] [mhi_state_uevent] Calling notify for ch_id:4
[ 36.419286464/ 0x2de20486] [mhi_state_uevent] Calling notify for ch_id:5
[ 36.419290266/ 0x2de204cf] [mhi_state_uevent] Calling notify for ch_id:14
[ 36.419294225/ 0x2de2051b] [mhi_state_uevent] Calling notify for ch_id:15
[ 36.419298027/ 0x2de20564] [mhi_state_uevent] Calling notify for ch_id:20
[ 36.419301777/ 0x2de205ac] [mhi_state_uevent] Calling notify for ch_id:21
[ 36.419305891/ 0x2de205fa] [mhi_state_uevent] Calling notify for ch_id:32
[ 36.419309798/ 0x2de20645] [mhi_state_uevent] Calling notify for ch_id:33
[ 36.419313704/ 0x2de20690] [mhi_state_uevent] Calling notify for ch_id:36
[ 36.419317402/ 0x2de206d8] [mhi_state_uevent] Calling notify for ch_id:37
[ 36.428309850/ 0x2de4a947] [mhi_state_uevent] Calling notify for ch_id:12
[ 36.428315058/ 0x2de4a9ab] [mhi_state_uevent] Calling notify for ch_id:13
[ 36.428319329/ 0x2de4a9fc] [mhi_state_uevent] Calling notify for ch_id:4
[ 36.428323027/ 0x2de4aa44] [mhi_state_uevent] Calling notify for ch_id:5
[ 36.428326829/ 0x2de4aa8c] [mhi_state_uevent] Calling notify for ch_id:14
[ 36.428330735/ 0x2de4aad8] [mhi_state_uevent] Calling notify for ch_id:15
[ 36.428334589/ 0x2de4ab22] [mhi_state_uevent] Calling notify for ch_id:20
[ 36.428338339/ 0x2de4ab69] [mhi_state_uevent] Calling notify for ch_id:21
[ 36.428342350/ 0x2de4abb7] [mhi_state_uevent] Calling notify for ch_id:32
[ 36.428346256/ 0x2de4ac02] [mhi_state_uevent] Calling notify for ch_id:33
[ 36.428350162/ 0x2de4ac4d] [mhi_state_uevent] Calling notify for ch_id:36
[ 36.428353964/ 0x2de4ac96] [mhi_state_uevent] Calling notify for ch_id:37
[ 36.430763912/ 0x2de56158] [mhi_state_uevent] Calling notify for ch_id:12
[ 36.430769485/ 0x2de561c5] [mhi_state_uevent] Calling notify for ch_id:13
[ 36.430774017/ 0x2de56217] [mhi_state_uevent] Calling notify for ch_id:4
[ 36.430777923/ 0x2de56262] [mhi_state_uevent] Calling notify for ch_id:5
[ 36.430781725/ 0x2de562ab] [mhi_state_uevent] Calling notify for ch_id:14
[ 36.430785839/ 0x2de562fa] [mhi_state_uevent] Calling notify for ch_id:15
[ 36.430789798/ 0x2de56346] [mhi_state_uevent] Calling notify for ch_id:20
[ 36.430793652/ 0x2de56390] [mhi_state_uevent] Calling notify for ch_id:21
[ 36.430797662/ 0x2de563dd] [mhi_state_uevent] Calling notify for ch_id:32
[ 36.430801569/ 0x2de56428] [mhi_state_uevent] Calling notify for ch_id:33
[ 36.430805475/ 0x2de56473] [mhi_state_uevent] Calling notify for ch_id:36
[ 36.430809225/ 0x2de564bb] [mhi_state_uevent] Calling notify for ch_id:37
[ 36.434911412/ 0x2de69865] [mhi_state_uevent] Calling notify for ch_id:12
[ 36.434916517/ 0x2de698c8] [mhi_state_uevent] Calling notify for ch_id:13
[ 36.434920631/ 0x2de69916] [mhi_state_uevent] Calling notify for ch_id:4
[ 36.434924329/ 0x2de6995d] [mhi_state_uevent] Calling notify for ch_id:5
[ 36.434928131/ 0x2de699a6] [mhi_state_uevent] Calling notify for ch_id:14
[ 36.434932246/ 0x2de699f5] [mhi_state_uevent] Calling notify for ch_id:15
[ 36.434936360/ 0x2de69a44] [mhi_state_uevent] Calling notify for ch_id:20
[ 36.434940267/ 0x2de69a8f] [mhi_state_uevent] Calling notify for ch_id:21
[ 36.434944329/ 0x2de69add] [mhi_state_uevent] Calling notify for ch_id:32
[ 36.434948235/ 0x2de69b28] [mhi_state_uevent] Calling notify for ch_id:33
[ 36.434952194/ 0x2de69b74] [mhi_state_uevent] Calling notify for ch_id:36
[ 36.434956048/ 0x2de69bbd] [mhi_state_uevent] Calling notify for ch_id:37
[ 38.803283242/ 0x309c7448] [mhi_state_uevent] Calling notify for ch_id:12
[ 38.803288347/ 0x309c74aa] [mhi_state_uevent] Calling notify for ch_id:13
[ 38.803292722/ 0x309c74fd] [mhi_state_uevent] Calling notify for ch_id:4
[ 38.803296420/ 0x309c7545] [mhi_state_uevent] Calling notify for ch_id:5
[ 38.803300222/ 0x309c758e] [mhi_state_uevent] Calling notify for ch_id:14
[ 38.803304180/ 0x309c75da] [mhi_state_uevent] Calling notify for ch_id:15
[ 38.803308086/ 0x309c7625] [mhi_state_uevent] Calling notify for ch_id:20
[ 38.803311888/ 0x309c766e] [mhi_state_uevent] Calling notify for ch_id:21
[ 38.803315951/ 0x309c76bb] [mhi_state_uevent] Calling notify for ch_id:32
[ 38.803319857/ 0x309c7707] [mhi_state_uevent] Calling notify for ch_id:33
[ 38.803323763/ 0x309c7752] [mhi_state_uevent] Calling notify for ch_id:36
[ 38.803327565/ 0x309c779b] [mhi_state_uevent] Calling notify for ch_id:37
[ 39.930382829/ 0x31e6a8c0] [mhi_state_uevent] Calling notify for ch_id:12
[ 39.930388246/ 0x31e6a92b] [mhi_state_uevent] Calling notify for ch_id:13
[ 39.930392517/ 0x31e6a97a] [mhi_state_uevent] Calling notify for ch_id:4
[ 39.930396267/ 0x31e6a9c2] [mhi_state_uevent] Calling notify for ch_id:5
[ 39.930400069/ 0x31e6aa0b] [mhi_state_uevent] Calling notify for ch_id:14
[ 39.930404131/ 0x31e6aa59] [mhi_state_uevent] Calling notify for ch_id:15
[ 39.930408194/ 0x31e6aaa7] [mhi_state_uevent] Calling notify for ch_id:20
[ 39.930412100/ 0x31e6aaf2] [mhi_state_uevent] Calling notify for ch_id:21
[ 39.930416163/ 0x31e6ab3f] [mhi_state_uevent] Calling notify for ch_id:32
[ 39.930420017/ 0x31e6ab8a] [mhi_state_uevent] Calling notify for ch_id:33
[ 39.930423975/ 0x31e6abd6] [mhi_state_uevent] Calling notify for ch_id:36
[ 39.930427777/ 0x31e6ac1f] [mhi_state_uevent] Calling notify for ch_id:37
[ 40.264370174/ 0x324881dc] [mhi_uci_client_open] Client opened struct device node 0x7, ref count 0x0
[ 40.264378820/ 0x32488273] [mhi_uci_client_open] Opening channels client 7
[ 40.264386528/ 0x32488307] [mhi_uci_are_channels_connected] ch_id:14 or 15 are not connected
[ 40.264418664/ 0x32488570] [open_client_mhi_channels] Channels are not connected
[ 40.264420487/ 0x32488595] [mhi_uci_client_open] Failed to open channels ret -19
[ 40.264422205/ 0x324885b4] [mhi_uci_client_open] Closing failed channel
[ 41.264718406/ 0x336d93fd] [mhi_uci_client_open] Client opened struct device node 0x7, ref count 0x0
[ 41.264728719/ 0x336d94b6] [mhi_uci_client_open] Opening channels client 7
[ 41.264737625/ 0x336d955c] [mhi_uci_are_channels_connected] ch_id:14 or 15 are not connected
[ 41.264769240/ 0x336d97bd] [open_client_mhi_channels] Channels are not connected
[ 41.264771115/ 0x336d97e0] [mhi_uci_client_open] Failed to open channels ret -19
[ 41.264772885/ 0x336d9801] [mhi_uci_client_open] Closing failed channel
[ 42.264934086/ 0x34929c29] [mhi_uci_client_open] Client opened struct device node 0x7, ref count 0x0
[ 42.264945909/ 0x34929cfb] [mhi_uci_client_open] Opening channels client 7
[ 42.264954451/ 0x34929d9f] [mhi_uci_are_channels_connected] ch_id:14 or 15 are not connected
[ 42.264986118/ 0x34929fff] [open_client_mhi_channels] Channels are not connected
[ 42.264988045/ 0x3492a025] [mhi_uci_client_open] Failed to open channels ret -19
[ 42.264989607/ 0x3492a042] [mhi_uci_client_open] Closing failed channel
[ 43.265201225/ 0x35b7a827] [mhi_uci_client_open] Client opened struct device node 0x7, ref count 0x0
[ 43.265206850/ 0x35b7a88d] [mhi_uci_client_open] Opening channels client 7
[ 43.265214142/ 0x35b7a919] [mhi_uci_are_channels_connected] ch_id:14 or 15 are not connected
[ 43.265245964/ 0x35b7ab7c] [open_client_mhi_channels] Channels are not connected
[ 43.265248048/ 0x35b7aba5] [mhi_uci_client_open] Failed to open channels ret -19
[ 43.265249714/ 0x35b7abc4] [mhi_uci_client_open] Closing failed channel
[ 44.265413207/ 0x36dcb016] [mhi_uci_client_open] Client opened struct device node 0x7, ref count 0x0
[ 44.265421957/ 0x36dcb0af] [mhi_uci_client_open] Opening channels client 7
[ 44.265429822/ 0x36dcb146] [mhi_uci_are_channels_connected] ch_id:14 or 15 are not connected
[ 44.265966645/ 0x36dcd98a] [open_client_mhi_channels] Channels are not connected
[ 44.265968728/ 0x36dcd9b1] [mhi_uci_client_open] Failed to open channels ret -19
[ 44.265970499/ 0x36dcd9d3] [mhi_uci_client_open] Closing failed channel
[ 45.267009616/ 0x38021fe4] [mhi_uci_client_open] Client opened struct device node 0x7, ref count 0x0
[ 45.267036543/ 0x380221d7] [mhi_uci_client_open] Opening channels client 7
[ 45.267067689/ 0x38022425] [mhi_uci_are_channels_connected] ch_id:14 or 15 are not connected
[ 45.267129356/ 0x380228c9] [open_client_mhi_channels] Channels are not connected
[ 45.267136283/ 0x3802294c] [mhi_uci_client_open] Failed to open channels ret -19
[ 45.267143783/ 0x380229da] [mhi_uci_client_open] Closing failed channel
[ 46.267409880/ 0x392735e2] [mhi_uci_client_open] Client opened struct device node 0x7, ref count 0x0
[ 46.267435609/ 0x392737c2] [mhi_uci_client_open] Opening channels client 7
[ 46.267466286/ 0x39273a0a] [mhi_uci_are_channels_connected] ch_id:14 or 15 are not connected
[ 46.267527432/ 0x39273ea4] [open_client_mhi_channels] Channels are not connected
[ 46.267535088/ 0x39273f35] [mhi_uci_client_open] Failed to open channels ret -19
[ 46.267542588/ 0x39273fc3] [mhi_uci_client_open] Closing failed channel
[ 47.268612487/ 0x3a4c881c] [mhi_uci_client_open] Client opened struct device node 0x7, ref count 0x0
[ 47.268640404/ 0x3a4c8a25] [mhi_uci_client_open] Opening channels client 7
[ 47.268670977/ 0x3a4c8c64] [mhi_uci_are_channels_connected] ch_id:14 or 15 are not connected
[ 47.268732695/ 0x3a4c9109] [open_client_mhi_channels] Channels are not connected
[ 47.268739987/ 0x3a4c9193] [mhi_uci_client_open] Failed to open channels ret -19
[ 47.268747643/ 0x3a4c9223] [mhi_uci_client_open] Closing failed channel
[ 48.269816136/ 0x3b71da61] [mhi_uci_client_open] Client opened struct device node 0x7, ref count 0x0
[ 48.269843011/ 0x3b71dc56] [mhi_uci_client_open] Opening channels client 7
[ 48.269873532/ 0x3b71de96] [mhi_uci_are_channels_connected] ch_id:14 or 15 are not connected
[ 48.269935615/ 0x3b71e340] [open_client_mhi_channels] Channels are not connected
[ 48.269942751/ 0x3b71e3c9] [mhi_uci_client_open] Failed to open channels ret -19
[ 48.269950198/ 0x3b71e455] [mhi_uci_client_open] Closing failed channel
[ 49.271127337/ 0x3c9734ba] [mhi_uci_client_open] Client opened struct device node 0x7, ref count 0x0
[ 49.271154316/ 0x3c9736ac] [mhi_uci_client_open] Opening channels client 7
[ 49.271185410/ 0x3c9738f9] [mhi_uci_are_channels_connected] ch_id:14 or 15 are not connected
[ 49.271246816/ 0x3c973d97] [open_client_mhi_channels] Channels are not connected
[ 49.271253952/ 0x3c973e1f] [mhi_uci_client_open] Failed to open channels ret -19
[ 49.271261347/ 0x3c973eab] [mhi_uci_client_open] Closing failed channel
[ 90.273047358/ 0x6b837c94] [uci_ctrl_update] received state change update
[ 90.278366108/ 0x6b850b7d] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:12
[ 90.293745014/ 0x6b898cee] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:13
[ 90.299130900/ 0x6b8b20e0] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:4
[ 90.313265275/ 0x6b8f44f4] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:5
[ 90.318856160/ 0x6b90e845] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:14
[ 90.325161577/ 0x6b92c130] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:15
[ 90.411971056/ 0x6bac2fe0] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:20
[ 90.415995692/ 0x6bad5dbc] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:21
[ 90.447933140/ 0x6bb6b904] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:32
[ 90.453247202/ 0x6bb84799] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:33
[ 90.570350900/ 0x6bda9666] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:36
[ 90.574103140/ 0x6bdbafcc] [mhi_uci_chan_state_notify_all] Calling notify for ch_id:37
~ #
[-- Attachment #3: host_mhi.txt --]
[-- Type: text/plain, Size: 1426 bytes --]
shawn@rockpro64:~/Escritorio$ dmesg | grep mhi
[ 21.781954] mhi-pci-generic 0000:01:00.0: MHI PCI device found: foxconn-sdx65
[ 21.782002] mhi-pci-generic 0000:01:00.0: BAR 0: assigned [mem 0xfa000000-0xfa000fff 64bit]
[ 21.782096] mhi-pci-generic 0000:01:00.0: enabling device (0000 -> 0002)
[ 21.793477] mhi mhi0: Requested to power ON
[ 21.793520] mhi mhi0: Attempting power on with EE: MISSION MODE, state: SYS ERROR
[ 21.901833] mhi mhi0: Power on setup success
[ 21.901866] mhi mhi0: ##shawn## ret of async is 0
[ 21.902250] mhi mhi0: Handling state transition: READY
[ 21.902280] mhi mhi0: Device in READY State
[ 21.902296] mhi mhi0: Initializing MHI registers
[ 72.673362] mhi mhi0: ##shawn## current mode is 0, state is 0
[ 72.673524] mhi mhi0: Handling state transition: DISABLE
[ 72.673544] mhi mhi0: Processing disable transition with PM state: Linkdown or Error Fatal Detect
[ 72.673559] mhi mhi0: Waiting for all pending event ring processing to complete
[ 72.673599] mhi mhi0: Waiting for all pending threads to complete
[ 72.673613] mhi mhi0: Reset all active channels and remove MHI devices
[ 72.673630] mhi mhi0: Resetting EV CTXT and CMD CTXT
[ 72.673646] mhi mhi0: Exiting with PM state: DISABLE, MHI state: RESET
[ 72.673779] mhi-pci-generic 0000:01:00.0: failed to power up MHI controller
[ 72.675067] mhi-pci-generic: probe of 0000:01:00.0 failed with error -110
next prev parent reply other threads:[~2024-04-08 9:59 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <38c7997c.10212.18e84f08a4f.Coremail.slark_xiao@163.com>
2024-04-02 4:56 ` failed to power up MHI controller issue Manivannan Sadhasivam
2024-04-08 9:59 ` Slark Xiao [this message]
2024-04-09 4:35 ` Qiang Yu
[not found] ` <40210cbb.3949.18ed6b904d6.Coremail.slark_xiao@163.com>
2024-04-15 6:09 ` Qiang Yu
2024-04-15 10:33 ` Manivannan Sadhasivam
2024-04-16 3:56 ` Slark Xiao
2024-04-17 2:30 ` Qiang Yu
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