From: "Ravinandan Arakali" <ravinandan.arakali@s2io.com>
To: "'Jeff Garzik'" <jgarzik@pobox.com>
Cc: <netdev@oss.sgi.com>, <leonid.grossman@s2io.com>,
<raghavendra.koushik@s2io.com>, <rapuru.sriram@s2io.com>
Subject: RE: Patch submission for S2io Xframe driver to 2.6 kernel
Date: Mon, 13 Sep 2004 10:09:53 -0700 [thread overview]
Message-ID: <002201c499b4$7c7b60c0$a010100a@S2IOtech.com> (raw)
In-Reply-To: <413116FF.7000701@pobox.com>
[-- Attachment #1: Type: text/plain, Size: 643 bytes --]
Hi Jeff,
Attached is the patch with the first round comments incorporated.
In addition, this patch contains
Some fixes related to 32-bit systems.
Few fixes related to Rx path in NAPI.
Thanks to all for the comments.
Pls review this patch as well and come back with your comments.
Regards,
Ravi
-----Original Message-----
From: Jeff Garzik [mailto:jgarzik@pobox.com]
Sent: Saturday, August 28, 2004 4:37 PM
To: ravinandan.arakali@s2io.com
Cc: netdev@oss.sgi.com; leonid.grossman@s2io.com;
raghavendra.koushik@s2io.com
Subject: Re: Patch submission for S2io Xframe driver to 2.6 kernel
is there a follow-up patch addressing the comments ?
[-- Attachment #2: s2io_submit2_1_patch --]
[-- Type: application/octet-stream, Size: 187993 bytes --]
diff -urN vanilla_linux-2.6.7/drivers/net/Kconfig linux-2.6.7/drivers/net/Kconfig
--- vanilla_linux-2.6.7/drivers/net/Kconfig 2004-06-15 22:19:52.000000000 -0700
+++ linux-2.6.7/drivers/net/Kconfig 2004-09-08 12:54:13.000000000 -0700
@@ -2160,7 +2160,16 @@
config S2IO_NAPI
bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
depends on S2IO && EXPERIMENTAL
-
+config 2BUFF_MODE
+ bool "Use 2 Buffer Mode on Rx side."
+ depends on S2IO
+ ---help---
+ On enabling the 2 buffer mode, the received frame will be
+ split into 2 parts before being DMA'ed to the hosts memory.
+ The parts are the ethernet header and ethernet payload.
+ This is useful on systems where DMA'ing to to unaligned
+ physical memory loactions comes with a heavy price.
+ If not sure please say N.
endmenu
source "drivers/net/tokenring/Kconfig"
diff -urN vanilla_linux-2.6.7/drivers/net/s2io-regs.h linux-2.6.7/drivers/net/s2io-regs.h
--- vanilla_linux-2.6.7/drivers/net/s2io-regs.h 2004-06-15 22:19:22.000000000 -0700
+++ linux-2.6.7/drivers/net/s2io-regs.h 2004-09-08 12:55:02.000000000 -0700
@@ -289,6 +289,8 @@
u64 tda_err_alarm;
u64 pcc_err_reg;
+#define PCC_FB_ECC_DB_ERR vBIT(0xFF, 16, 8)
+
u64 pcc_err_mask;
u64 pcc_err_alarm;
@@ -512,6 +514,7 @@
#define RX_PA_CFG_IGNORE_FRM_ERR BIT(1)
#define RX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
#define RX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
+#define RX_PA_CFG_IGNORE_L2_ERR BIT(6)
u8 unused12[0x700 - 0x1D8];
diff -urN vanilla_linux-2.6.7/drivers/net/s2io.c linux-2.6.7/drivers/net/s2io.c
--- vanilla_linux-2.6.7/drivers/net/s2io.c 2004-06-15 22:19:37.000000000 -0700
+++ linux-2.6.7/drivers/net/s2io.c 2004-09-10 13:16:58.000000000 -0700
@@ -61,6 +61,7 @@
#include<asm/uaccess.h>
#include<linux/version.h>
#include<asm/io.h>
+#include<linux/proc_fs.h>
#include<linux/workqueue.h>
/* local include */
@@ -69,7 +70,16 @@
/* S2io Driver name & version. */
static char s2io_driver_name[] = "s2io";
-static char s2io_driver_version[] = "Version 1.0";
+static char s2iO_driver_version[] = "Version 1.1";
+
+/*
+ * Cards with following subsystem_id have a link state indication
+ * problem, 600B, 600C, 600D, 640B, 640C and 640D.
+ * macro below identifies these cards given the subsystem_id.
+ */
+#define CARDS_WITH_FAULTY_LINK_INDICATORS(subid) \
+ (((subid >= 0x600B) && (subid <= 0x600D)) || \
+ ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0
#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
@@ -80,10 +90,11 @@
static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
{
int level = 0;
- if ((sp->pkt_cnt[ring] - rxb_size) > 128) {
+ if ((sp->pkt_cnt[ring] - rxb_size) > 16) {
level = LOW;
- if (rxb_size < sp->pkt_cnt[ring] / 8)
+ if ((sp->pkt_cnt[ring] - rxb_size) < MAX_RXDS_PER_BLOCK) {
level = PANIC;
+ }
}
return level;
@@ -99,45 +110,45 @@
};
static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
- "tmac_frms",
- "tmac_data_octets",
- "tmac_drop_frms",
- "tmac_mcst_frms",
- "tmac_bcst_frms",
- "tmac_pause_ctrl_frms",
- "tmac_any_err_frms",
- "tmac_vld_ip_octets",
- "tmac_vld_ip",
- "tmac_drop_ip",
- "tmac_icmp",
- "tmac_rst_tcp",
- "tmac_tcp",
- "tmac_udp",
- "rmac_vld_frms",
- "rmac_data_octets",
- "rmac_fcs_err_frms",
- "rmac_drop_frms",
- "rmac_vld_mcst_frms",
- "rmac_vld_bcst_frms",
- "rmac_in_rng_len_err_frms",
- "rmac_long_frms",
- "rmac_pause_ctrl_frms",
- "rmac_discarded_frms",
- "rmac_usized_frms",
- "rmac_osized_frms",
- "rmac_frag_frms",
- "rmac_jabber_frms",
- "rmac_ip",
- "rmac_ip_octets",
- "rmac_hdr_err_ip",
- "rmac_drop_ip",
- "rmac_icmp",
- "rmac_tcp",
- "rmac_udp",
- "rmac_err_drp_udp",
- "rmac_pause_cnt",
- "rmac_accepted_ip",
- "rmac_err_tcp",
+ {"tmac_frms"},
+ {"tmac_data_octets"},
+ {"tmac_drop_frms"},
+ {"tmac_mcst_frms"},
+ {"tmac_bcst_frms"},
+ {"tmac_pause_ctrl_frms"},
+ {"tmac_any_err_frms"},
+ {"tmac_vld_ip_octets"},
+ {"tmac_vld_ip"},
+ {"tmac_drop_ip"},
+ {"tmac_icmp"},
+ {"tmac_rst_tcp"},
+ {"tmac_tcp"},
+ {"tmac_udp"},
+ {"rmac_vld_frms"},
+ {"rmac_data_octets"},
+ {"rmac_fcs_err_frms"},
+ {"rmac_drop_frms"},
+ {"rmac_vld_mcst_frms"},
+ {"rmac_vld_bcst_frms"},
+ {"rmac_in_rng_len_err_frms"},
+ {"rmac_long_frms"},
+ {"rmac_pause_ctrl_frms"},
+ {"rmac_discarded_frms"},
+ {"rmac_usized_frms"},
+ {"rmac_osized_frms"},
+ {"rmac_frag_frms"},
+ {"rmac_jabber_frms"},
+ {"rmac_ip"},
+ {"rmac_ip_octets"},
+ {"rmac_hdr_err_ip"},
+ {"rmac_drop_ip"},
+ {"rmac_icmp"},
+ {"rmac_tcp"},
+ {"rmac_udp"},
+ {"rmac_err_drp_udp"},
+ {"rmac_pause_cnt"},
+ {"rmac_accepted_ip"},
+ {"rmac_err_tcp"},
};
#define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
@@ -147,7 +158,8 @@
#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
-/* Constants to be programmed into the Xena's registers to configure
+/*
+ * Constants to be programmed into the Xena's registers to configure
* the XAUI.
*/
@@ -188,7 +200,9 @@
END_SIGN
};
-/* Constants for Fixing the MacAddress problem seen mostly on
+
+/*
+ * Constants for Fixing the MacAddress problem seen mostly on
* Alpha machines.
*/
static u64 fix_mac[] = {
@@ -209,16 +223,67 @@
END_SIGN
};
-
/* Module Loadable parameters. */
-static u32 ring_num;
static u32 frame_len[MAX_RX_RINGS];
-static u32 ring_len[MAX_RX_RINGS];
-static u32 fifo_num;
-static u32 fifo_len[MAX_TX_FIFOS];
static u32 rx_prio;
static u32 tx_prio;
-static u8 latency_timer = 0;
+
+static unsigned int lso_enable = 1;
+#ifndef CONFIG_S2IO_NAPI
+static unsigned int indicate_max_pkts = 0;
+#endif
+static unsigned int cksum_offload_enable = 1;
+static unsigned int TxFifoNum = 1;
+static unsigned int TxFIFOLen_0 = DEFAULT_FIFO_LEN;
+static unsigned int TxFIFOLen_1 = 0;
+static unsigned int TxFIFOLen_2 = 0;
+static unsigned int TxFIFOLen_3 = 0;
+static unsigned int TxFIFOLen_4 = 0;
+static unsigned int TxFIFOLen_5 = 0;
+static unsigned int TxFIFOLen_6 = 0;
+static unsigned int TxFIFOLen_7 = 0;
+static unsigned int MaxTxDs = MAX_SKB_FRAGS;
+static unsigned int RxRingNum = 1;
+static unsigned int RxRingSz_0 = SMALL_BLK_CNT;
+static unsigned int RxRingSz_1 = 0;
+static unsigned int RxRingSz_2 = 0;
+static unsigned int RxRingSz_3 = 0;
+static unsigned int RxRingSz_4 = 0;
+static unsigned int RxRingSz_5 = 0;
+static unsigned int RxRingSz_6 = 0;
+static unsigned int RxRingSz_7 = 0;
+static unsigned int Stats_refresh_time = 4;
+static unsigned int rmac_pause_time = 65535;
+static unsigned int mc_pause_threshold_q0q3 = 187;
+static unsigned int mc_pause_threshold_q4q7 = 187;
+static unsigned int shared_splits = 0;
+#if defined(__ia64__)
+static unsigned int max_splits_trans = XENA_THREE_SPLIT_TRANSACTION;
+#else
+static unsigned int max_splits_trans = XENA_TWO_SPLIT_TRANSACTION;
+#endif
+static unsigned int tmac_util_period = 5;
+static unsigned int rmac_util_period = 5;
+static unsigned int tx_timer_val = 0xFFF;
+static unsigned int tx_utilz_periodic = 1;
+static unsigned int rx_timer_val = 0xFFF;
+static unsigned int rx_utilz_periodic = 1;
+static unsigned int tx_urange_a = 0xA;
+static unsigned int tx_ufc_a = 0x10;
+static unsigned int tx_urange_b = 0x10;
+static unsigned int tx_ufc_b = 0x20;
+static unsigned int tx_urange_c = 0x30;
+static unsigned int tx_ufc_c = 0x40;
+static unsigned int tx_ufc_d = 0x80;
+static unsigned int rx_urange_a = 0xA;
+static unsigned int rx_ufc_a = 0x1;
+static unsigned int rx_urange_b = 0x10;
+static unsigned int rx_ufc_b = 0x2;
+static unsigned int rx_urange_c = 0x30;
+static unsigned int rx_ufc_c = 0x40;
+static unsigned int rx_ufc_d = 0x80;
+static u8 latency_timer = 0xf8;
+static u8 max_read_byte_cnt = 2;
/*
* S2IO device table.
@@ -235,30 +300,36 @@
MODULE_DEVICE_TABLE(pci, s2io_tbl);
static struct pci_driver s2io_driver = {
- name:"S2IO",
- id_table:s2io_tbl,
- probe:s2io_init_nic,
- remove:__devexit_p(s2io_rem_nic),
+ name:"S2IO",
+ id_table:s2io_tbl,
+ probe:s2io_init_nic,
+ remove:__devexit_p(s2io_rem_nic),
};
-/*
- * Input Arguments:
- * Device private variable.
- * Return Value:
- * SUCCESS on success and an appropriate -ve value on failure.
- * Description:
- * The function allocates the all memory areas shared
- * between the NIC and the driver. This includes Tx descriptors,
- * Rx descriptors and the statistics block.
+/* A simplifier macro used both by init and free shared_mem Fns(). */
+#define container_index(len, per_each) ((len+per_each - 1) / per_each)
+
+/**
+ * init_shared_mem - Allocation and Initialization of Memory
+ * @nic: Device private variable.
+ * Description: The function allocates the all memory areas shared
+ * between the NIC and the driver. This includes Tx descriptors,
+ * Rx descriptors and the statistics block.
*/
-static int initSharedMem(struct s2io_nic *nic)
+
+static int init_shared_mem(struct s2io_nic *nic)
{
u32 size;
void *tmp_v_addr, *tmp_v_addr_next;
dma_addr_t tmp_p_addr, tmp_p_addr_next;
RxD_block_t *pre_rxd_blk = NULL;
int i, j, blk_cnt;
+ int lst_size, lst_per_page;
struct net_device *dev = nic->dev;
+#ifdef CONFIG_2BUFF_MODE
+ u64 tmp;
+ buffAdd_t *ba;
+#endif
mac_info_t *mac_control;
struct config_param *config;
@@ -270,7 +341,7 @@
/* Allocation and initialization of TXDLs in FIOFs */
size = 0;
for (i = 0; i < config->TxFIFONum; i++) {
- size += config->TxCfg[i].FifoLen;
+ size += config->tx_cfg[i].FifoLen;
}
if (size > MAX_AVAILABLE_TXDS) {
DBG_PRINT(ERR_DBG, "%s: Total number of Tx FIFOs ",
@@ -279,55 +350,71 @@
DBG_PRINT(ERR_DBG, "that can be used\n");
return FAILURE;
}
- size *= (sizeof(TxD_t) * config->MaxTxDs);
- mac_control->txd_list_mem = pci_alloc_consistent
- (nic->pdev, size, &mac_control->txd_list_mem_phy);
- if (!mac_control->txd_list_mem) {
- return -ENOMEM;
- }
- mac_control->txd_list_mem_sz = size;
-
- tmp_v_addr = mac_control->txd_list_mem;
- tmp_p_addr = mac_control->txd_list_mem_phy;
- memset(tmp_v_addr, 0, size);
-
- DBG_PRINT(INIT_DBG, "%s:List Mem PHY: 0x%llx\n", dev->name,
- (unsigned long long) tmp_p_addr);
+ lst_size = (sizeof(TxD_t) * config->MaxTxDs);
+ lst_per_page = PAGE_SIZE / lst_size;
for (i = 0; i < config->TxFIFONum; i++) {
- mac_control->txdl_start_phy[i] = tmp_p_addr;
- mac_control->txdl_start[i] = (TxD_t *) tmp_v_addr;
+ int fifo_len = config->tx_cfg[i].FifoLen;
+ int list_holder_size = fifo_len * sizeof(list_info_hold_t);
+ nic->list_info[i] = kmalloc(list_holder_size, GFP_KERNEL);
+ if (!nic->list_info[i]) {
+ DBG_PRINT(ERR_DBG,
+ "Malloc failed for list_info\n");
+ return -ENOMEM;
+ }
+ memset(nic->list_info[i], 0, list_holder_size);
+ }
+ for (i = 0; i < config->TxFIFONum; i++) {
+ int page_num = container_index(config->tx_cfg[i].FifoLen,
+ lst_per_page);
mac_control->tx_curr_put_info[i].offset = 0;
mac_control->tx_curr_put_info[i].fifo_len =
- config->TxCfg[i].FifoLen - 1;
+ config->tx_cfg[i].FifoLen - 1;
mac_control->tx_curr_get_info[i].offset = 0;
mac_control->tx_curr_get_info[i].fifo_len =
- config->TxCfg[i].FifoLen - 1;
-
- tmp_p_addr +=
- (config->TxCfg[i].FifoLen * (sizeof(TxD_t)) *
- config->MaxTxDs);
- tmp_v_addr +=
- (config->TxCfg[i].FifoLen * (sizeof(TxD_t)) *
- config->MaxTxDs);
+ config->tx_cfg[i].FifoLen - 1;
+ for (j = 0; j < page_num; j++) {
+ int k = 0;
+ dma_addr_t tmp_p;
+ void *tmp_v;
+ tmp_v = pci_alloc_consistent(nic->pdev,
+ PAGE_SIZE, &tmp_p);
+ if (!tmp_v) {
+ DBG_PRINT(ERR_DBG,
+ "pci_alloc_consistent ");
+ DBG_PRINT(ERR_DBG, "failed for TxDL\n");
+ return -ENOMEM;
+ }
+ while (k < lst_per_page) {
+ int l = (j * lst_per_page) + k;
+ if (l == config->tx_cfg[i].FifoLen)
+ goto end_txd_alloc;
+ nic->list_info[i][l].list_virt_addr =
+ tmp_v + (k * lst_size);
+ nic->list_info[i][l].list_phy_addr =
+ tmp_p + (k * lst_size);
+ k++;
+ }
+ }
}
+ end_txd_alloc:
/* Allocation and initialization of RXDs in Rings */
size = 0;
for (i = 0; i < config->RxRingNum; i++) {
- if (config->RxCfg[i].NumRxd % (MAX_RXDS_PER_BLOCK + 1)) {
+ if (config->rx_cfg[i].NumRxd % (MAX_RXDS_PER_BLOCK + 1)) {
DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
i);
DBG_PRINT(ERR_DBG, "RxDs per Block");
return FAILURE;
}
- size += config->RxCfg[i].NumRxd;
+ size += config->rx_cfg[i].NumRxd;
nic->block_count[i] =
- config->RxCfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1);
+ config->rx_cfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1);
nic->pkt_cnt[i] =
- config->RxCfg[i].NumRxd - nic->block_count[i];
+ config->rx_cfg[i].NumRxd - nic->block_count[i];
}
size = (size * (sizeof(RxD_t)));
mac_control->rxd_ring_mem_sz = size;
@@ -336,20 +423,25 @@
mac_control->rx_curr_get_info[i].block_index = 0;
mac_control->rx_curr_get_info[i].offset = 0;
mac_control->rx_curr_get_info[i].ring_len =
- config->RxCfg[i].NumRxd - 1;
+ config->rx_cfg[i].NumRxd - 1;
mac_control->rx_curr_put_info[i].block_index = 0;
mac_control->rx_curr_put_info[i].offset = 0;
mac_control->rx_curr_put_info[i].ring_len =
- config->RxCfg[i].NumRxd - 1;
+ config->rx_cfg[i].NumRxd - 1;
blk_cnt =
- config->RxCfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1);
+ config->rx_cfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1);
/* Allocating all the Rx blocks */
for (j = 0; j < blk_cnt; j++) {
+#ifndef CONFIG_2BUFF_MODE
size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t));
+#else
+ size = SIZE_OF_BLOCK;
+#endif
tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
&tmp_p_addr);
if (tmp_v_addr == NULL) {
- /* In case of failure, freeSharedMem()
+ /*
+ * In case of failure, free_shared_mem()
* is called, which should free any
* memory that was alloced till the
* failure happened.
@@ -377,20 +469,68 @@
pre_rxd_blk->reserved_1 = END_OF_BLOCK; /* last RxD
* marker.
*/
+#ifndef CONFIG_2BUFF_MODE
pre_rxd_blk->reserved_2_pNext_RxD_block =
(unsigned long) tmp_v_addr_next;
+#endif
pre_rxd_blk->pNext_RxD_Blk_physical =
(u64) tmp_p_addr_next;
}
}
+#ifdef CONFIG_2BUFF_MODE
+ /*
+ * Allocation of Storages for buffer addresses in 2BUFF mode
+ * and the buffers as well.
+ */
+ for (i = 0; i < config->RxRingNum; i++) {
+ blk_cnt =
+ config->rx_cfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1);
+ nic->ba[i] = kmalloc((sizeof(buffAdd_t *) * blk_cnt),
+ GFP_KERNEL);
+ if (!nic->ba[i])
+ return -ENOMEM;
+ for (j = 0; j < blk_cnt; j++) {
+ int k = 0;
+ nic->ba[i][j] = kmalloc((sizeof(buffAdd_t) *
+ (MAX_RXDS_PER_BLOCK + 1)),
+ GFP_KERNEL);
+ if (!nic->ba[i][j])
+ return -ENOMEM;
+ while (k != MAX_RXDS_PER_BLOCK) {
+ ba = &nic->ba[i][j][k];
+
+ ba->ba_0_org = (void *) kmalloc
+ (BUF0_LEN + ALIGN_SIZE, GFP_ATOMIC);
+ if (!ba->ba_0_org)
+ return -ENOMEM;
+ tmp = (u64) ba->ba_0_org;
+ tmp += ALIGN_SIZE;
+ tmp &= ~((u64) ALIGN_SIZE);
+ ba->ba_0 = (void *) tmp;
+
+ ba->ba_1_org = (void *) kmalloc
+ (BUF1_LEN + ALIGN_SIZE, GFP_ATOMIC);
+ if (!ba->ba_1_org)
+ return -ENOMEM;
+ tmp = (u64) ba->ba_1_org;
+ tmp += ALIGN_SIZE;
+ tmp &= ~((u64) ALIGN_SIZE);
+ ba->ba_1 = (void *) tmp;
+ k++;
+ }
+ }
+ }
+#endif
+
/* Allocation and initialization of Statistics block */
size = sizeof(StatInfo_t);
mac_control->stats_mem = pci_alloc_consistent
(nic->pdev, size, &mac_control->stats_mem_phy);
if (!mac_control->stats_mem) {
- /* In case of failure, freeSharedMem() is called, which
+ /*
+ * In case of failure, free_shared_mem() is called, which
* should free any memory that was alloced till the
* failure happened.
*/
@@ -399,8 +539,12 @@
mac_control->stats_mem_sz = size;
tmp_v_addr = mac_control->stats_mem;
- mac_control->StatsInfo = (StatInfo_t *) tmp_v_addr;
+ mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
memset(tmp_v_addr, 0, size);
+#ifdef SNMP_SUPPORT
+ nic->nMemorySize = mac_control->txd_list_mem_sz +
+ mac_control->stats_mem_sz + mac_control->rxd_ring_mem_sz;
+#endif
DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
(unsigned long long) tmp_p_addr);
@@ -408,22 +552,21 @@
return SUCCESS;
}
-/*
- * Input Arguments:
- * Device peivate variable.
- * Return Value:
- * NONE
- * Description:
- * This function is to free all memory locations allocated by
- * the initSharedMem() function and return it to the kernel.
+/**
+ * free_shared_mem - Free the allocated Memory
+ * @nic: Device private variable.
+ * Description: This function is to free all memory locations allocated by
+ * the init_shared_mem() function and return it to the kernel.
*/
-static void freeSharedMem(struct s2io_nic *nic)
+
+static void free_shared_mem(struct s2io_nic *nic)
{
int i, j, blk_cnt, size;
void *tmp_v_addr;
dma_addr_t tmp_p_addr;
mac_info_t *mac_control;
struct config_param *config;
+ int lst_size, lst_per_page;
if (!nic)
@@ -432,14 +575,30 @@
mac_control = &nic->mac_control;
config = &nic->config;
- if (mac_control->txd_list_mem) {
- pci_free_consistent(nic->pdev,
- mac_control->txd_list_mem_sz,
- mac_control->txd_list_mem,
- mac_control->txd_list_mem_phy);
+ lst_size = (sizeof(TxD_t) * config->MaxTxDs);
+ lst_per_page = PAGE_SIZE / lst_size;
+
+ for (i = 0; i < config->TxFIFONum; i++) {
+ int page_num = container_index(config->tx_cfg[i].FifoLen,
+ lst_per_page);
+ for (j = 0; j < page_num; j++) {
+ int mem_blks = (j * lst_per_page);
+ if (!nic->list_info[i][mem_blks].list_virt_addr)
+ break;
+ pci_free_consistent(nic->pdev, PAGE_SIZE,
+ nic->list_info[i][mem_blks].
+ list_virt_addr,
+ nic->list_info[i][mem_blks].
+ list_phy_addr);
+ }
+ kfree(nic->list_info[i]);
}
+#ifndef CONFIG_2BUFF_MODE
size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t));
+#else
+ size = SIZE_OF_BLOCK;
+#endif
for (i = 0; i < config->RxRingNum; i++) {
blk_cnt = nic->block_count[i];
for (j = 0; j < blk_cnt; j++) {
@@ -452,6 +611,28 @@
}
}
+#ifdef CONFIG_2BUFF_MODE
+ /* Freeing buffer storage addresses in 2BUFF mode. */
+ for (i = 0; i < config->RxRingNum; i++) {
+ blk_cnt =
+ config->rx_cfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1);
+ for (j = 0; j < blk_cnt; j++) {
+ int k = 0;
+ if (!nic->ba[i][j])
+ continue;
+ while (k != MAX_RXDS_PER_BLOCK) {
+ buffAdd_t *ba = &nic->ba[i][j][k];
+ kfree(ba->ba_0_org);
+ kfree(ba->ba_1_org);
+ k++;
+ }
+ kfree(nic->ba[i][j]);
+ }
+ if (nic->ba[i])
+ kfree(nic->ba[i]);
+ }
+#endif
+
if (mac_control->stats_mem) {
pci_free_consistent(nic->pdev,
mac_control->stats_mem_sz,
@@ -460,16 +641,16 @@
}
}
-/*
- * Input Arguments:
- * device peivate variable
- * Return Value:
- * SUCCESS on success and '-1' on failure (endian settings incorrect).
- * Description:
- * The function sequentially configures every block
+/**
+ * init_nic - Initialization of hardware
+ * @nic: device peivate variable
+ * Description: The function sequentially configures every block
* of the H/W from their reset values.
+ * Returns: SUCCESS on success and
+ * '-1' on failure (endian settings incorrect).
*/
-static int initNic(struct s2io_nic *nic)
+
+static int init_nic(struct s2io_nic *nic)
{
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
struct net_device *dev = nic->dev;
@@ -485,11 +666,13 @@
mac_control = &nic->mac_control;
config = &nic->config;
- /* Set proper endian settings and verify the same by
- * reading the PIF Feed-back register.
+ /*
+ * Set proper endian settings and verify the same by
+ * reading the PIF Feed-back register.
*/
#ifdef __BIG_ENDIAN
- /* The device by default set to a big endian format, so
+ /*
+ * The device by default set to a big endian format, so
* a big endian driver need not set anything.
*/
writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
@@ -510,7 +693,8 @@
SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
writeq(val64, &bar0->swapper_ctrl);
#else
- /* Initially we enable all bits to make it accessible by
+ /*
+ * Initially we enable all bits to make it accessible by
* the driver, then we selectively enable only those bits
* that we want to set.
*/
@@ -537,8 +721,9 @@
writeq(val64, &bar0->swapper_ctrl);
#endif
- /* Verifying if endian settings are accurate by reading
- * a feedback register.
+ /*
+ * Verifying if endian settings are accurate by
+ * reading a feedback register.
*/
val64 = readq(&bar0->pif_rd_swapper_fb);
if (val64 != 0x0123456789ABCDEFULL) {
@@ -559,10 +744,13 @@
schedule_timeout(HZ / 2);
/* Enable Receiving broadcasts */
+ add = (void *) &bar0->mac_cfg;
val64 = readq(&bar0->mac_cfg);
val64 |= MAC_RMAC_BCAST_ENABLE;
writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
- writeq(val64, &bar0->mac_cfg);
+ writel((u32) val64, add);
+ writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
+ writel((u32) (val64 >> 32), (add + 4));
/* Read registers in all blocks */
val64 = readq(&bar0->mac_int_mask);
@@ -573,8 +761,9 @@
val64 = dev->mtu;
writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
- /* Configuring the XAUI Interface of Xena.
- *****************************************
+ /*
+ * Configuring the XAUI Interface of Xena.
+ * ***************************************
* To Configure the Xena's XAUI, one has to write a series
* of 64 bit values into two registers in a particular
* sequence. Hence a macro 'SWITCH_SIGN' has been defined
@@ -593,8 +782,8 @@
dtx_cnt++;
goto mdio_cfg;
}
- writeq(default_dtx_cfg[dtx_cnt],
- &bar0->dtx_control);
+ SPECIAL_REG_WRITE(default_dtx_cfg[dtx_cnt],
+ &bar0->dtx_control, UF);
val64 = readq(&bar0->dtx_control);
dtx_cnt++;
}
@@ -604,8 +793,8 @@
mdio_cnt++;
goto dtx_cfg;
}
- writeq(default_mdio_cfg[mdio_cnt],
- &bar0->mdio_control);
+ SPECIAL_REG_WRITE(default_mdio_cfg[mdio_cnt],
+ &bar0->mdio_control, UF);
val64 = readq(&bar0->mdio_control);
mdio_cnt++;
}
@@ -627,8 +816,8 @@
for (i = 0, j = 0; i < config->TxFIFONum; i++) {
val64 |=
- vBIT(config->TxCfg[i].FifoLen - 1, ((i * 32) + 19),
- 13) | vBIT(config->TxCfg[i].FifoPriority,
+ vBIT(config->tx_cfg[i].FifoLen - 1, ((i * 32) + 19),
+ 13) | vBIT(config->tx_cfg[i].FifoPriority,
((i * 32) + 5), 3);
if (i == (config->TxFIFONum - 1)) {
@@ -677,12 +866,13 @@
val64 = 0;
for (i = 0; i < config->RxRingNum; i++) {
val64 |=
- vBIT(config->RxCfg[i].RingPriority, (5 + (i * 8)), 3);
+ vBIT(config->rx_cfg[i].RingPriority, (5 + (i * 8)), 3);
}
writeq(val64, &bar0->rx_queue_priority);
- /* Allocating equal share of memory to all the configured
- * Rings.
+ /*
+ * Allocating equal share of memory to all the
+ * configured Rings.
*/
val64 = 0;
for (i = 0; i < config->RxRingNum; i++) {
@@ -724,7 +914,8 @@
}
writeq(val64, &bar0->rx_queue_cfg);
- /* Initializing the Tx round robin registers to 0.
+ /*
+ * Initializing the Tx round robin registers to 0.
* Filling Tx and Rx round robin registers as per the
* number of FIFOs and Rings is still TODO.
*/
@@ -734,9 +925,11 @@
writeq(0, &bar0->tx_w_round_robin_3);
writeq(0, &bar0->tx_w_round_robin_4);
- /* Disable Rx steering. Hard coding all packets be steered to
+ /*
+ * TODO
+ * Disable Rx steering. Hard coding all packets be steered to
* Queue 0 for now.
- * TODO*/
+ */
if (rx_prio) {
u64 def = 0x8000000000000000ULL, tmp;
for (i = 0; i < MAX_RX_RINGS; i++) {
@@ -760,34 +953,43 @@
/* Enable statistics */
writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
- val64 = SET_UPDT_PERIOD(8) | STAT_CFG_STAT_RO | STAT_CFG_STAT_EN;
+ val64 = SET_UPDT_PERIOD(Stats_refresh_time) |
+ STAT_CFG_STAT_RO | STAT_CFG_STAT_EN;
writeq(val64, &bar0->stat_cfg);
- /* Initializing the sampling rate for the device to calculate the
+ /*
+ * Initializing the sampling rate for the device to calculate the
* bandwidth utilization.
*/
- val64 = MAC_TX_LINK_UTIL_VAL(0x5) | MAC_RX_LINK_UTIL_VAL(0x5);
+ val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
+ MAC_RX_LINK_UTIL_VAL(rmac_util_period);
writeq(val64, &bar0->mac_link_util);
- /* Initializing the Transmit and Receive Traffic Interrupt
+ /*
+ * Initializing the Transmit and Receive Traffic Interrupt
* Scheme.
*/
/* TTI Initialization */
- val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0xFFF) |
- TTI_DATA1_MEM_TX_URNG_A(0xA) | TTI_DATA1_MEM_TX_URNG_B(0x10) |
- TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
+ val64 = TTI_DATA1_MEM_TX_TIMER_VAL(tx_timer_val) |
+ TTI_DATA1_MEM_TX_URNG_A(tx_urange_a) |
+ TTI_DATA1_MEM_TX_URNG_B(tx_urange_b) |
+ TTI_DATA1_MEM_TX_URNG_C(tx_urange_c);
+ if (tx_utilz_periodic)
+ val64 |= TTI_DATA1_MEM_TX_TIMER_AC_EN;
writeq(val64, &bar0->tti_data1_mem);
- val64 =
- TTI_DATA2_MEM_TX_UFC_A(0x10) | TTI_DATA2_MEM_TX_UFC_B(0x20) |
- TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
+ val64 = TTI_DATA2_MEM_TX_UFC_A(tx_ufc_a) |
+ TTI_DATA2_MEM_TX_UFC_B(tx_ufc_b) |
+ TTI_DATA2_MEM_TX_UFC_C(tx_ufc_c) |
+ TTI_DATA2_MEM_TX_UFC_D(tx_ufc_d);
writeq(val64, &bar0->tti_data2_mem);
val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
writeq(val64, &bar0->tti_command_mem);
- /* Once the operation completes, the Strobe bit of the command
+ /*
+ * Once the operation completes, the Strobe bit of the command
* register will be reset. We poll for this particular condition
* We wait for a maximum of 500ms for the operation to complete,
* if it's not complete by then we return error.
@@ -809,19 +1011,26 @@
}
/* RTI Initialization */
- val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF) |
- RTI_DATA1_MEM_RX_URNG_A(0xA) | RTI_DATA1_MEM_RX_URNG_B(0x10) |
- RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
+ val64 = RTI_DATA1_MEM_RX_TIMER_VAL(rx_timer_val) |
+ RTI_DATA1_MEM_RX_URNG_A(rx_urange_a) |
+ RTI_DATA1_MEM_RX_URNG_B(rx_urange_b) |
+ RTI_DATA1_MEM_RX_URNG_C(rx_urange_c);
+ if (rx_utilz_periodic)
+ val64 |= RTI_DATA1_MEM_RX_TIMER_AC_EN;
+
writeq(val64, &bar0->rti_data1_mem);
- val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) | RTI_DATA2_MEM_RX_UFC_B(0x2) |
- RTI_DATA2_MEM_RX_UFC_C(0x40) | RTI_DATA2_MEM_RX_UFC_D(0x80);
+ val64 = RTI_DATA2_MEM_RX_UFC_A(rx_ufc_a) |
+ RTI_DATA2_MEM_RX_UFC_B(rx_ufc_b) |
+ RTI_DATA2_MEM_RX_UFC_C(rx_ufc_c) |
+ RTI_DATA2_MEM_RX_UFC_D(rx_ufc_d);
writeq(val64, &bar0->rti_data2_mem);
val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD;
writeq(val64, &bar0->rti_command_mem);
- /* Once the operation completes, the Strobe bit of the command
+ /*
+ * Once the operation completes, the Strobe bit of the command
* register will be reset. We poll for this particular condition
* We wait for a maximum of 500ms for the operation to complete,
* if it's not complete by then we return error.
@@ -842,7 +1051,8 @@
schedule_timeout(HZ / 20);
}
- /* Initializing proper values as Pause threshold into all
+ /*
+ * Initializing proper values as Pause threshold into all
* the 8 Queues on Rx side.
*/
writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
@@ -858,22 +1068,62 @@
writel((u32) (val64 >> 32), (add + 4));
val64 = readq(&bar0->mac_cfg);
+ /*
+ * Set the time value to be inserted in the pause frame
+ * generated by xena.
+ */
+ val64 = readq(&bar0->rmac_pause_cfg);
+ val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
+ val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
+ writeq(val64, &bar0->rmac_pause_cfg);
+
+ /*
+ * Set the Threshold Limit for Generating the pause frame
+ * If the amount of data in any Queue exceeds ratio of
+ * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
+ * pause frame is generated
+ */
+ val64 = 0;
+ for (i = 0; i < 4; i++) {
+ val64 |=
+ (((u64) 0xFF00 | nic->mac_control.
+ mc_pause_threshold_q0q3)
+ << (i * 2 * 8));
+ }
+ writeq(val64, &bar0->mc_pause_thresh_q0q3);
+
+ val64 = 0;
+ for (i = 0; i < 4; i++) {
+ val64 |=
+ (((u64) 0xFF00 | nic->mac_control.
+ mc_pause_threshold_q4q7)
+ << (i * 2 * 8));
+ }
+ writeq(val64, &bar0->mc_pause_thresh_q4q7);
+
+ /*
+ * TxDMA will stop Read request if the number of read split has
+ * exceeded the limit pointed by shared_splits
+ */
+ val64 = readq(&bar0->pic_control);
+ val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
+ writeq(val64, &bar0->pic_control);
+
return SUCCESS;
}
-/*
- * Input Arguments:
- * device private variable,
- * A mask indicating which Intr block must be modified and,
- * A flag indicating whether to enable or disable the Intrs.
- * Return Value:
- * NONE.
- * Description:
- * This function will either disable or enable the interrupts
+/**
+ * en_dis_able_nic_intrs - Enable or Disable the interrupts
+ * @nic: device private variable,
+ * @mask: A mask indicating which Intr block must be modified and,
+ * @flag: A flag indicating whether to enable or disable the Intrs.
+ * Description: This function will either disable or enable the interrupts
* depending on the flag argument. The mask argument can be used to
* enable/disable any Intr block.
+ * Return Value: NONE.
*/
-static void en_dis_able_NicIntrs(struct s2io_nic *nic, u16 mask, int flag)
+
+static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
{
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
register u64 val64 = 0, temp64 = 0;
@@ -887,15 +1137,20 @@
temp64 = readq(&bar0->general_int_mask);
temp64 &= ~((u64) val64);
writeq(temp64, &bar0->general_int_mask);
- /* Disabled all PCIX, Flash, MDIO, IIC and GPIO
- * interrupts for now.
- * TODO */
+ /*
+ * Disabled all PCIX, Flash, MDIO, IIC and GPIO
+ * interrupts for now.
+ * TODO
+ */
writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
- /* No MSI Support is available presently, so TTI and
+ /*
+ * No MSI Support is available presently, so TTI and
* RTI interrupts are also disabled.
*/
} else if (flag == DISABLE_INTRS) {
- /* Disable PIC Intrs in the general intr mask register
+ /*
+ * Disable PIC Intrs in the general
+ * intr mask register
*/
writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
temp64 = readq(&bar0->general_int_mask);
@@ -907,24 +1162,34 @@
/* DMA Interrupts */
/* Enabling/Disabling Tx DMA interrupts */
if (mask & TX_DMA_INTR) {
- /* Enable TxDMA Intrs in the general intr mask register */
+ /* Enable TxDMA Intrs in the general intr mask register */
val64 = TXDMA_INT_M;
if (flag == ENABLE_INTRS) {
temp64 = readq(&bar0->general_int_mask);
temp64 &= ~((u64) val64);
writeq(temp64, &bar0->general_int_mask);
- /* Disable all interrupts other than PFC interrupt in
- * DMA level.
+ /*
+ * Keep all interrupts other than PFC interrupt
+ * and PCC interrupt disabled in DMA level.
*/
- val64 = DISABLE_ALL_INTRS & (~TXDMA_PFC_INT_M);
+ val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
+ TXDMA_PCC_INT_M);
writeq(val64, &bar0->txdma_int_mask);
- /* Enable only the MISC error 1 interrupt in PFC block
+ /*
+ * Enable only the MISC error 1 interrupt in PFC block
*/
val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
writeq(val64, &bar0->pfc_err_mask);
+ /*
+ * Enable only the FB_ECC error interrupt in PCC block
+ */
+ val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
+ writeq(val64, &bar0->pcc_err_mask);
} else if (flag == DISABLE_INTRS) {
- /* Disable TxDMA Intrs in the general intr mask
- * register */
+ /*
+ * Disable TxDMA Intrs in the general intr mask
+ * register
+ */
writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
temp64 = readq(&bar0->general_int_mask);
@@ -941,12 +1206,16 @@
temp64 = readq(&bar0->general_int_mask);
temp64 &= ~((u64) val64);
writeq(temp64, &bar0->general_int_mask);
- /* All RxDMA block interrupts are disabled for now
- * TODO */
+ /*
+ * All RxDMA block interrupts are disabled for now
+ * TODO
+ */
writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
} else if (flag == DISABLE_INTRS) {
- /* Disable RxDMA Intrs in the general intr mask
- * register */
+ /*
+ * Disable RxDMA Intrs in the general intr mask
+ * register
+ */
writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
temp64 = readq(&bar0->general_int_mask);
val64 |= temp64;
@@ -962,9 +1231,11 @@
temp64 = readq(&bar0->general_int_mask);
temp64 &= ~((u64) val64);
writeq(temp64, &bar0->general_int_mask);
- /* All MAC block error interrupts are disabled for now
+ /*
+ * All MAC block error interrupts are disabled for now
* except the link status change interrupt.
- * TODO*/
+ * TODO
+ */
val64 = MAC_INT_STATUS_RMAC_INT;
temp64 = readq(&bar0->mac_int_mask);
temp64 &= ~((u64) val64);
@@ -974,7 +1245,8 @@
val64 &= ~((u64) RMAC_LINK_STATE_CHANGE_INT);
writeq(val64, &bar0->mac_rmac_err_mask);
} else if (flag == DISABLE_INTRS) {
- /* Disable MAC Intrs in the general intr mask register
+ /*
+ * Disable MAC Intrs in the general intr mask register
*/
writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
writeq(DISABLE_ALL_INTRS,
@@ -993,11 +1265,14 @@
temp64 = readq(&bar0->general_int_mask);
temp64 &= ~((u64) val64);
writeq(temp64, &bar0->general_int_mask);
- /* All XGXS block error interrupts are disabled for now
- * TODO */
+ /*
+ * All XGXS block error interrupts are disabled for now
+ * TODO
+ */
writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
} else if (flag == DISABLE_INTRS) {
- /* Disable MC Intrs in the general intr mask register
+ /*
+ * Disable MC Intrs in the general intr mask register
*/
writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
temp64 = readq(&bar0->general_int_mask);
@@ -1013,11 +1288,14 @@
temp64 = readq(&bar0->general_int_mask);
temp64 &= ~((u64) val64);
writeq(temp64, &bar0->general_int_mask);
- /* All MC block error interrupts are disabled for now
- * TODO */
+ /*
+ * All MC block error interrupts are disabled for now
+ * TODO
+ */
writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
} else if (flag == DISABLE_INTRS) {
- /* Disable MC Intrs in the general intr mask register
+ /*
+ * Disable MC Intrs in the general intr mask register
*/
writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
temp64 = readq(&bar0->general_int_mask);
@@ -1034,15 +1312,15 @@
temp64 = readq(&bar0->general_int_mask);
temp64 &= ~((u64) val64);
writeq(temp64, &bar0->general_int_mask);
- /* Enable all the Tx side interrupts */
- writeq(0x0, &bar0->tx_traffic_mask); /* '0' Enables
- * all 64 TX
- * interrupt
- * levels.
- */
+ /*
+ * Enable all the Tx side interrupts
+ * writing 0 Enables all 64 TX interrupt levels
+ */
+ writeq(0x0, &bar0->tx_traffic_mask);
} else if (flag == DISABLE_INTRS) {
- /* Disable Tx Traffic Intrs in the general intr mask
- * register.
+ /*
+ * Disable Tx Traffic Intrs in the general intr mask
+ * register.
*/
writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
temp64 = readq(&bar0->general_int_mask);
@@ -1058,14 +1336,12 @@
temp64 = readq(&bar0->general_int_mask);
temp64 &= ~((u64) val64);
writeq(temp64, &bar0->general_int_mask);
- writeq(0x0, &bar0->rx_traffic_mask); /* '0' Enables
- * all 8 RX
- * interrupt
- * levels.
- */
+ /* writing 0 Enables all 8 RX interrupt levels */
+ writeq(0x0, &bar0->rx_traffic_mask);
} else if (flag == DISABLE_INTRS) {
- /* Disable Rx Traffic Intrs in the general intr mask
- * register.
+ /*
+ * Disable Rx Traffic Intrs in the general intr mask
+ * register.
*/
writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
temp64 = readq(&bar0->general_int_mask);
@@ -1075,17 +1351,19 @@
}
}
-/*
- * Input Arguments:
- * val64 - Value read from adapter status register.
- * flag - indicates if the adapter enable bit was ever written once before.
- * Return Value:
- * void.
- * Description:
- * Returns whether the H/W is ready to go or not. Depending on whether
- * adapter enable bit was written or not the comparison differs and the
- * calling function passes the input argument flag to indicate this.
+/**
+ * verify_xena_quiescence - Checks whether the H/W is ready
+ * @val64 : Value read from adapter status register.
+ * @flag : indicates if the adapter enable bit was ever written once
+ * before.
+ * Description: Returns whether the H/W is ready to go or not. Depending
+ * on whether adapter enable bit was written or not the comparison
+ * differs and the calling function passes the input argument flag to
+ * indicate this.
+ * Return: 1 If xena is quiescence
+ * 0 If Xena is not quiescence
*/
+
static int verify_xena_quiescence(u64 val64, int flag)
{
int ret = 0;
@@ -1122,11 +1400,15 @@
return ret;
}
-/*
+/**
+ * fix_mac_address - Fix for Mac addr problem on Alpha platforms
+ * @sp: Pointer to device specifc structure
+ * Description :
* New procedure to clear mac address reading problems on Alpha platforms
*
*/
-void FixMacAddress(nic_t * sp)
+
+void fix_mac_address(nic_t * sp)
{
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
u64 val64;
@@ -1138,19 +1420,20 @@
}
}
-/*
- * Input Arguments:
- * device private variable.
- * Return Value:
- * SUCCESS on success and -1 on failure.
+/**
+ * start_nic - Turns the device on
+ * @nic : device private variable.
* Description:
- * This function actually turns the device on. Before this
- * function is called, all Registers are configured from their reset states
+ * This function actually turns the device on. Before this function is
+ * called,all Registers are configured from their reset states
* and shared memory is allocated but the NIC is still quiescent. On
* calling this function, the device interrupts are cleared and the NIC is
* literally switched on by writing into the adapter control register.
+ * Return Value:
+ * SUCCESS on success and -1 on failure.
*/
-static int startNic(struct s2io_nic *nic)
+
+static int start_nic(struct s2io_nic *nic)
{
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
struct net_device *dev = nic->dev;
@@ -1169,17 +1452,29 @@
&bar0->prc_rxd0_n[i]);
val64 = readq(&bar0->prc_ctrl_n[i]);
+#ifndef CONFIG_2BUFF_MODE
val64 |= PRC_CTRL_RC_ENABLED;
+#else
+ val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
+#endif
writeq(val64, &bar0->prc_ctrl_n[i]);
}
- /* Enabling MC-RLDRAM. After enabling the device, we timeout
+#ifdef CONFIG_2BUFF_MODE
+ /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
+ val64 = readq(&bar0->rx_pa_cfg);
+ val64 |= RX_PA_CFG_IGNORE_L2_ERR;
+ writeq(val64, &bar0->rx_pa_cfg);
+#endif
+
+ /*
+ * Enabling MC-RLDRAM. After enabling the device, we timeout
* for around 100ms, which is approximately the time required
* for the device to be ready for operation.
*/
val64 = readq(&bar0->mc_rldram_mrs);
val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
- writeq(val64, &bar0->mc_rldram_mrs);
+ SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
val64 = readq(&bar0->mc_rldram_mrs);
set_current_state(TASK_UNINTERRUPTIBLE);
@@ -1190,14 +1485,16 @@
val64 &= ~ADAPTER_ECC_EN;
writeq(val64, &bar0->adapter_control);
- /* Clearing any possible Link state change interrupts that
+ /*
+ * Clearing any possible Link state change interrupts that
* could have popped up just before Enabling the card.
*/
val64 = readq(&bar0->mac_rmac_err_reg);
if (val64)
writeq(val64, &bar0->mac_rmac_err_reg);
- /* Verify if the device is ready to be enabled, if so enable
+ /*
+ * Verify if the device is ready to be enabled, if so enable
* it.
*/
val64 = readq(&bar0->adapter_status);
@@ -1211,9 +1508,10 @@
/* Enable select interrupts */
interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR |
RX_MAC_INTR;
- en_dis_able_NicIntrs(nic, interruptible, ENABLE_INTRS);
+ en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
- /* With some switches, link might be already up at this point.
+ /*
+ * With some switches, link might be already up at this point.
* Because of this weird behavior, when we enable laser,
* we may not get link. We need to handle this. We cannot
* figure out which switch is misbehaving. So we are forced to
@@ -1240,82 +1538,74 @@
* force link down. Since link is already up, we will get
* link state change interrupt after this reset
*/
- writeq(0x8007051500000000ULL, &bar0->dtx_control);
+ SPECIAL_REG_WRITE(0x80010515001E0000ULL, &bar0->dtx_control, UF);
val64 = readq(&bar0->dtx_control);
- writeq(0x80070515000000E0ULL, &bar0->dtx_control);
+ udelay(50);
+ SPECIAL_REG_WRITE(0x80010515001E00E0ULL, &bar0->dtx_control, UF);
val64 = readq(&bar0->dtx_control);
- writeq(0x80070515001F00E4ULL, &bar0->dtx_control);
+ udelay(50);
+ SPECIAL_REG_WRITE(0x80070515001F00E4ULL, &bar0->dtx_control, UF);
val64 = readq(&bar0->dtx_control);
+ udelay(50);
return SUCCESS;
}
-/*
- * Input Arguments:
- * nic - device private variable.
- * Return Value:
- * void.
+/**
+ * free_tx_buffers - Free all queued Tx buffers
+ * @nic : device private variable.
* Description:
- * Free all queued Tx buffers.
- */
-void freeTxBuffers(struct s2io_nic *nic)
+ * Free all queued Tx buffers.
+ * Return Value: void
+*/
+
+void free_tx_buffers(struct s2io_nic *nic)
{
struct net_device *dev = nic->dev;
struct sk_buff *skb;
TxD_t *txdp;
int i, j;
-#if DEBUG_ON
- int cnt = 0;
-#endif
mac_info_t *mac_control;
struct config_param *config;
+ int cnt = 0;
mac_control = &nic->mac_control;
config = &nic->config;
for (i = 0; i < config->TxFIFONum; i++) {
- for (j = 0; j < config->TxCfg[i].FifoLen - 1; j++) {
- txdp = mac_control->txdl_start[i] +
- (config->MaxTxDs * j);
-
- if (!(txdp->Control_1 & TXD_LIST_OWN_XENA)) {
- /* If owned by host, ignore */
- continue;
- }
+ for (j = 0; j < config->tx_cfg[i].FifoLen - 1; j++) {
+ txdp = (TxD_t *) nic->list_info[i][j].
+ list_virt_addr;
skb =
(struct sk_buff *) ((unsigned long) txdp->
Host_Control);
if (skb == NULL) {
- DBG_PRINT(ERR_DBG, "%s: NULL skb ",
- dev->name);
- DBG_PRINT(ERR_DBG, "in Tx Int\n");
- return;
+ memset(txdp, 0, sizeof(TxD_t));
+ continue;
}
-#if DEBUG_ON
- cnt++;
-#endif
dev_kfree_skb(skb);
memset(txdp, 0, sizeof(TxD_t));
+ cnt++;
}
-#if DEBUG_ON
DBG_PRINT(INTR_DBG,
"%s:forcibly freeing %d skbs on FIFO%d\n",
dev->name, cnt, i);
-#endif
+ mac_control->tx_curr_get_info[i].offset = 0;
+ mac_control->tx_curr_put_info[i].offset = 0;
}
}
-/*
- * Input Arguments:
- * nic - device private variable.
- * Return Value:
+/**
+ * stop_nic - To stop the nic
+ * @nic ; device private variable.
+ * Description:
+ * This function does exactly the opposite of what the start_nic()
+ * function does. This function is called to stop the device.
+ * Return Value:
* void.
- * Description:
- * This function does exactly the opposite of what the startNic()
- * function does. This function is called to stop
- * the device.
*/
-static void stopNic(struct s2io_nic *nic)
+
+static void stop_nic(struct s2io_nic *nic)
{
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
register u64 val64 = 0;
@@ -1326,12 +1616,12 @@
mac_control = &nic->mac_control;
config = &nic->config;
-/* Disable all interrupts */
+ /* Disable all interrupts */
interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR |
RX_MAC_INTR;
- en_dis_able_NicIntrs(nic, interruptible, DISABLE_INTRS);
+ en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
-/* Disable PRCs */
+ /* Disable PRCs */
for (i = 0; i < config->RxRingNum; i++) {
val64 = readq(&bar0->prc_ctrl_n[i]);
val64 &= ~((u64) PRC_CTRL_RC_ENABLED);
@@ -1339,11 +1629,10 @@
}
}
-/*
- * Input Arguments:
- * device private variable
- * Return Value:
- * SUCCESS on success or an appropriate -ve value on failure.
+/**
+ * fill_rx_buffers - Allocates the Rx side skbs
+ * @nic: device private variable
+ * @ring_no: ring number
* Description:
* The function allocates Rx side skbs and puts the physical
* address of these buffers into the RxD buffer pointers, so that the NIC
@@ -1354,9 +1643,13 @@
* 3. Five buffer modes.
* Each mode defines how many fragments the received frame will be split
* up into by the NIC. The frame is split into L3 header, L4 Header,
- * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
- * is split into 3 fragments. As of now only single buffer mode is supported.
+ * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
+ * is split into 3 fragments. As of now only single buffer mode is
+ * supported.
+ * Return Value:
+ * SUCCESS on success or an appropriate -ve value on failure.
*/
+
int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
{
struct net_device *dev = nic->dev;
@@ -1369,6 +1662,16 @@
atomic_read(&nic->rx_bufs_left[ring_no]);
mac_info_t *mac_control;
struct config_param *config;
+#ifdef CONFIG_2BUFF_MODE
+ RxD_t *rxdpnext;
+ int nextblk;
+ u64 tmp;
+ buffAdd_t *ba;
+ dma_addr_t rxdpphys;
+#endif
+#ifndef CONFIG_S2IO_NAPI
+ unsigned long flags;
+#endif
mac_control = &nic->mac_control;
config = &nic->config;
@@ -1390,8 +1693,13 @@
block_index;
off = mac_control->rx_curr_put_info[ring_no].offset;
off1 = mac_control->rx_curr_get_info[ring_no].offset;
+#ifndef CONFIG_2BUFF_MODE
offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off;
offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1;
+#else
+ offset = block_no * (MAX_RXDS_PER_BLOCK) + off;
+ offset1 = block_no1 * (MAX_RXDS_PER_BLOCK) + off1;
+#endif
rxdp = nic->rx_blocks[ring_no][block_no].
block_virt_addr + off;
@@ -1400,7 +1708,7 @@
DBG_PRINT(INTR_DBG, " info equated\n");
goto end;
}
-
+#ifndef CONFIG_2BUFF_MODE
if (rxdp->Control_1 == END_OF_BLOCK) {
mac_control->rx_curr_put_info[ring_no].
block_index++;
@@ -1412,25 +1720,85 @@
off %= (MAX_RXDS_PER_BLOCK + 1);
mac_control->rx_curr_put_info[ring_no].offset =
off;
- /*rxdp = nic->rx_blocks[ring_no][block_no].
- block_virt_addr + off; */
rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2);
DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
dev->name, rxdp);
}
+#ifndef CONFIG_S2IO_NAPI
+ spin_lock_irqsave(&nic->put_lock, flags);
+ nic->put_pos = (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off;
+ spin_unlock_irqrestore(&nic->put_lock, flags);
+#endif
+#else
+ if (rxdp->Host_Control == END_OF_BLOCK) {
+ mac_control->rx_curr_put_info[ring_no].
+ block_index++;
+ mac_control->rx_curr_put_info[ring_no].
+ block_index %= nic->block_count[ring_no];
+ block_no = mac_control->rx_curr_put_info
+ [ring_no].block_index;
+ off = 0;
+ DBG_PRINT(INTR_DBG, "%s: block%d at: 0x%llx\n",
+ dev->name, block_no,
+ (unsigned long long) rxdp->Control_1);
+ mac_control->rx_curr_put_info[ring_no].offset =
+ off;
+ rxdp = nic->rx_blocks[ring_no][block_no].
+ block_virt_addr;
+ }
+#ifndef CONFIG_S2IO_NAPI
+ spin_lock_irqsave(&nic->put_lock, flags);
+ nic->put_pos = (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off;
+ spin_unlock_irqrestore(&nic->put_lock, flags);
+#endif
+#endif
- if (rxdp->Control_1 & RXD_OWN_XENA) {
+#ifndef CONFIG_2BUFF_MODE
+ if (rxdp->Control_1 & RXD_OWN_XENA)
+#else
+ if (rxdp->Control_2 & BIT(0))
+#endif
+ {
mac_control->rx_curr_put_info[ring_no].
offset = off;
goto end;
}
+#ifdef CONFIG_2BUFF_MODE
+ /*
+ * RxDs Spanning cache lines will be replenished only
+ * if the succeeding RxD is also owned by Host. It
+ * will always be the ((8*i)+3) and ((8*i)+6)
+ * descriptors for the 48 byte descriptor. The offending
+ * decsriptor is of-course the 3rd descriptor.
+ */
+ rxdpphys = nic->rx_blocks[ring_no][block_no].
+ block_dma_addr + (off * sizeof(RxD_t));
+ if (((u64) (rxdpphys)) % 128 > 80) {
+ rxdpnext = nic->rx_blocks[ring_no][block_no].
+ block_virt_addr + (off + 1);
+ if (rxdpnext->Host_Control == END_OF_BLOCK) {
+ nextblk = (block_no + 1) %
+ (nic->block_count[ring_no]);
+ rxdpnext = nic->rx_blocks[ring_no]
+ [nextblk].block_virt_addr;
+ }
+ if (rxdpnext->Control_2 & BIT(0))
+ goto end;
+ }
+#endif
+#ifndef CONFIG_2BUFF_MODE
skb = dev_alloc_skb(size + HEADER_ALIGN_LAYER_3);
+#else
+ skb = dev_alloc_skb(dev->mtu + ALIGN_SIZE +
+ /*BUF0_LEN + */ 22);
+#endif
if (!skb) {
DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
return -ENOMEM;
}
+#ifndef CONFIG_2BUFF_MODE
skb_reserve(skb, HEADER_ALIGN_LAYER_3);
memset(rxdp, 0, sizeof(RxD_t));
rxdp->Buffer0_ptr = pci_map_single
@@ -1442,6 +1810,33 @@
off++;
off %= (MAX_RXDS_PER_BLOCK + 1);
mac_control->rx_curr_put_info[ring_no].offset = off;
+#else
+ ba = &nic->ba[ring_no][block_no][off];
+ tmp = (u64) skb->data;
+ tmp += ALIGN_SIZE;
+ tmp &= ~ALIGN_SIZE;
+ skb->data = (void *) tmp;
+
+ memset(rxdp, 0, sizeof(RxD_t));
+ rxdp->Buffer2_ptr = pci_map_single
+ (nic->pdev, skb->data, dev->mtu + 22,
+ PCI_DMA_FROMDEVICE);
+ rxdp->Buffer0_ptr =
+ pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
+ PCI_DMA_FROMDEVICE);
+ rxdp->Buffer1_ptr =
+ pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,
+ PCI_DMA_FROMDEVICE);
+
+ rxdp->Control_2 = SET_BUFFER2_SIZE(dev->mtu + 22);
+ rxdp->Control_2 |= SET_BUFFER0_SIZE(BUF0_LEN);
+ rxdp->Control_2 |= SET_BUFFER1_SIZE(1); /* dummy. */
+ rxdp->Control_2 |= BIT(0); /* Set Buffer_Empty bit. */
+ rxdp->Host_Control = (u64) ((unsigned long) (skb));
+ rxdp->Control_1 |= RXD_OWN_XENA;
+ off++;
+ mac_control->rx_curr_put_info[ring_no].offset = off;
+#endif
atomic_inc(&nic->rx_bufs_left[ring_no]);
alloc_tab++;
}
@@ -1450,15 +1845,16 @@
return SUCCESS;
}
-/*
- * Input Arguments:
- * device private variable.
- * Return Value:
- * NONE.
+/**
+ * free_rx_buffers - Frees all Rx buffers
+ * @sp: device private variable.
* Description:
* This function will free all Rx buffers allocated by host.
+ * Return Value:
+ * NONE.
*/
-static void freeRxBuffers(struct s2io_nic *sp)
+
+static void free_rx_buffers(struct s2io_nic *sp)
{
struct net_device *dev = sp->dev;
int i, j, blk = 0, off, buf_cnt = 0;
@@ -1466,15 +1862,19 @@
struct sk_buff *skb;
mac_info_t *mac_control;
struct config_param *config;
+#ifdef CONFIG_2BUFF_MODE
+ buffAdd_t *ba;
+#endif
mac_control = &sp->mac_control;
config = &sp->config;
for (i = 0; i < config->RxRingNum; i++) {
- for (j = 0, blk = 0; j < config->RxCfg[i].NumRxd; j++) {
+ for (j = 0, blk = 0; j < config->rx_cfg[i].NumRxd; j++) {
off = j % (MAX_RXDS_PER_BLOCK + 1);
rxdp = sp->rx_blocks[i][blk].block_virt_addr + off;
+#ifndef CONFIG_2BUFF_MODE
if (rxdp->Control_1 == END_OF_BLOCK) {
rxdp =
(RxD_t *) ((unsigned long) rxdp->
@@ -1482,11 +1882,23 @@
j++;
blk++;
}
+#else
+ if (rxdp->Host_Control == END_OF_BLOCK) {
+ blk++;
+ continue;
+ }
+#endif
+
+ if (!(rxdp->Control_1 & RXD_OWN_XENA)) {
+ memset(rxdp, 0, sizeof(RxD_t));
+ continue;
+ }
skb =
(struct sk_buff *) ((unsigned long) rxdp->
Host_Control);
if (skb) {
+#ifndef CONFIG_2BUFF_MODE
pci_unmap_single(sp->pdev, (dma_addr_t)
rxdp->Buffer0_ptr,
dev->mtu +
@@ -1494,6 +1906,21 @@
+ HEADER_802_2_SIZE +
HEADER_SNAP_SIZE,
PCI_DMA_FROMDEVICE);
+#else
+ ba = &sp->ba[i][blk][off];
+ pci_unmap_single(sp->pdev, (dma_addr_t)
+ rxdp->Buffer0_ptr,
+ BUF0_LEN,
+ PCI_DMA_FROMDEVICE);
+ pci_unmap_single(sp->pdev, (dma_addr_t)
+ rxdp->Buffer1_ptr,
+ BUF1_LEN,
+ PCI_DMA_FROMDEVICE);
+ pci_unmap_single(sp->pdev, (dma_addr_t)
+ rxdp->Buffer2_ptr,
+ dev->mtu + 22,
+ PCI_DMA_FROMDEVICE);
+#endif
dev_kfree_skb(skb);
atomic_dec(&sp->rx_bufs_left[i]);
buf_cnt++;
@@ -1510,18 +1937,19 @@
}
}
-/*
- * Input Argument:
- * dev - pointer to the device structure.
- * budget - The number of packets that were budgeted to be processed during
- * one pass through the 'Poll" function.
- * Return value:
- * 0 on success and 1 if there are No Rx packets to be processed.
- * Description:
- * Comes into picture only if NAPI support has been incorporated. It does
- * the same thing that rxIntrHandler does, but not in a interrupt context
- * also It will process only a given number of packets.
+/**
+ * s2io_poll - Rx interrupt handler for NAPI support
+ * @dev : pointer to the device structure.
+ * @budget : The number of packets that were budgeted to be processed
+ * during one pass through the 'Poll" function.
+ * Description:
+ * Comes into picture only if NAPI support has been incorporated. It does
+ * the same thing that rx_intr_handler does, but not in a interrupt context
+ * also It will process only a given number of packets.
+ * Return value:
+ * 0 on success and 1 if there are No Rx packets to be processed.
*/
+
#ifdef CONFIG_S2IO_NAPI
static int s2io_poll(struct net_device *dev, int *budget)
{
@@ -1529,13 +1957,18 @@
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
int pkts_to_process = *budget, pkt_cnt = 0;
register u64 val64 = 0;
- rx_curr_get_info_t offset_info;
- int i, block_no;
+ rx_curr_get_info_t get_info, put_info;
+ int i, get_block, put_block, get_offset, put_offset, ring_bufs;
+#ifndef CONFIG_2BUFF_MODE
u16 val16, cksum;
+#endif
struct sk_buff *skb;
RxD_t *rxdp;
mac_info_t *mac_control;
struct config_param *config;
+#ifdef CONFIG_2BUFF_MODE
+ buffAdd_t *ba;
+#endif
mac_control = &nic->mac_control;
config = &nic->config;
@@ -1547,29 +1980,47 @@
writeq(val64, &bar0->rx_traffic_int);
for (i = 0; i < config->RxRingNum; i++) {
- if (--pkts_to_process < 0) {
- goto no_rx;
- }
- offset_info = mac_control->rx_curr_get_info[i];
- block_no = offset_info.block_index;
- rxdp = nic->rx_blocks[i][block_no].block_virt_addr +
- offset_info.offset;
- while (!(rxdp->Control_1 & RXD_OWN_XENA)) {
+ get_info = mac_control->rx_curr_get_info[i];
+ get_block = get_info.block_index;
+ put_info = mac_control->rx_curr_put_info[i];
+ put_block = put_info.block_index;
+ ring_bufs = config->rx_cfg[i].NumRxd;
+ rxdp = nic->rx_blocks[i][get_block].block_virt_addr +
+ get_info.offset;
+#ifndef CONFIG_2BUFF_MODE
+ get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
+ get_info.offset;
+#ifndef CONFIG_S2IO_NAPI
+ spin_lock(&nic->put_lock);
+ put_offset = nic->put_pos;
+ spin_unlock(&nic->put_lock);
+#else
+ put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
+ put_info.offset;
+#endif
+ while ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
+ (((get_offset + 1) % ring_bufs) != put_offset)) {
+ if (--pkts_to_process < 0) {
+ goto no_rx;
+ }
if (rxdp->Control_1 == END_OF_BLOCK) {
rxdp =
(RxD_t *) ((unsigned long) rxdp->
Control_2);
- offset_info.offset++;
- offset_info.offset %=
+ get_info.offset++;
+ get_info.offset %=
(MAX_RXDS_PER_BLOCK + 1);
- block_no++;
- block_no %= nic->block_count[i];
+ get_block++;
+ get_block %= nic->block_count[i];
mac_control->rx_curr_get_info[i].
- offset = offset_info.offset;
+ offset = get_info.offset;
mac_control->rx_curr_get_info[i].
- block_index = block_no;
+ block_index = get_block;
continue;
}
+ get_offset =
+ (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
+ get_info.offset;
skb =
(struct sk_buff *) ((unsigned long) rxdp->
Host_Control);
@@ -1577,7 +2028,7 @@
DBG_PRINT(ERR_DBG, "%s: The skb is ",
dev->name);
DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
- return 0;
+ goto no_rx;
}
val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
val16 = (u16) (val64 >> 48);
@@ -1589,97 +2040,192 @@
HEADER_802_2_SIZE +
HEADER_SNAP_SIZE,
PCI_DMA_FROMDEVICE);
- rxOsmHandler(nic, val16, rxdp, i);
+ rx_osm_handler(nic, val16, rxdp, i);
pkt_cnt++;
- offset_info.offset++;
- offset_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
+ get_info.offset++;
+ get_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
rxdp =
- nic->rx_blocks[i][block_no].block_virt_addr +
- offset_info.offset;
+ nic->rx_blocks[i][get_block].block_virt_addr +
+ get_info.offset;
mac_control->rx_curr_get_info[i].offset =
- offset_info.offset;
+ get_info.offset;
}
- }
- if (!pkt_cnt)
- pkt_cnt = 1;
-
- for (i = 0; i < config->RxRingNum; i++)
- fill_rx_buffers(nic, i);
+#else
+ get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
+ get_info.offset;
+#ifndef CONFIG_S2IO_NAPI
+ spin_lock(&nic->put_lock);
+ put_offset = nic->put_pos;
+ spin_unlock(&nic->put_lock);
+#else
+ put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
+ put_info.offset;
+#endif
+ while (((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
+ !(rxdp->Control_2 & BIT(0))) &&
+ (((get_offset + 1) % ring_bufs) != put_offset)) {
+ if (--pkts_to_process < 0) {
+ goto no_rx;
+ }
+ skb = (struct sk_buff *) ((unsigned long)
+ rxdp->Host_Control);
+ if (skb == NULL) {
+ DBG_PRINT(ERR_DBG, "%s: The skb is ",
+ dev->name);
+ DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
+ goto no_rx;
+ }
+
+ pci_unmap_single(nic->pdev, (dma_addr_t)
+ rxdp->Buffer0_ptr,
+ BUF0_LEN, PCI_DMA_FROMDEVICE);
+ pci_unmap_single(nic->pdev, (dma_addr_t)
+ rxdp->Buffer1_ptr,
+ BUF1_LEN, PCI_DMA_FROMDEVICE);
+ pci_unmap_single(nic->pdev, (dma_addr_t)
+ rxdp->Buffer2_ptr,
+ dev->mtu + 22,
+ PCI_DMA_FROMDEVICE);
+ ba = &nic->ba[i][get_block][get_info.offset];
+
+ rx_osm_handler(nic, rxdp, i, ba);
+
+ get_info.offset++;
+ mac_control->rx_curr_get_info[i].offset =
+ get_info.offset;
+ rxdp =
+ nic->rx_blocks[i][get_block].block_virt_addr +
+ get_info.offset;
+
+ if (get_info.offset &&
+ (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
+ get_info.offset = 0;
+ mac_control->rx_curr_get_info[i].
+ offset = get_info.offset;
+ get_block++;
+ get_block %= nic->block_count[i];
+ mac_control->rx_curr_get_info[i].
+ block_index = get_block;
+ rxdp =
+ nic->rx_blocks[i][get_block].
+ block_virt_addr;
+ }
+ get_offset =
+ (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
+ get_info.offset;
+ pkt_cnt++;
+ }
+#endif
+ }
+ if (!pkt_cnt)
+ pkt_cnt = 1;
dev->quota -= pkt_cnt;
*budget -= pkt_cnt;
netif_rx_complete(dev);
-/* Re enable the Rx interrupts. */
- en_dis_able_NicIntrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
+ for (i = 0; i < config->RxRingNum; i++) {
+ if (fill_rx_buffers(nic, i) == -ENOMEM) {
+ DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
+ DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
+ break;
+ }
+ }
+ /* Re enable the Rx interrupts. */
+ en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
return 0;
no_rx:
- for (i = 0; i < config->RxRingNum; i++)
- fill_rx_buffers(nic, i);
dev->quota -= pkt_cnt;
*budget -= pkt_cnt;
+
+ for (i = 0; i < config->RxRingNum; i++) {
+ if (fill_rx_buffers(nic, i) == -ENOMEM) {
+ DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
+ DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
+ break;
+ }
+ }
return 1;
}
#else
-/*
- * Input Arguments:
- * device private variable.
- * Return Value:
- * NONE.
+/**
+ * rx_intr_handler - Rx interrupt handler
+ * @nic: device private variable.
* Description:
- * If the interrupt is because of a received frame or if the
- * receive ring contains fresh as yet un-processed frames, this function is
+ * If the interrupt is because of a received frame or if the
+ * receive ring contains fresh as yet un-processed frames,this function is
* called. It picks out the RxD at which place the last Rx processing had
* stopped and sends the skb to the OSM's Rx handler and then increments
* the offset.
+ * Return Value:
+ * NONE.
*/
-static void rxIntrHandler(struct s2io_nic *nic)
+
+static void rx_intr_handler(struct s2io_nic *nic)
{
struct net_device *dev = (struct net_device *) nic->dev;
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
- rx_curr_get_info_t offset_info;
+ rx_curr_get_info_t get_info, put_info;
RxD_t *rxdp;
struct sk_buff *skb;
+#ifndef CONFIG_2BUFF_MODE
u16 val16, cksum;
+#endif
register u64 val64 = 0;
- int i, block_no;
+ int get_block, get_offset, put_block, put_offset, ring_bufs;
+ int i, pkt_cnt = 0;
mac_info_t *mac_control;
struct config_param *config;
+#ifdef CONFIG_2BUFF_MODE
+ buffAdd_t *ba;
+#endif
mac_control = &nic->mac_control;
config = &nic->config;
-#if DEBUG_ON
- nic->rxint_cnt++;
-#endif
-
-/* rx_traffic_int reg is an R1 register, hence we read and write back
- * the samevalue in the register to clear it.
- */
+ /*
+ * rx_traffic_int reg is an R1 register, hence we read and write back
+ * the samevalue in the register to clear it.
+ */
val64 = readq(&bar0->rx_traffic_int);
writeq(val64, &bar0->rx_traffic_int);
for (i = 0; i < config->RxRingNum; i++) {
- offset_info = mac_control->rx_curr_get_info[i];
- block_no = offset_info.block_index;
- rxdp = nic->rx_blocks[i][block_no].block_virt_addr +
- offset_info.offset;
- while (!(rxdp->Control_1 & RXD_OWN_XENA)) {
+ get_info = mac_control->rx_curr_get_info[i];
+ get_block = get_info.block_index;
+ put_info = mac_control->rx_curr_put_info[i];
+ put_block = put_info.block_index;
+ ring_bufs = config->rx_cfg[i].NumRxd;
+ rxdp = nic->rx_blocks[i][get_block].block_virt_addr +
+ get_info.offset;
+#ifndef CONFIG_2BUFF_MODE
+ get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
+ get_info.offset;
+#ifndef CONFIG_S2IO_NAPI
+ spin_lock(&nic->put_lock);
+ put_offset = nic->put_pos;
+ spin_unlock(&nic->put_lock);
+#endif
+ while ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
+ (((get_offset + 1) % ring_bufs) != put_offset)) {
if (rxdp->Control_1 == END_OF_BLOCK) {
rxdp = (RxD_t *) ((unsigned long)
rxdp->Control_2);
- offset_info.offset++;
- offset_info.offset %=
+ get_info.offset++;
+ get_info.offset %=
(MAX_RXDS_PER_BLOCK + 1);
- block_no++;
- block_no %= nic->block_count[i];
+ get_block++;
+ get_block %= nic->block_count[i];
mac_control->rx_curr_get_info[i].
- offset = offset_info.offset;
+ offset = get_info.offset;
mac_control->rx_curr_get_info[i].
- block_index = block_no;
+ block_index = get_block;
continue;
}
+ get_offset =
+ (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
+ get_info.offset;
skb = (struct sk_buff *) ((unsigned long)
rxdp->Host_Control);
if (skb == NULL) {
@@ -1698,35 +2244,104 @@
HEADER_802_2_SIZE +
HEADER_SNAP_SIZE,
PCI_DMA_FROMDEVICE);
- rxOsmHandler(nic, val16, rxdp, i);
- offset_info.offset++;
- offset_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
+ rx_osm_handler(nic, val16, rxdp, i);
+ get_info.offset++;
+ get_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
rxdp =
- nic->rx_blocks[i][block_no].block_virt_addr +
- offset_info.offset;
+ nic->rx_blocks[i][get_block].block_virt_addr +
+ get_info.offset;
+ mac_control->rx_curr_get_info[i].offset =
+ get_info.offset;
+ pkt_cnt++;
+ if ((indicate_max_pkts)
+ && (pkt_cnt > indicate_max_pkts))
+ break;
+ }
+#else
+ get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
+ get_info.offset;
+#ifndef CONFIG_S2IO_NAPI
+ spin_lock(&nic->put_lock);
+ put_offset = nic->put_pos;
+ spin_unlock(&nic->put_lock);
+#endif
+ while (((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
+ !(rxdp->Control_2 & BIT(0))) &&
+ (((get_offset + 1) % ring_bufs) != put_offset)) {
+ skb = (struct sk_buff *) ((unsigned long)
+ rxdp->Host_Control);
+ if (skb == NULL) {
+ DBG_PRINT(ERR_DBG, "%s: The skb is ",
+ dev->name);
+ DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
+ return;
+ }
+
+ pci_unmap_single(nic->pdev, (dma_addr_t)
+ rxdp->Buffer0_ptr,
+ BUF0_LEN, PCI_DMA_FROMDEVICE);
+ pci_unmap_single(nic->pdev, (dma_addr_t)
+ rxdp->Buffer1_ptr,
+ BUF1_LEN, PCI_DMA_FROMDEVICE);
+ pci_unmap_single(nic->pdev, (dma_addr_t)
+ rxdp->Buffer2_ptr,
+ dev->mtu + 22,
+ PCI_DMA_FROMDEVICE);
+ ba = &nic->ba[i][get_block][get_info.offset];
+
+ rx_osm_handler(nic, rxdp, i, ba);
+
+ get_info.offset++;
mac_control->rx_curr_get_info[i].offset =
- offset_info.offset;
+ get_info.offset;
+ rxdp =
+ nic->rx_blocks[i][get_block].block_virt_addr +
+ get_info.offset;
+
+ if (get_info.offset &&
+ (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
+ get_info.offset = 0;
+ mac_control->rx_curr_get_info[i].
+ offset = get_info.offset;
+ get_block++;
+ get_block %= nic->block_count[i];
+ mac_control->rx_curr_get_info[i].
+ block_index = get_block;
+ rxdp =
+ nic->rx_blocks[i][get_block].
+ block_virt_addr;
+ }
+ get_offset =
+ (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
+ get_info.offset;
+ pkt_cnt++;
+ if ((indicate_max_pkts)
+ && (pkt_cnt > indicate_max_pkts))
+ break;
}
+#endif
+ if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
+ break;
}
}
#endif
-
-/*
- * Input Arguments:
- * device private variable
- * Return Value:
- * NONE
+/**
+ * tx_intr_handler - Transmit interrupt handler
+ * @nic : device private variable
* Description:
* If an interrupt was raised to indicate DMA complete of the
- * Tx packet, this function is called. It identifies the last TxD whose buffer
- * was freed and frees all skbs whose data have already DMA'ed into the NICs
- * internal memory.
+ * Tx packet, this function is called. It identifies the last TxD
+ * whose buffer was freed and frees all skbs whose data have already
+ * DMA'ed into the NICs internal memory.
+ * Return Value:
+ * NONE
*/
-static void txIntrHandler(struct s2io_nic *nic)
+
+static void tx_intr_handler(struct s2io_nic *nic)
{
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
struct net_device *dev = (struct net_device *) nic->dev;
- tx_curr_get_info_t offset_info, offset_info1;
+ tx_curr_get_info_t get_info, put_info;
struct sk_buff *skb;
TxD_t *txdlp;
register u64 val64 = 0;
@@ -1734,27 +2349,24 @@
u16 j, frg_cnt;
mac_info_t *mac_control;
struct config_param *config;
-#if DEBUG_ON
- int cnt = 0;
- nic->txint_cnt++;
-#endif
mac_control = &nic->mac_control;
config = &nic->config;
- /* tx_traffic_int reg is an R1 register, hence we read and write
+ /*
+ * tx_traffic_int reg is an R1 register, hence we read and write
* back the samevalue in the register to clear it.
*/
val64 = readq(&bar0->tx_traffic_int);
writeq(val64, &bar0->tx_traffic_int);
for (i = 0; i < config->TxFIFONum; i++) {
- offset_info = mac_control->tx_curr_get_info[i];
- offset_info1 = mac_control->tx_curr_put_info[i];
- txdlp = mac_control->txdl_start[i] +
- (config->MaxTxDs * offset_info.offset);
+ get_info = mac_control->tx_curr_get_info[i];
+ put_info = mac_control->tx_curr_put_info[i];
+ txdlp = (TxD_t *) nic->list_info[i][get_info.offset].
+ list_virt_addr;
while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
- (offset_info.offset != offset_info1.offset) &&
+ (get_info.offset != put_info.offset) &&
(txdlp->Host_Control)) {
/* Check for TxD errors */
if (txdlp->Control_1 & TXD_T_CODE) {
@@ -1802,23 +2414,15 @@
/* Updating the statistics block */
nic->stats.tx_packets++;
nic->stats.tx_bytes += skb->len;
-#if DEBUG_ON
- nic->txpkt_bytes += skb->len;
- cnt++;
-#endif
dev_kfree_skb_irq(skb);
- offset_info.offset++;
- offset_info.offset %= offset_info.fifo_len + 1;
- txdlp = mac_control->txdl_start[i] +
- (config->MaxTxDs * offset_info.offset);
+ get_info.offset++;
+ get_info.offset %= get_info.fifo_len + 1;
+ txdlp = (TxD_t *) nic->list_info[i]
+ [get_info.offset].list_virt_addr;
mac_control->tx_curr_get_info[i].offset =
- offset_info.offset;
+ get_info.offset;
}
-#if DEBUG_ON
- DBG_PRINT(INTR_DBG, "%s: freed %d Tx Pkts\n", dev->name,
- cnt);
-#endif
}
spin_lock(&nic->tx_lock);
@@ -1827,67 +2431,78 @@
spin_unlock(&nic->tx_lock);
}
-/*
- * Input Arguments:
- * device private variable
- * Return Value:
+/**
+ * alarm_intr_handler - Alarm Interrrupt handler
+ * @nic: device private variable
+ * Description: If the interrupt was neither because of Rx packet or Tx
+ * complete, this function is called. If the interrupt was to indicate
+ * a loss of link, the OSM link status handler is invoked for any other
+ * alarm interrupt the block that raised the interrupt is displayed
+ * and a H/W reset is issued.
+ * Return Value:
* NONE
- * Description:
- * If the interrupt was neither because of Rx packet or Tx
- * complete, this function is called. If the interrupt was to indicate a loss
- * of link, the OSM link status handler is invoked for any other alarm
- * interrupt the block that raised the interrupt is displayed and a H/W reset
- * is issued.
- */
-static void alarmIntrHandler(struct s2io_nic *nic)
+*/
+
+static void alarm_intr_handler(struct s2io_nic *nic)
{
struct net_device *dev = (struct net_device *) nic->dev;
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
register u64 val64 = 0, err_reg = 0;
-
/* Handling link status change error Intr */
err_reg = readq(&bar0->mac_rmac_err_reg);
+ writeq(err_reg, &bar0->mac_rmac_err_reg);
if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
schedule_work(&nic->set_link_task);
}
- /* Handling SERR errors by stopping device Xmit queue and forcing
- * a H/W reset.
- */
+ /* In case of a serious error, the device will be Reset. */
val64 = readq(&bar0->serr_source);
if (val64 & SERR_SOURCE_ANY) {
DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
DBG_PRINT(ERR_DBG, "serious error!!\n");
- netif_stop_queue(dev);
+ schedule_work(&nic->rst_timer_task);
+ }
+
+ /*
+ * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
+ * Error occurs, the adapter will be recycled by disabling the
+ * adapter enable bit and enabling it again after the device
+ * becomes Quiescent.
+ */
+ val64 = readq(&bar0->pcc_err_reg);
+ writeq(val64, &bar0->pcc_err_reg);
+ if (val64 & PCC_FB_ECC_DB_ERR) {
+ u64 ac = readq(&bar0->adapter_control);
+ ac &= ~(ADAPTER_CNTL_EN);
+ writeq(ac, &bar0->adapter_control);
+ ac = readq(&bar0->adapter_control);
+ schedule_work(&nic->set_link_task);
}
-/* Other type of interrupts are not being handled now, TODO*/
+
+ /* Other type of interrupts are not being handled now, TODO */
}
-/*
- * Input Argument:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
+/**
+ * wait_for_cmd_complete - waits for a command to complete.
+ * @sp : private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * Description: Function that waits for a command to Write into RMAC
+ * ADDR DATA registers to be completed and returns either success or
+ * error depending on whether the command was complete or not.
* Return value:
* SUCCESS on success and FAILURE on failure.
- * Description:
- * Function that waits for a command to Write into RMAC ADDR DATA registers
- * to be completed and returns either success or error depending on whether
- * the command was complete or not.
*/
-int waitForCmdComplete(nic_t * sp)
+
+int wait_for_cmd_complete(nic_t * sp)
{
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
int ret = FAILURE, cnt = 0;
u64 val64;
while (TRUE) {
- val64 =
- RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
- | RMAC_ADDR_CMD_MEM_OFFSET(0);
- writeq(val64, &bar0->rmac_addr_cmd_mem);
val64 = readq(&bar0->rmac_addr_cmd_mem);
- if (!val64) {
+ if (!(val64 & RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
ret = SUCCESS;
break;
}
@@ -1900,17 +2515,16 @@
return ret;
}
-/*
- * Input Argument:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
+/**
+ * s2io_reset - Resets the card.
+ * @sp : private member of the device structure.
+ * Description: Function to Reset the card. This function then also
+ * restores the previously saved PCI configuration space registers as
+ * the card reset also resets the Configration space.
* Return value:
- * void.
- * Description:
- * Function to Reset the card. This function then also restores the previously
- * saved PCI configuration space registers as the card reset also resets the
- * Configration space.
+ * void.
*/
+
void s2io_reset(nic_t * sp)
{
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
@@ -1920,7 +2534,8 @@
val64 = SW_RESET_ALL;
writeq(val64, &bar0->sw_reset);
- /* At this stage, if the PCI write is indeed completed, the
+ /*
+ * At this stage, if the PCI write is indeed completed, the
* card is reset and so is the PCI Config space of the device.
* So a read cannot be issued at this stage on any of the
* registers to ensure the write into "sw_reset" register
@@ -1928,18 +2543,16 @@
* Question: Is there any system call that will explicitly force
* all the write commands still pending on the bus to be pushed
* through?
- * As of now I'am just giving a 250ms delay and hoping that the
+ * As of now I'am just giving a 100ms delay and hoping that the
* PCI write to sw_reset register is done by this time.
*/
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(HZ / 4);
+ mdelay(100);
/* Restore the PCI state saved during initializarion. */
pci_restore_state(sp->pdev, sp->config_space);
s2io_init_pci(sp);
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(HZ / 4);
+ mdelay(100);
/* SXE-002: Configure link and activity LED to turn it off */
subid = sp->pdev->subsystem_device;
@@ -1954,29 +2567,31 @@
sp->device_enabled_once = FALSE;
}
-/*
- * Input Argument:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
+/**
+ * s2io_set_swapper - to set the swapper controle on the card
+ * @sp : private member of the device structure,
+ * pointer to the s2io_nic structure.
+ * Description: Function to set the swapper control on the card
+ * correctly depending on the 'endianness' of the system.
* Return value:
* SUCCESS on success and FAILURE on failure.
- * Description:
- * Function to set the swapper control on the card correctly depending on the
- * 'endianness' of the system.
*/
+
int s2io_set_swapper(nic_t * sp)
{
struct net_device *dev = sp->dev;
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
u64 val64;
-/* Set proper endian settings and verify the same by reading the PIF
- * Feed-back register.
- */
+ /*
+ * Set proper endian settings and verify the same by reading
+ * the PIF Feed-back register.
+ */
#ifdef __BIG_ENDIAN
-/* The device by default set to a big endian format, so a big endian
- * driver need not set anything.
- */
+ /*
+ * The device by default set to a big endian format, so a
+ * big endian driver need not set anything.
+ */
writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
val64 = (SWAPPER_CTRL_PIF_R_FE |
SWAPPER_CTRL_PIF_R_SE |
@@ -1995,9 +2610,11 @@
SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
writeq(val64, &bar0->swapper_ctrl);
#else
-/* Initially we enable all bits to make it accessible by the driver,
- * then we selectively enable only those bits that we want to set.
- */
+ /*
+ * Initially we enable all bits to make it accessible by the
+ * driver, then we selectively enable only those bits that
+ * we want to set.
+ */
writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
val64 = (SWAPPER_CTRL_PIF_R_FE |
SWAPPER_CTRL_PIF_R_SE |
@@ -2021,9 +2638,10 @@
writeq(val64, &bar0->swapper_ctrl);
#endif
-/* Verifying if endian settings are accurate by reading a feedback
- * register.
- */
+ /*
+ * Verifying if endian settings are accurate by reading a
+ * feedback register.
+ */
val64 = readq(&bar0->pif_rd_swapper_fb);
if (val64 != 0x0123456789ABCDEFULL) {
/* Endian settings are incorrect, calls for another dekko. */
@@ -2041,17 +2659,18 @@
* Functions defined below concern the OS part of the driver *
* ********************************************************* */
-/*
- * Input Argument:
- * dev - pointer to the device structure.
- * Return value:
- * '0' on success and an appropriate (-)ve integer as defined in errno.h
- * file on failure.
+/**
+ * s2io-open - open entry point of the driver
+ * @dev : pointer to the device structure.
* Description:
* This function is the open entry point of the driver. It mainly calls a
* function to allocate Rx buffers and inserts them into the buffer
* descriptors and then enables the Rx part of the NIC.
+ * Return value:
+ * 0 on success and an appropriate (-)ve integer as defined in errno.h
+ * file on failure.
*/
+
int s2io_open(struct net_device *dev)
{
nic_t *sp = dev->priv;
@@ -2060,18 +2679,21 @@
struct config_param *config;
-/* Make sure you have link off by default every time Nic is initialized*/
+ /*
+ * Make sure you have link off by default every time
+ * Nic is initialized
+ */
netif_carrier_off(dev);
sp->last_link_state = LINK_DOWN;
-/* Initialize the H/W I/O registers */
- if (initNic(sp) != 0) {
+ /* Initialize the H/W I/O registers */
+ if (init_nic(sp) != 0) {
DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
dev->name);
return -ENODEV;
}
-/* After proper initialization of H/W, register ISR */
+ /* After proper initialization of H/W, register ISR */
err =
request_irq((int) sp->irq, s2io_isr, SA_SHIRQ, sp->name, dev);
if (err) {
@@ -2087,12 +2709,13 @@
}
-/* Setting its receive mode */
+ /* Setting its receive mode */
s2io_set_multicast(dev);
-/* Initializing the Rx buffers. For now we are considering only 1 Rx ring
- * and initializing buffers into 1016 RxDs or 8 Rx blocks
- */
+ /*
+ * Initializing the Rx buffers. For now we are considering only 1
+ * Rx ring and initializing buffers into 1016 RxDs or 8 Rx blocks
+ */
mac_control = &sp->mac_control;
config = &sp->config;
@@ -2102,23 +2725,23 @@
dev->name);
s2io_reset(sp);
free_irq(dev->irq, dev);
- freeRxBuffers(sp);
+ free_rx_buffers(sp);
return -ENOMEM;
}
DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
atomic_read(&sp->rx_bufs_left[i]));
}
-/* Enable tasklet for the device */
+ /* Enable tasklet for the device */
tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
-/* Enable Rx Traffic and interrupts on the NIC */
- if (startNic(sp)) {
+ /* Enable Rx Traffic and interrupts on the NIC */
+ if (start_nic(sp)) {
DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
tasklet_kill(&sp->task);
s2io_reset(sp);
free_irq(dev->irq, dev);
- freeRxBuffers(sp);
+ free_rx_buffers(sp);
return -ENODEV;
}
@@ -2128,41 +2751,55 @@
return 0;
}
-/*
- * Input Argument/s:
- * dev - device pointer.
- * Return value:
- * '0' on success and an appropriate (-)ve integer as defined in errno.h
- * file on failure.
+/**
+ * s2io_close -close entry point of the driver
+ * @dev : device pointer.
* Description:
* This is the stop entry point of the driver. It needs to undo exactly
- * whatever was done by the open entry point, thus it's usually referred to
- * as the close function. Among other things this function mainly stops the
+ * whatever was done by the open entry point,thus it's usually referred to
+ * as the close function.Among other things this function mainly stops the
* Rx side of the NIC and frees all the Rx buffers in the Rx rings.
+ * Return value:
+ * 0 on success and an appropriate (-)ve integer as defined in errno.h
+ * file on failure.
*/
+
int s2io_close(struct net_device *dev)
{
nic_t *sp = dev->priv;
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
register u64 val64 = 0;
u16 cnt = 0;
+ unsigned long flags;
- spin_lock(&sp->isr_lock);
+ spin_lock_irqsave(&sp->tx_lock, flags);
netif_stop_queue(dev);
-/* disable Tx and Rx traffic on the NIC */
- stopNic(sp);
+ /* disable Tx and Rx traffic on the NIC */
+ stop_nic(sp);
- spin_unlock(&sp->isr_lock);
-
-/* If the device tasklet is running, wait till its done before killing it */
+ /*
+ * If the device tasklet is running, wait till its done
+ * before killing it
+ */
while (atomic_read(&(sp->tasklet_status))) {
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(HZ / 10);
}
tasklet_kill(&sp->task);
-/* Check if the device is Quiescent and then Reset the NIC */
+ /* Free the Registered IRQ */
+ free_irq(dev->irq, dev);
+
+ /* Flush all scheduled tasks */
+ if (sp->task_flag == 1) {
+ DBG_PRINT(INFO_DBG, "%s: Calling close from a task\n",
+ dev->name);
+ } else {
+ flush_scheduled_work();
+ }
+
+ /* Check if the device is Quiescent and then Reset the NIC */
do {
val64 = readq(&bar0->adapter_status);
if (verify_xena_quiescence(val64, sp->device_enabled_once)) {
@@ -2182,36 +2819,35 @@
} while (1);
s2io_reset(sp);
-/* Free the Registered IRQ */
- free_irq(dev->irq, dev);
-
-/* Free all Tx Buffers waiting for transmission */
- freeTxBuffers(sp);
+ /* Free all Tx Buffers waiting for transmission */
+ free_tx_buffers(sp);
-/* Free all Rx buffers allocated by host */
- freeRxBuffers(sp);
+ /* Free all Rx buffers allocated by host */
+ free_rx_buffers(sp);
sp->device_close_flag = TRUE; /* Device is shut down. */
+ spin_unlock_irqrestore(&sp->tx_lock, flags);
return 0;
}
-/*
- * Input Argument/s:
- * skb - the socket buffer containing the Tx data.
- * dev - device pointer.
- * Return value:
- * '0' on success & 1 on failure.
- * NOTE: when device cant queue the pkt, just the trans_start variable will
- * not be upadted.
- * Description:
+/**
+ * s2io_xmit - Tx entry point of te driver
+ * @skb : the socket buffer containing the Tx data.
+ * @dev : device pointer.
+ * Description :
* This function is the Tx entry point of the driver. S2IO NIC supports
* certain protocol assist features on Tx side, namely CSO, S/G, LSO.
+ * NOTE: when device cant queue the pkt,just the trans_start variable will
+ * not be upadted.
+ * Return value:
+ * 0 on success & 1 on failure.
*/
+
int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
{
nic_t *sp = dev->priv;
- u16 off, txd_len, frg_cnt, frg_len, i, queue, off1, queue_len;
+ u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
register u64 val64;
TxD_t *txdp;
TxFIFO_element_t *tx_fifo;
@@ -2221,6 +2857,7 @@
#endif
mac_info_t *mac_control;
struct config_param *config;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
mac_control = &sp->mac_control;
config = &sp->config;
@@ -2228,6 +2865,14 @@
DBG_PRINT(TX_DBG, "%s: In S2IO Tx routine\n", dev->name);
spin_lock_irqsave(&sp->tx_lock, flags);
+ if ((netif_queue_stopped(dev)) || (!netif_carrier_ok(dev))) {
+ DBG_PRINT(ERR_DBG, "%s:s2io_xmit: Tx Queue stopped\n",
+ dev->name);
+ dev_kfree_skb(skb);
+ spin_unlock_irqrestore(&sp->tx_lock, flags);
+ return 0;
+ }
+
queue = 0;
/* Multi FIFO Tx is disabled for now. */
if (!queue && tx_prio) {
@@ -2236,21 +2881,19 @@
}
- off = (u16) mac_control->tx_curr_put_info[queue].offset;
- off1 = (u16) mac_control->tx_curr_get_info[queue].offset;
- txd_len = mac_control->txdl_len;
- txdp = mac_control->txdl_start[queue] + (config->MaxTxDs * off);
+ put_off = (u16) mac_control->tx_curr_put_info[queue].offset;
+ get_off = (u16) mac_control->tx_curr_get_info[queue].offset;
+ txdp = (TxD_t *) sp->list_info[queue][put_off].list_virt_addr;
queue_len = mac_control->tx_curr_put_info[queue].fifo_len + 1;
/* Avoid "put" pointer going beyond "get" pointer */
- if (txdp->Host_Control || (((off + 1) % queue_len) == off1)) {
+ if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) {
DBG_PRINT(ERR_DBG, "Error in xmit, No free TXDs.\n");
netif_stop_queue(dev);
dev_kfree_skb(skb);
spin_unlock_irqrestore(&sp->tx_lock, flags);
return 0;
}
-
#ifdef NETIF_F_TSO
mss = skb_shinfo(skb)->tso_size;
if (mss) {
@@ -2289,8 +2932,7 @@
txdp->Control_1 |= TXD_GATHER_CODE_LAST;
tx_fifo = mac_control->tx_FIFO_start[queue];
- val64 = (mac_control->txdl_start_phy[queue] +
- (sizeof(TxD_t) * txd_len * off));
+ val64 = sp->list_info[queue][put_off].list_phy_addr;
writeq(val64, &tx_fifo->TxDL_Pointer);
val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
@@ -2301,15 +2943,18 @@
#endif
writeq(val64, &tx_fifo->List_Control);
- off++;
- off %= mac_control->tx_curr_put_info[queue].fifo_len + 1;
- mac_control->tx_curr_put_info[queue].offset = off;
+ /* Perform a PCI read to flush previous writes */
+ val64 = readq(&bar0->general_int_status);
+
+ put_off++;
+ put_off %= mac_control->tx_curr_put_info[queue].fifo_len + 1;
+ mac_control->tx_curr_put_info[queue].offset = put_off;
/* Avoid "put" pointer going beyond "get" pointer */
- if (((off + 1) % queue_len) == off1) {
- DBG_PRINT(TX_DBG,
- "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
- off, off1);
+ if (((put_off + 1) % queue_len) == get_off) {
+ DBG_PRINT(TX_DBG,
+ "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
+ put_off, get_off);
netif_stop_queue(dev);
}
@@ -2319,36 +2964,37 @@
return 0;
}
-/*
- * Input Argument/s:
- * irq: the irq of the device.
- * dev_id: a void pointer to the dev structure of the NIC.
- * ptregs: pointer to the registers pushed on the stack.
+/**
+ * s2io_isr - ISR handler of the device .
+ * @irq: the irq of the device.
+ * @dev_id: a void pointer to the dev structure of the NIC.
+ * @pt_regs: pointer to the registers pushed on the stack.
+ * Description: This function is the ISR handler of the device. It
+ * identifies the reason for the interrupt and calls the relevant
+ * service routines. As a contongency measure, this ISR allocates the
+ * recv buffers, if their numbers are below the panic value which is
+ * presently set to 25% of the original number of rcv buffers allocated.
* Return value:
- * void.
- * Description:
- * This function is the ISR handler of the device. It identifies the reason
- * for the interrupt and calls the relevant service routines.
- * As a contongency measure, this ISR allocates the recv buffers, if their
- * numbers are below the panic value which is presently set to 25% of the
- * original number of rcv buffers allocated.
+ * IRQ_HANDLED: will be returned if IRQ was handled by this routine
+ * IRQ_NONE: will be returned if interrupt is not from our device
*/
-
static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
{
struct net_device *dev = (struct net_device *) dev_id;
nic_t *sp = dev->priv;
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
- u64 reason = 0, general_mask = 0;
+#ifndef CONFIG_S2IO_NAPI
+ int i, ret;
+#endif
+ u64 reason = 0;
mac_info_t *mac_control;
struct config_param *config;
mac_control = &sp->mac_control;
config = &sp->config;
- spin_lock(&sp->isr_lock);
-
- /* Identify the cause for interrupt and call the appropriate
+ /*
+ * Identify the cause for interrupt and call the appropriate
* interrupt handler. Causes for the interrupt could be;
* 1. Rx of packet.
* 2. Tx complete.
@@ -2359,69 +3005,53 @@
if (!reason) {
/* The interrupt was not raised by Xena. */
- spin_unlock(&sp->isr_lock);
return IRQ_NONE;
}
- /* Mask the interrupts on the NIC */
- general_mask = readq(&bar0->general_int_mask);
- writeq(0xFFFFFFFFFFFFFFFFULL, &bar0->general_int_mask);
-
-#if DEBUG_ON
- sp->int_cnt++;
-#endif
/* If Intr is because of Tx Traffic */
if (reason & GEN_INTR_TXTRAFFIC) {
- txIntrHandler(sp);
+ tx_intr_handler(sp);
}
/* If Intr is because of an error */
if (reason & (GEN_ERROR_INTR))
- alarmIntrHandler(sp);
+ alarm_intr_handler(sp);
#ifdef CONFIG_S2IO_NAPI
if (reason & GEN_INTR_RXTRAFFIC) {
if (netif_rx_schedule_prep(dev)) {
- en_dis_able_NicIntrs(sp, RX_TRAFFIC_INTR,
- DISABLE_INTRS);
- /* We retake the snap shot of the general interrupt
- * register.
- */
- general_mask = readq(&bar0->general_int_mask);
+ en_dis_able_nic_intrs(sp, RX_TRAFFIC_INTR,
+ DISABLE_INTRS);
__netif_rx_schedule(dev);
}
}
#else
/* If Intr is because of Rx Traffic */
if (reason & GEN_INTR_RXTRAFFIC) {
- rxIntrHandler(sp);
+ rx_intr_handler(sp);
}
#endif
-/* If the Rx buffer count is below the panic threshold then reallocate the
- * buffers from the interrupt handler itself, else schedule a tasklet to
- * reallocate the buffers.
- */
-#if 1
- {
- int i;
-
+ /*
+ * If the Rx buffer count is below the panic threshold then
+ * reallocate the buffers from the interrupt handler itself,
+ * else schedule a tasklet to reallocate the buffers.
+ */
+#ifndef CONFIG_S2IO_NAPI
for (i = 0; i < config->RxRingNum; i++) {
int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
int level = rx_buffer_level(sp, rxb_size, i);
if ((level == PANIC) && (!TASKLET_IN_USE)) {
- int ret;
-
- DBG_PRINT(ERR_DBG, "%s: Rx BD hit ", dev->name);
- DBG_PRINT(ERR_DBG, "PANIC levels\n");
+ DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", dev->name);
+ DBG_PRINT(INTR_DBG, "PANIC levels\n");
if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
DBG_PRINT(ERR_DBG, "%s:Out of memory",
dev->name);
DBG_PRINT(ERR_DBG, " in ISR!!\n");
- writeq(general_mask,
- &bar0->general_int_mask);
- spin_unlock(&sp->isr_lock);
+ clear_bit(0,
+ (unsigned long *) (&sp->
+ tasklet_status));
return IRQ_HANDLED;
}
clear_bit(0,
@@ -2432,28 +3062,21 @@
}
}
-
- }
-#else
- tasklet_schedule(&sp->task);
#endif
- /* Unmask all the previously enabled interrupts on the NIC */
- writeq(general_mask, &bar0->general_int_mask);
-
- spin_unlock(&sp->isr_lock);
return IRQ_HANDLED;
}
-/*
- * Input Argument/s:
- * dev - pointer to the device structure.
- * Return value:
- * pointer to the updated net_device_stats structure.
+/**
+ * s2io_get_stats - Updates the device statistics structure.
+ * @dev : pointer to the device structure.
* Description:
* This function updates the device statistics structure in the s2io_nic
* structure and returns a pointer to the same.
+ * Return value:
+ * pointer to the updated net_device_stats structure.
*/
+
struct net_device_stats *s2io_get_stats(struct net_device *dev)
{
nic_t *sp = dev->priv;
@@ -2463,27 +3086,28 @@
mac_control = &sp->mac_control;
config = &sp->config;
- sp->stats.tx_errors = mac_control->StatsInfo->tmac_any_err_frms;
- sp->stats.rx_errors = mac_control->StatsInfo->rmac_drop_frms;
- sp->stats.multicast = mac_control->StatsInfo->rmac_vld_mcst_frms;
+ sp->stats.tx_errors = mac_control->stats_info->tmac_any_err_frms;
+ sp->stats.rx_errors = mac_control->stats_info->rmac_drop_frms;
+ sp->stats.multicast = mac_control->stats_info->rmac_vld_mcst_frms;
sp->stats.rx_length_errors =
- mac_control->StatsInfo->rmac_long_frms;
+ mac_control->stats_info->rmac_long_frms;
return (&sp->stats);
}
-/*
- * Input Argument/s:
- * dev - pointer to the device structure
- * Return value:
- * void.
+/**
+ * s2io_set_multicast - entry point for multicast address enable/disable.
+ * @dev : pointer to the device structure
* Description:
* This function is a driver entry point which gets called by the kernel
* whenever multicast addresses must be enabled/disabled. This also gets
* called to set/reset promiscuous mode. Depending on the deivce flag, we
* determine, if multicast address must be enabled or if promiscuous mode
* is to be disabled etc.
+ * Return value:
+ * void.
*/
+
static void s2io_set_multicast(struct net_device *dev)
{
int i, j, prev_cnt;
@@ -2506,7 +3130,7 @@
RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
writeq(val64, &bar0->rmac_addr_cmd_mem);
/* Wait till command completes */
- waitForCmdComplete(sp);
+ wait_for_cmd_complete(sp);
sp->m_cast_flg = 1;
sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
@@ -2519,7 +3143,7 @@
RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
writeq(val64, &bar0->rmac_addr_cmd_mem);
/* Wait till command completes */
- waitForCmdComplete(sp);
+ wait_for_cmd_complete(sp);
sp->m_cast_flg = 0;
sp->all_multi_pos = 0;
@@ -2582,7 +3206,7 @@
writeq(val64, &bar0->rmac_addr_cmd_mem);
/* Wait for command completes */
- if (waitForCmdComplete(sp)) {
+ if (wait_for_cmd_complete(sp)) {
DBG_PRINT(ERR_DBG, "%s: Adding ",
dev->name);
DBG_PRINT(ERR_DBG, "Multicasts failed\n");
@@ -2609,7 +3233,7 @@
writeq(val64, &bar0->rmac_addr_cmd_mem);
/* Wait for command completes */
- if (waitForCmdComplete(sp)) {
+ if (wait_for_cmd_complete(sp)) {
DBG_PRINT(ERR_DBG, "%s: Adding ",
dev->name);
DBG_PRINT(ERR_DBG, "Multicasts failed\n");
@@ -2619,17 +3243,16 @@
}
}
-/*
- * Input Argument/s:
- * dev - pointer to the device structure.
- * new_mac - a uchar pointer to the new mac address which is to be set.
- * Return value:
- * SUCCESS on success and an appropriate (-)ve integer as defined in errno.h
- * file on failure.
- * Description:
- * This procedure will program the Xframe to receive frames with new
- * Mac Address
+/**
+ * s2io_set_mac_addr - Programs the Xframe mac address
+ * @dev : pointer to the device structure.
+ * @addr: a uchar pointer to the new mac address which is to be set.
+ * Description : This procedure will program the Xframe to receive
+ * frames with new Mac Address
+ * Return value: SUCCESS on success and an appropriate (-)ve integer
+ * as defined in errno.h file on failure.
*/
+
int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
{
nic_t *sp = dev->priv;
@@ -2655,7 +3278,7 @@
RMAC_ADDR_CMD_MEM_OFFSET(0);
writeq(val64, &bar0->rmac_addr_cmd_mem);
/* Wait till command completes */
- if (waitForCmdComplete(sp)) {
+ if (wait_for_cmd_complete(sp)) {
DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
return FAILURE;
}
@@ -2663,18 +3286,18 @@
return SUCCESS;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * info - pointer to the structure with parameters given by ethtool to set
- * link information.
- * Return value:
- * 0 on success.
+/**
+ * s2io_ethtool_sset - Sets different link parameters.
+ * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
+ * @info: pointer to the structure with parameters given by ethtool to set
+ * link information.
* Description:
- * The function sets different link parameters provided by the user onto
- * the NIC.
- */
+ * The function sets different link parameters provided by the user onto
+ * the NIC.
+ * Return value:
+ * 0 on success.
+*/
+
static int s2io_ethtool_sset(struct net_device *dev,
struct ethtool_cmd *info)
{
@@ -2690,17 +3313,18 @@
return 0;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * info - pointer to the structure with parameters given by ethtool to return
- * link information.
- * Return value:
- * void
+/**
+ * s2io_ethtol_gset - Return link specific information.
+ * @sp : private member of the device structure, pointer to the
+ * s2io_nic structure.
+ * @info : pointer to the structure with parameters given by ethtool
+ * to return link information.
* Description:
- * Returns link specefic information like speed, duplex etc.. to ethtool.
+ * Returns link specefic information like speed, duplex etc.. to ethtool.
+ * Return value :
+ * return 0 on success.
*/
+
int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
{
nic_t *sp = dev->priv;
@@ -2721,17 +3345,18 @@
return 0;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * info - pointer to the structure with parameters given by ethtool to return
- * driver information.
+/**
+ * s2io_ethtool_gdrvinfo - Returns driver specific information.
+ * @sp : private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * @info : pointer to the structure with parameters given by ethtool to
+ * return driver information.
+ * Description:
+ * Returns driver specefic information like name, version etc.. to ethtool.
* Return value:
* void
- * Description:
- * Returns driver specefic information like name, version etc.. to ethtool.
*/
+
static void s2io_ethtool_gdrvinfo(struct net_device *dev,
struct ethtool_drvinfo *info)
{
@@ -2748,19 +3373,20 @@
info->n_stats = S2IO_STAT_LEN;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * regs - pointer to the structure with parameters given by ethtool for
+/**
+ * s2io_ethtool_gregs - dumps the entire space of Xfame into te buffer.
+ * @sp: private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * @regs : pointer to the structure with parameters given by ethtool for
* dumping the registers.
- * reg_space - The input argumnet into which all the registers are dumped.
- * Return value:
- * void
- * Description:
- * Dumps the entire register space of xFrame NIC into the user given buffer
- * area.
- */
+ * @reg_space: The input argumnet into which all the registers are dumped.
+ * Description:
+ * Dumps the entire register space of xFrame NIC into the user given
+ * buffer area.
+ * Return value :
+ * void .
+*/
+
static void s2io_ethtool_gregs(struct net_device *dev,
struct ethtool_regs *regs, void *space)
{
@@ -2778,17 +3404,15 @@
}
}
-/*
- * Input Argument/s:
- * data - address of the private member of the device structure, which
+/**
+ * s2io_phy_id - timer function that alternates adapter LED.
+ * @data : address of the private member of the device structure, which
* is a pointer to the s2io_nic structure, provided as an u32.
- * Return value:
- * void
- * Description:
- * This is actually the timer function that alternates the adapter LED bit
- * of the adapter control bit to set/reset every time on invocation.
- * The timer is set for 1/2 a second, hence tha NIC blinks once every second.
- */
+ * Description: This is actually the timer function that alternates the
+ * adapter LED bit of the adapter control bit to set/reset every time on
+ * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
+ * once every second.
+*/
static void s2io_phy_id(unsigned long data)
{
nic_t *sp = (nic_t *) data;
@@ -2810,28 +3434,30 @@
mod_timer(&sp->id_timer, jiffies + HZ / 2);
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * id - pointer to the structure with identification parameters given by
- * ethtool.
+/**
+ * s2io_ethtool_idnic - To physically ientify the nic on the system.
+ * @sp : private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * @id : pointer to the structure with identification parameters given by
+ * ethtool.
+ * Description: Used to physically identify the NIC on the system.
+ * The Link LED will blink for a time specified by the user for
+ * identification.
+ * NOTE: The Link has to be Up to be able to blink the LED. Hence
+ * identification is possible only if it's link is up.
* Return value:
- * int , returns '0' on success
- * Description:
- * Used to physically identify the NIC on the system. The Link LED will blink
- * for a time specified by the user for identification.
- * NOTE: The Link has to be Up to be able to blink the LED. Hence
- * identification is possible only if it's link is up.
+ * int , returns 0 on success
*/
+
static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
{
- u64 val64 = 0;
+ u64 val64 = 0, last_gpio_ctrl_val;
nic_t *sp = dev->priv;
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
u16 subid;
subid = sp->pdev->subsystem_device;
+ last_gpio_ctrl_val = readq(&bar0->gpio_control);
if ((subid & 0xFF) < 0x07) {
val64 = readq(&bar0->adapter_control);
if (!(val64 & ADAPTER_CNTL_EN)) {
@@ -2853,18 +3479,22 @@
schedule_timeout(MAX_SCHEDULE_TIMEOUT);
del_timer_sync(&sp->id_timer);
+ if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) {
+ writeq(last_gpio_ctrl_val, &bar0->gpio_control);
+ last_gpio_ctrl_val = readq(&bar0->gpio_control);
+ }
+
return 0;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * ep - pointer to the structure with pause parameters given by ethtool.
+/**
+ * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
+ * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
+ * @ep : pointer to the structure with pause parameters given by ethtool.
+ * Description:
+ * Returns the Pause frame generation and reception capability of the NIC.
* Return value:
* void
- * Description:
- * Returns the Pause frame generation and reception capability of the NIC.
*/
static void s2io_ethtool_getpause_data(struct net_device *dev,
struct ethtool_pauseparam *ep)
@@ -2881,17 +3511,18 @@
ep->autoneg = FALSE;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * ep - pointer to the structure with pause parameters given by ethtool.
- * Return value:
- * int, returns '0' on Success
+/**
+ * s2io_ethtool-setpause_data - set/reset pause frame generation.
+ * @sp : private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * @ep : pointer to the structure with pause parameters given by ethtool.
* Description:
- * It can be used to set or reset Pause frame generation or reception support
- * of the NIC.
+ * It can be used to set or reset Pause frame generation or reception
+ * support of the NIC.
+ * Return value:
+ * int, returns 0 on Success
*/
+
int s2io_ethtool_setpause_data(struct net_device *dev,
struct ethtool_pauseparam *ep)
{
@@ -2912,35 +3543,40 @@
return 0;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * off - offset at which the data must be written
- * Return value:
- * -1 on failure and the value read from the Eeprom if successful.
+/**
+ * read_eeprom - reads 4 bytes of data from user given offset.
+ * @sp : private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * @off : offset at which the data must be written
+ * @data : Its an output parameter where the data read at the given
+ * offset is stored.
* Description:
- * Will read 4 bytes of data from the user given offset and return the
- * read data.
+ * Will read 4 bytes of data from the user given offset and return the
+ * read data.
* NOTE: Will allow to read only part of the EEPROM visible through the
- * I2C bus.
+ * I2C bus.
+ * Return value:
+ * -1 on failure and 0 on success.
*/
+
#define S2IO_DEV_ID 5
-static u32 readEeprom(nic_t * sp, int off)
+static int read_eeprom(nic_t * sp, int off, u32 * data)
{
- u32 data = -1, exit_cnt = 0;
+ int ret = -1;
+ u32 exit_cnt = 0;
u64 val64;
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
I2C_CONTROL_CNTL_START;
- writeq(val64, &bar0->i2c_control);
+ SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
while (exit_cnt < 5) {
val64 = readq(&bar0->i2c_control);
if (I2C_CONTROL_CNTL_END(val64)) {
- data = I2C_CONTROL_GET_DATA(val64);
+ *data = I2C_CONTROL_GET_DATA(val64);
+ ret = 0;
break;
}
set_current_state(TASK_UNINTERRUPTIBLE);
@@ -2948,24 +3584,25 @@
exit_cnt++;
}
- return data;
+ return ret;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * off - offset at which the data must be written
- * data - The data that is to be written
- * cnt - Number of bytes of the data that are actually to be written into
+/**
+ * write_eeprom - actually writes the relevant part of the data value.
+ * @sp : private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * @off : offset at which the data must be written
+ * @data : The data that is to be written
+ * @cnt : Number of bytes of the data that are actually to be written into
* the Eeprom. (max of 3)
- * Return value:
- * '0' on success, -1 on failure.
* Description:
* Actually writes the relevant part of the data value into the Eeprom
* through the I2C bus.
+ * Return value:
+ * 0 on success, -1 on failure.
*/
-static int writeEeprom(nic_t * sp, int off, u32 data, int cnt)
+
+static int write_eeprom(nic_t * sp, int off, u32 data, int cnt)
{
int exit_cnt = 0, ret = -1;
u64 val64;
@@ -2974,7 +3611,7 @@
val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA(data) |
I2C_CONTROL_CNTL_START;
- writeq(val64, &bar0->i2c_control);
+ SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
while (exit_cnt < 5) {
val64 = readq(&bar0->i2c_control);
@@ -2991,39 +3628,19 @@
return ret;
}
-/*
- * A helper function used to invert the 4 byte u32 data field
- * byte by byte. This will be used by the Read Eeprom function
- * for display purposes.
- */
-u32 inv(u32 data)
-{
- static u32 ret = 0;
-
- if (data) {
- u8 c = data;
- ret = ((ret << 8) + c);
- data >>= 8;
- inv(data);
- }
-
- return ret;
-}
-
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * eeprom - pointer to the user level structure provided by ethtool,
- * containing all relevant information.
- * data_buf - user defined value to be written into Eeprom.
- * Return value:
- * int '0' on success
- * Description:
- * Reads the values stored in the Eeprom at given offset for a given length.
- * Stores these values int the input argument data buffer 'data_buf' and
- * returns these to the caller (ethtool.)
+/**
+ * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
+ * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
+ * @eeprom : pointer to the user level structure provided by ethtool,
+ * containing all relevant information.
+ * @data_buf : user defined value to be written into Eeprom.
+ * Description: Reads the values stored in the Eeprom at given offset
+ * for a given length. Stores these values int the input argument data
+ * buffer 'data_buf' and returns these to the caller (ethtool.)
+ * Return value:
+ * int 0 on success
*/
+
int s2io_ethtool_geeprom(struct net_device *dev,
struct ethtool_eeprom *eeprom, u8 * data_buf)
{
@@ -3036,30 +3653,30 @@
eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
for (i = 0; i < eeprom->len; i += 4) {
- data = readEeprom(sp, eeprom->offset + i);
- if (data < 0) {
+ if (read_eeprom(sp, (eeprom->offset + i), &data)) {
DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
return -EFAULT;
}
- valid = inv(data);
+ valid = INV(data);
memcpy((data_buf + i), &valid, 4);
}
return 0;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * eeprom - pointer to the user level structure provided by ethtool,
- * containing all relevant information.
- * data_buf - user defined value to be written into Eeprom.
- * Return value:
- * '0' on success, -EFAULT on failure.
- * Description:
+/**
+ * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
+ * @sp : private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * @eeprom : pointer to the user level structure provided by ethtool,
+ * containing all relevant information.
+ * @data_buf ; user defined value to be written into Eeprom.
+ * Description:
* Tries to write the user provided value in the Eeprom, at the offset
* given by the user.
+ * Return value:
+ * 0 on success, -EFAULT on failure.
*/
+
static int s2io_ethtool_seeprom(struct net_device *dev,
struct ethtool_eeprom *eeprom,
u8 * data_buf)
@@ -3083,7 +3700,7 @@
} else
valid = data;
- if (writeEeprom(sp, (eeprom->offset + cnt), valid, 0)) {
+ if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
DBG_PRINT(ERR_DBG,
"ETHTOOL_WRITE_EEPROM Err: Cannot ");
DBG_PRINT(ERR_DBG,
@@ -3097,19 +3714,20 @@
return 0;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * data - variable that returns the result of each of the test conducted by
- * the driver.
- * Return value:
- * '0' on success.
+/**
+ * s2io_register_test - reads and writes into all clock domains.
+ * @sp : private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * @data : variable that returns the result of each of the test conducted b
+ * by the driver.
* Description:
- * Read and write into all clock domains. The NIC has 3 clock domains,
- * see that registers in all the three regions are accessible.
+ * Read and write into all clock domains. The NIC has 3 clock domains,
+ * see that registers in all the three regions are accessible.
+ * Return value:
+ * 0 on success.
*/
-static int s2io_registerTest(nic_t * sp, uint64_t * data)
+
+static int s2io_register_test(nic_t * sp, uint64_t * data)
{
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
u64 val64 = 0;
@@ -3159,88 +3777,91 @@
return 0;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * data - variable that returns the result of each of the test conducted by
- * the driver.
- * Return value:
- * '0' on success.
+/**
+ * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
+ * @sp : private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * @data:variable that returns the result of each of the test conducted by
+ * the driver.
* Description:
- * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
- * register.
+ * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
+ * register.
+ * Return value:
+ * 0 on success.
*/
-static int s2io_eepromTest(nic_t * sp, uint64_t * data)
+
+static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
{
- int fail = 0, ret_data;
+ int fail = 0;
+ u32 ret_data;
/* Test Write Error at offset 0 */
- if (!writeEeprom(sp, 0, 0, 3))
+ if (!write_eeprom(sp, 0, 0, 3))
fail = 1;
/* Test Write at offset 4f0 */
- if (writeEeprom(sp, 0x4F0, 0x01234567, 3))
+ if (write_eeprom(sp, 0x4F0, 0x01234567, 3))
fail = 1;
- if ((ret_data = readEeprom(sp, 0x4f0)) < 0)
+ if (read_eeprom(sp, 0x4F0, &ret_data))
fail = 1;
if (ret_data != 0x01234567)
fail = 1;
/* Reset the EEPROM data go FFFF */
- writeEeprom(sp, 0x4F0, 0xFFFFFFFF, 3);
+ write_eeprom(sp, 0x4F0, 0xFFFFFFFF, 3);
/* Test Write Request Error at offset 0x7c */
- if (!writeEeprom(sp, 0x07C, 0, 3))
+ if (!write_eeprom(sp, 0x07C, 0, 3))
fail = 1;
/* Test Write Request at offset 0x7fc */
- if (writeEeprom(sp, 0x7FC, 0x01234567, 3))
+ if (write_eeprom(sp, 0x7FC, 0x01234567, 3))
fail = 1;
- if ((ret_data = readEeprom(sp, 0x7FC)) < 0)
+ if (read_eeprom(sp, 0x7FC, &ret_data))
fail = 1;
if (ret_data != 0x01234567)
fail = 1;
/* Reset the EEPROM data go FFFF */
- writeEeprom(sp, 0x7FC, 0xFFFFFFFF, 3);
+ write_eeprom(sp, 0x7FC, 0xFFFFFFFF, 3);
/* Test Write Error at offset 0x80 */
- if (!writeEeprom(sp, 0x080, 0, 3))
+ if (!write_eeprom(sp, 0x080, 0, 3))
fail = 1;
/* Test Write Error at offset 0xfc */
- if (!writeEeprom(sp, 0x0FC, 0, 3))
+ if (!write_eeprom(sp, 0x0FC, 0, 3))
fail = 1;
/* Test Write Error at offset 0x100 */
- if (!writeEeprom(sp, 0x100, 0, 3))
+ if (!write_eeprom(sp, 0x100, 0, 3))
fail = 1;
/* Test Write Error at offset 4ec */
- if (!writeEeprom(sp, 0x4EC, 0, 3))
+ if (!write_eeprom(sp, 0x4EC, 0, 3))
fail = 1;
*data = fail;
return 0;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * data - variable that returns the result of each of the test conducted by
- * the driver.
- * Return value:
- * '0' on success and -1 on failure.
+/**
+ * s2io_bist_test - invokes the MemBist test of the card .
+ * @sp : private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * @data:variable that returns the result of each of the test conducted by
+ * the driver.
* Description:
- * This invokes the MemBist test of the card. We give around
- * 2 secs time for the Test to complete. If it's still not complete
- * within this peiod, we consider that the test failed.
+ * This invokes the MemBist test of the card. We give around
+ * 2 secs time for the Test to complete. If it's still not complete
+ * within this peiod, we consider that the test failed.
+ * Return value:
+ * 0 on success and -1 on failure.
*/
-static int s2io_bistTest(nic_t * sp, uint64_t * data)
+
+static int s2io_bist_test(nic_t * sp, uint64_t * data)
{
u8 bist = 0;
int cnt = 0, ret = -1;
@@ -3264,19 +3885,20 @@
return ret;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * data - variable that returns the result of each of the test conducted by
- * the driver.
- * Return value:
- * '0' on success.
+/**
+ * s2io-link_test - verifies the link state of the nic
+ * @sp ; private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * @data: variable that returns the result of each of the test conducted by
+ * the driver.
* Description:
- * The function verifies the link state of the NIC and updates the input
- * argument 'data' appropriately.
+ * The function verifies the link state of the NIC and updates the input
+ * argument 'data' appropriately.
+ * Return value:
+ * 0 on success.
*/
-static int s2io_linkTest(nic_t * sp, uint64_t * data)
+
+static int s2io_link_test(nic_t * sp, uint64_t * data)
{
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
u64 val64;
@@ -3288,19 +3910,20 @@
return 0;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * data - variable that returns the result of each of the test conducted by
- * the driver.
- * Return value:
- * '0' on success.
+/**
+ * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
+ * @sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * @data - variable that returns the result of each of the test
+ * conducted by the driver.
* Description:
* This is one of the offline test that tests the read and write
* access to the RldRam chip on the NIC.
+ * Return value:
+ * 0 on success.
*/
-static int s2io_rldramTest(nic_t * sp, uint64_t * data)
+
+static int s2io_rldram_test(nic_t * sp, uint64_t * data)
{
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
u64 val64;
@@ -3316,10 +3939,10 @@
val64 = readq(&bar0->mc_rldram_mrs);
val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
- writeq(val64, &bar0->mc_rldram_mrs);
+ SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
val64 |= MC_RLDRAM_MRS_ENABLE;
- writeq(val64, &bar0->mc_rldram_mrs);
+ SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
while (iteration < 2) {
val64 = 0x55555555aaaa0000ULL;
@@ -3395,20 +4018,21 @@
return 0;
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * ethtest - pointer to a ethtool command specific structure that will be
- * returned to the user.
- * data - variable that returns the result of each of the test conducted by
- * the driver.
- * Return value:
- * SUCCESS on success and an appropriate -1 on failure.
+/**
+ * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
+ * @sp : private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * @ethtest : pointer to a ethtool command specific structure that will be
+ * returned to the user.
+ * @data : variable that returns the result of each of the test
+ * conducted by the driver.
* Description:
* This function conducts 6 tests ( 4 offline and 2 online) to determine
- * the health of the card.
+ * the health of the card.
+ * Return value:
+ * void
*/
+
static void s2io_ethtool_test(struct net_device *dev,
struct ethtool_test *ethtest,
uint64_t * data)
@@ -3424,22 +4048,22 @@
} else
s2io_set_swapper(sp);
- if (s2io_registerTest(sp, &data[0]))
+ if (s2io_register_test(sp, &data[0]))
ethtest->flags |= ETH_TEST_FL_FAILED;
s2io_reset(sp);
s2io_set_swapper(sp);
- if (s2io_rldramTest(sp, &data[3]))
+ if (s2io_rldram_test(sp, &data[3]))
ethtest->flags |= ETH_TEST_FL_FAILED;
s2io_reset(sp);
s2io_set_swapper(sp);
- if (s2io_eepromTest(sp, &data[1]))
+ if (s2io_eeprom_test(sp, &data[1]))
ethtest->flags |= ETH_TEST_FL_FAILED;
- if (s2io_bistTest(sp, &data[4]))
+ if (s2io_bist_test(sp, &data[4]))
ethtest->flags |= ETH_TEST_FL_FAILED;
if (orig_state)
@@ -3459,7 +4083,7 @@
data[4] = -1;
}
- if (s2io_linkTest(sp, &data[2]))
+ if (s2io_link_test(sp, &data[2]))
ethtest->flags |= ETH_TEST_FL_FAILED;
data[0] = 0;
@@ -3475,7 +4099,7 @@
{
int i = 0;
nic_t *sp = dev->priv;
- StatInfo_t *stat_info = sp->mac_control.StatsInfo;
+ StatInfo_t *stat_info = sp->mac_control.stats_info;
tmp_stats[i++] = stat_info->tmac_frms;
tmp_stats[i++] = stat_info->tmac_data_octets;
@@ -3567,6 +4191,17 @@
return (S2IO_STAT_LEN);
}
+int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
+{
+ if (data)
+ dev->features |= NETIF_F_IP_CSUM;
+ else
+ dev->features &= ~NETIF_F_IP_CSUM;
+
+ return 0;
+}
+
+
static struct ethtool_ops netdev_ethtool_ops = {
.get_settings = s2io_ethtool_gset,
.set_settings = s2io_ethtool_sset,
@@ -3582,7 +4217,7 @@
.get_rx_csum = s2io_ethtool_get_rx_csum,
.set_rx_csum = s2io_ethtool_set_rx_csum,
.get_tx_csum = ethtool_op_get_tx_csum,
- .set_tx_csum = ethtool_op_set_tx_csum,
+ .set_tx_csum = s2io_ethtool_op_set_tx_csum,
.get_sg = ethtool_op_get_sg,
.set_sg = ethtool_op_set_sg,
#ifdef NETIF_F_TSO
@@ -3597,36 +4232,37 @@
.get_ethtool_stats = s2io_get_ethtool_stats
};
-/*
- * Input Argument/s:
- * dev - Device pointer.
- * ifr - An IOCTL specefic structure, that can contain a pointer to
- * a proprietary structure used to pass information to the driver.
- * cmd - This is used to distinguish between the different commands that
- * can be passed to the IOCTL functions.
- * Return value:
- * '0' on success and an appropriate (-)ve integer as defined in errno.h
- * file on failure.
+/**
+ * s2io_ioctl - Entry point for the Ioctl
+ * @dev : Device pointer.
+ * @ifr : An IOCTL specefic structure, that can contain a pointer to
+ * a proprietary structure used to pass information to the driver.
+ * @cmd : This is used to distinguish between the different commands that
+ * can be passed to the IOCTL functions.
* Description:
* This function has support for ethtool, adding multiple MAC addresses on
* the NIC and some DBG commands for the util tool.
+ * Return value:
+ * Currently the IOCTL supports no operations, hence by default this
+ * function returns OP NOT SUPPORTED value.
*/
+
int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
return -EOPNOTSUPP;
}
-/*
- * Input Argument/s:
- * dev - device pointer.
- * new_mtu - the new MTU size for the device.
+/**
+ * s2io_change_mtu - entry point to change MTU size for the device.
+ * @dev : device pointer.
+ * @new_mtu : the new MTU size for the device.
+ * Description: A driver entry point to change MTU size for the device.
+ * Before changing the MTU the device must be stopped.
* Return value:
- * '0' on success and an appropriate (-)ve integer as defined in errno.h
+ * 0 on success and an appropriate (-)ve integer as defined in errno.h
* file on failure.
- * Description:
- * A driver entry point to change MTU size for the device. Before changing
- * the MTU the device must be stopped.
*/
+
int s2io_change_mtu(struct net_device *dev, int new_mtu)
{
nic_t *sp = dev->priv;
@@ -3645,7 +4281,7 @@
return -EPERM;
}
-/* Set the new MTU into the PYLD register of the NIC */
+ /* Set the new MTU into the PYLD register of the NIC */
val64 = new_mtu;
writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
@@ -3654,18 +4290,19 @@
return 0;
}
-/*
- * Input Argument/s:
- * dev_adr - address of the device structure in dma_addr_t format.
- * Return value:
- * void.
+/**
+ * s2io_tasklet - Bottom half of the ISR.
+ * @dev_adr : address of the device structure in dma_addr_t format.
* Description:
* This is the tasklet or the bottom half of the ISR. This is
* an extension of the ISR which is scheduled by the scheduler to be run
* when the load on the CPU is low. All low priority tasks of the ISR can
* be pushed into the tasklet. For now the tasklet is used only to
* replenish the Rx buffers in the Rx buffer descriptors.
+ * Return value:
+ * void.
*/
+
static void s2io_tasklet(unsigned long dev_addr)
{
struct net_device *dev = (struct net_device *) dev_addr;
@@ -3684,31 +4321,35 @@
DBG_PRINT(ERR_DBG, "%s: Out of ",
dev->name);
DBG_PRINT(ERR_DBG, "memory in tasklet\n");
- return;
+ break;
} else if (ret == -EFILL) {
DBG_PRINT(ERR_DBG,
"%s: Rx Ring %d is full\n",
dev->name, i);
- return;
+ break;
}
}
clear_bit(0, (unsigned long *) (&sp->tasklet_status));
}
}
-
-/*
- * Description:
- *
+/**
+ * s2io_set_link - Set the LInk status
+ * @data: long pointer to device private structue
+ * Description: Sets the link status for the adapter
*/
+
static void s2io_set_link(unsigned long data)
{
nic_t *nic = (nic_t *) data;
struct net_device *dev = nic->dev;
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
- register u64 val64, err_reg;
+ register u64 val64;
+ u16 subid;
- /* Allow a small delay for the NICs self initiated
+ subid = nic->pdev->subsystem_device;
+ /*
+ * Allow a small delay for the NICs self initiated
* cleanup to complete.
*/
set_current_state(TASK_UNINTERRUPTIBLE);
@@ -3716,16 +4357,19 @@
val64 = readq(&bar0->adapter_status);
if (verify_xena_quiescence(val64, nic->device_enabled_once)) {
- /* Acknowledge interrupt and clear the R1 register */
- err_reg = readq(&bar0->mac_rmac_err_reg);
- writeq(err_reg, &bar0->mac_rmac_err_reg);
-
if (LINK_IS_UP(val64)) {
val64 = readq(&bar0->adapter_control);
val64 |= ADAPTER_CNTL_EN;
writeq(val64, &bar0->adapter_control);
- val64 |= ADAPTER_LED_ON;
- writeq(val64, &bar0->adapter_control);
+ if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) {
+ val64 = readq(&bar0->gpio_control);
+ val64 |= GPIO_CTRL_GPIO_0;
+ writeq(val64, &bar0->gpio_control);
+ val64 = readq(&bar0->gpio_control);
+ } else {
+ val64 |= ADAPTER_LED_ON;
+ writeq(val64, &bar0->adapter_control);
+ }
val64 = readq(&bar0->adapter_status);
if (!LINK_IS_UP(val64)) {
DBG_PRINT(ERR_DBG, "%s:", dev->name);
@@ -3739,6 +4383,12 @@
}
s2io_link(nic, LINK_UP);
} else {
+ if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) {
+ val64 = readq(&bar0->gpio_control);
+ val64 &= ~GPIO_CTRL_GPIO_0;
+ writeq(val64, &bar0->gpio_control);
+ val64 = readq(&bar0->gpio_control);
+ }
s2io_link(nic, LINK_DOWN);
}
} else { /* NIC is not Quiescent. */
@@ -3748,37 +4398,43 @@
}
}
-/*
+/**
+ * s2io_restart_nic - Resets the NIC.
+ * @data : long pointer to the device private structure
* Description:
* This function is scheduled to be run by the s2io_tx_watchdog
* function after 0.5 secs to reset the NIC. The idea is to reduce
* the run time of the watch dog routine which is run holding a
* spin lock.
*/
+
static void s2io_restart_nic(unsigned long data)
{
struct net_device *dev = (struct net_device *) data;
nic_t *sp = dev->priv;
+ sp->task_flag = 1;
s2io_close(dev);
+ sp->task_flag = 0;
sp->device_close_flag = TRUE;
s2io_open(dev);
DBG_PRINT(ERR_DBG,
"%s: was reset by Tx watchdog timer.\n", dev->name);
}
-/*
- * Input Argument/s:
- * dev - device pointer.
- * Return value:
- * void
+/**
+ * s2io_tx_watchdog - Watchdog for transmit side.
+ * @dev : Pointer to net device structure
* Description:
* This function is triggered if the Tx Queue is stopped
* for a pre-defined amount of time when the Interface is still up.
* If the Interface is jammed in such a situation, the hardware is
* reset (by s2io_close) and restarted again (by s2io_open) to
* overcome any problem that might have been caused in the hardware.
+ * Return value:
+ * void
*/
+
static void s2io_tx_watchdog(struct net_device *dev)
{
nic_t *sp = dev->priv;
@@ -3788,36 +4444,45 @@
}
}
-/*
- * Input Argument/s:
- * sp - private member of the device structure, which is a pointer to the
- * s2io_nic structure.
- * skb - the socket buffer pointer.
- * len - length of the packet
- * cksum - FCS checksum of the frame.
- * ring_no - the ring from which this RxD was extracted.
- * Return value:
- * SUCCESS on success and -1 on failure.
- * Description:
- * This function is called by the Tx interrupt serivce routine to perform
+/**
+ * rx_osm_handler - To perform some OS related operations on SKB.
+ * @sp: private member of the device structure,pointer to s2io_nic structure.
+ * @skb : the socket buffer pointer.
+ * @len : length of the packet
+ * @cksum : FCS checksum of the frame.
+ * @ring_no : the ring from which this RxD was extracted.
+ * Description:
+ * This function is called by the Tx interrupt serivce routine to perform
* some OS related operations on the SKB before passing it to the upper
* layers. It mainly checks if the checksum is OK, if so adds it to the
* SKBs cksum variable, increments the Rx packet count and passes the SKB
* to the upper layer. If the checksum is wrong, it increments the Rx
* packet error count, frees the SKB and returns error.
+ * Return value:
+ * SUCCESS on success and -1 on failure.
*/
-static int rxOsmHandler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no)
+#ifndef CONFIG_2BUFF_MODE
+static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no)
+#else
+static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
+ buffAdd_t * ba)
+#endif
{
struct net_device *dev = (struct net_device *) sp->dev;
struct sk_buff *skb =
(struct sk_buff *) ((unsigned long) rxdp->Host_Control);
u16 l3_csum, l4_csum;
+#ifdef CONFIG_2BUFF_MODE
+ int buf0_len, buf2_len;
+ struct ethhdr *eth = (struct ethhdr *) ba->ba_0;
+#endif
l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && (sp->rx_csum)) {
l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
- /* NIC verifies if the Checksum of the received
+ /*
+ * NIC verifies if the Checksum of the received
* frame is Ok or not and accordingly returns
* a flag in the RxD.
*/
@@ -3833,9 +4498,37 @@
skb->ip_summed = CHECKSUM_NONE;
}
+ if (rxdp->Control_1 & RXD_T_CODE) {
+ unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
+ DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
+ dev->name, err);
+ }
+#ifdef CONFIG_2BUFF_MODE
+ buf0_len = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
+ buf2_len = RXD_GET_BUFFER2_SIZE(rxdp->Control_2);
+#endif
+
skb->dev = dev;
+#ifndef CONFIG_2BUFF_MODE
skb_put(skb, len);
skb->protocol = eth_type_trans(skb, dev);
+#else
+ skb_put(skb, buf2_len);
+ /*
+ * Reproducing eth_type_trans functionality and running
+ * on the ethernet header 'eth' stripped and given to us
+ * by the hardware in 2Buff mode.
+ */
+ if (*eth->h_dest & 1) {
+ if (!memcmp(eth->h_dest, dev->broadcast, ETH_ALEN))
+ skb->pkt_type = PACKET_BROADCAST;
+ else
+ skb->pkt_type = PACKET_MULTICAST;
+ } else if (memcmp(eth->h_dest, dev->dev_addr, ETH_ALEN)) {
+ skb->pkt_type = PACKET_OTHERHOST;
+ }
+ skb->protocol = eth->h_proto;
+#endif
#ifdef CONFIG_S2IO_NAPI
netif_receive_skb(skb);
@@ -3844,20 +4537,20 @@
#endif
dev->last_rx = jiffies;
-#if DEBUG_ON
- sp->rxpkt_cnt++;
-#endif
sp->rx_pkt_count++;
sp->stats.rx_packets++;
+#ifndef CONFIG_2BUFF_MODE
sp->stats.rx_bytes += len;
- sp->rxpkt_bytes += len;
+#else
+ sp->stats.rx_bytes += buf0_len + buf2_len;
+#endif
atomic_dec(&sp->rx_bufs_left[ring_no]);
rxdp->Host_Control = 0;
return SUCCESS;
}
-int check_for_txSpace(nic_t * sp)
+int check_for_tx_space(nic_t * sp)
{
u32 put_off, get_off, queue_len;
int ret = TRUE, i;
@@ -3876,18 +4569,19 @@
return ret;
}
-/*
-* Input Argument/s:
-* sp - private member of the device structure, which is a pointer to the
-* s2io_nic structure.
-* link - inidicates whether link is UP/DOWN.
-* Return value:
-* void.
-* Description:
-* This function stops/starts the Tx queue depending on whether the link
-* status of the NIC is is down or up. This is called by the Alarm interrupt
-* handler whenever a link change interrupt comes up.
-*/
+/**
+ * s2io_link - stops/starts the Tx queue.
+ * @sp : private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * @link : inidicates whether link is UP/DOWN.
+ * Description:
+ * This function stops/starts the Tx queue depending on whether the link
+ * status of the NIC is is down or up. This is called by the Alarm
+ * interrupt handler whenever a link change interrupt comes up.
+ * Return value:
+ * void.
+ */
+
void s2io_link(nic_t * sp, int link)
{
struct net_device *dev = (struct net_device *) sp->dev;
@@ -3896,29 +4590,23 @@
if (link == LINK_DOWN) {
DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
netif_carrier_off(dev);
- netif_stop_queue(dev);
} else {
DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
netif_carrier_on(dev);
- if (check_for_txSpace(sp) == TRUE) {
- /* Don't wake the queue, if we know there
- * are no free TxDs available.
- */
- netif_wake_queue(dev);
- }
}
}
sp->last_link_state = link;
}
-/*
-* Input Argument/s:
-* pdev - structure containing the PCI related information of the device.
-* Return value:
-* returns the revision ID of the device.
-* Description:
-* Function to identify the Revision ID of xena.
-*/
+/**
+ * get_xena_rev_id - to identify revision ID of xena.
+ * @pdev : PCI Dev structure
+ * Description:
+ * Function to identify the Revision ID of xena.
+ * Return value:
+ * returns the revision ID of the device.
+ */
+
int get_xena_rev_id(struct pci_dev *pdev)
{
u8 id = 0;
@@ -3927,21 +4615,22 @@
return id;
}
-/*
-* Input Argument/s:
-* sp - private member of the device structure, which is a pointer to the
-* s2io_nic structure.
-* Return value:
-* void
-* Description:
-* This function initializes a few of the PCI and PCI-X configuration registers
-* with recommended values.
-*/
+/**
+ * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
+ * @sp : private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * Description:
+ * This function initializes a few of the PCI and PCI-X configuration registers
+ * with recommended values.
+ * Return value:
+ * void
+ */
+
static void s2io_init_pci(nic_t * sp)
{
u16 pci_cmd = 0;
-/* Enable Data Parity Error Recovery in PCI-X command register. */
+ /* Enable Data Parity Error Recovery in PCI-X command register. */
pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
&(sp->pcix_cmd));
pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
@@ -3949,13 +4638,13 @@
pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
&(sp->pcix_cmd));
-/* Set the PErr Response bit in PCI command register. */
+ /* Set the PErr Response bit in PCI command register. */
pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
pci_write_config_word(sp->pdev, PCI_COMMAND,
(pci_cmd | PCI_COMMAND_PARITY));
pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
-/* Set user specified value in Latency Timer */
+ /* Set user specified value in Latency Timer */
if (latency_timer) {
pci_write_config_byte(sp->pdev, PCI_LATENCY_TIMER,
latency_timer);
@@ -3963,49 +4652,97 @@
&latency_timer);
}
-/* Set MMRB count to 4096 in PCI-X Command register. */
+ /* Set MMRB count to 4096 in PCI-X Command register. */
+ sp->pcix_cmd &= 0xFFF3;
pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
- (sp->pcix_cmd | 0x0C));
+ (sp->pcix_cmd | (max_read_byte_cnt << 2)));
pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
&(sp->pcix_cmd));
-/* Setting Maximum outstanding splits to two for now. */
- sp->pcix_cmd &= 0xFF1F;
+ /* Setting Maximum outstanding splits based on system type. */
+ sp->pcix_cmd &= 0xFF8F;
- sp->pcix_cmd |=
- XENA_MAX_OUTSTANDING_SPLITS(XENA_TWO_SPLIT_TRANSACTION);
+ sp->pcix_cmd |= XENA_MAX_OUTSTANDING_SPLITS(max_splits_trans);
+ pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
+ sp->pcix_cmd);
+ pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
+ &(sp->pcix_cmd));
+ /* Forcibly disabling relaxed ordering capability of the card. */
+ sp->pcix_cmd &= 0xfffd;
pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
sp->pcix_cmd);
pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
&(sp->pcix_cmd));
-
}
MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@s2io.com>");
MODULE_LICENSE("GPL");
-MODULE_PARM(ring_num, "1-" __MODULE_STRING(1) "i");
-MODULE_PARM(frame_len, "1-" __MODULE_STRING(8) "i");
-MODULE_PARM(ring_len, "1-" __MODULE_STRING(8) "i");
-MODULE_PARM(fifo_num, "1-" __MODULE_STRING(1) "i");
-MODULE_PARM(fifo_len, "1-" __MODULE_STRING(8) "i");
-MODULE_PARM(rx_prio, "1-" __MODULE_STRING(1) "i");
-MODULE_PARM(tx_prio, "1-" __MODULE_STRING(1) "i");
-MODULE_PARM(latency_timer, "1-" __MODULE_STRING(1) "i");
-
-/*
-* Input Argument/s:
-* pdev - structure containing the PCI related information of the device.
-* pre - the List of PCI devices supported by the driver listed in s2io_tbl.
-* Return value:
-* returns '0' on success and negative on failure.
-* Description:
-* The function initializes an adapter identified by the pci_dec structure.
-* All OS related initialization including memory and device structure and
-* initlaization of the device private variable is done. Also the swapper
-* control register is initialized to enable read and write into the I/O
-* registers of the device.
-*
-*/
+MODULE_PARM(lso_enable, "i");
+#ifndef CONFIG_S2IO_NAPI
+MODULE_PARM(indicate_max_pkts, "i");
+#endif
+MODULE_PARM(cksum_offload_enable, "i");
+MODULE_PARM(TxFifoNum, "i");
+MODULE_PARM(TxFIFOLen_0, "i");
+MODULE_PARM(TxFIFOLen_1, "i");
+MODULE_PARM(TxFIFOLen_2, "i");
+MODULE_PARM(TxFIFOLen_3, "i");
+MODULE_PARM(TxFIFOLen_4, "i");
+MODULE_PARM(TxFIFOLen_5, "i");
+MODULE_PARM(TxFIFOLen_6, "i");
+MODULE_PARM(TxFIFOLen_7, "i");
+MODULE_PARM(MaxTxDs, "i");
+MODULE_PARM(RxRingNum, "i");
+MODULE_PARM(RxRingSz_0, "i");
+MODULE_PARM(RxRingSz_1, "i");
+MODULE_PARM(RxRingSz_2, "i");
+MODULE_PARM(RxRingSz_3, "i");
+MODULE_PARM(RxRingSz_4, "i");
+MODULE_PARM(RxRingSz_5, "i");
+MODULE_PARM(RxRingSz_6, "i");
+MODULE_PARM(RxRingSz_7, "i");
+MODULE_PARM(Stats_refresh_time, "i");
+MODULE_PARM(rmac_pause_time, "i");
+MODULE_PARM(mc_pause_threshold_q0q3, "i");
+MODULE_PARM(mc_pause_threshold_q4q7, "i");
+MODULE_PARM(shared_splits, "i");
+MODULE_PARM(max_splits_trans, "i");
+MODULE_PARM(tmac_util_period, "i");
+MODULE_PARM(rmac_util_period, "i");
+MODULE_PARM(tx_timer_val, "i");
+MODULE_PARM(tx_utilz_periodic, "i");
+MODULE_PARM(rx_timer_val, "i");
+MODULE_PARM(rx_utilz_periodic, "i");
+MODULE_PARM(tx_urange_a, "i");
+MODULE_PARM(tx_ufc_a, "i");
+MODULE_PARM(tx_urange_b, "i");
+MODULE_PARM(tx_ufc_b, "i");
+MODULE_PARM(tx_urange_c, "i");
+MODULE_PARM(tx_ufc_c, "i");
+MODULE_PARM(tx_ufc_d, "i");
+MODULE_PARM(rx_urange_a, "i");
+MODULE_PARM(rx_ufc_a, "i");
+MODULE_PARM(rx_urange_b, "i");
+MODULE_PARM(rx_ufc_b, "i");
+MODULE_PARM(rx_urange_c, "i");
+MODULE_PARM(rx_ufc_c, "i");
+MODULE_PARM(rx_ufc_d, "i");
+MODULE_PARM(latency_timer, "i");
+MODULE_PARM(max_read_byte_cnt, "i");
+/**
+ * s2io_init_nic - Initialization of the adapter .
+ * @pdev : structure containing the PCI related information of the device.
+ * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
+ * Description:
+ * The function initializes an adapter identified by the pci_dec structure.
+ * All OS related initialization including memory and device structure and
+ * initlaization of the device private variable is done. Also the swapper
+ * control register is initialized to enable read and write into the I/O
+ * registers of the device.
+ * Return value:
+ * returns 0 on success and negative on failure.
+ */
+
static int __devinit
s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
{
@@ -4031,6 +4768,7 @@
if (!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
dma_flag = TRUE;
+
if (pci_set_consistent_dma_mask
(pdev, 0xffffffffffffffffULL)) {
DBG_PRINT(ERR_DBG,
@@ -4080,7 +4818,8 @@
/* Initialize some PCI/PCI-X fields of the NIC. */
s2io_init_pci(sp);
- /* Setting the device configuration parameters.
+ /*
+ * Setting the device configuration parameters.
* Most of these parameters can be specified by the user during
* module insertion as they are module loadable parameters. If
* these parameters are not not specified during load time, they
@@ -4090,69 +4829,63 @@
config = &sp->config;
/* Tx side parameters. */
- config->TxFIFONum = fifo_num ? fifo_num : 1;
-
- if (!fifo_len[0] && (fifo_num > 1)) {
- printk(KERN_ERR "Fifo Lens not specified for all FIFOs\n");
- goto init_failed;
- }
-
- if (fifo_len[0]) {
- int cnt;
-
- for (cnt = 0; fifo_len[cnt]; cnt++);
- if (fifo_num) {
- if (cnt < fifo_num) {
- printk(KERN_ERR
- "Fifo Lens not specified for ");
- printk(KERN_ERR "all FIFOs\n");
- goto init_failed;
- }
- }
- for (cnt = 0; cnt < config->TxFIFONum; cnt++) {
- config->TxCfg[cnt].FifoLen = fifo_len[cnt];
- config->TxCfg[cnt].FifoPriority = cnt;
- }
- } else {
- config->TxCfg[0].FifoLen = DEFAULT_FIFO_LEN;
- config->TxCfg[0].FifoPriority = 0;
- }
+ config->TxFIFONum = TxFifoNum;
+ config->tx_cfg[0].FifoLen = TxFIFOLen_0;
+ config->tx_cfg[0].FifoPriority = 0;
+ config->tx_cfg[1].FifoLen = TxFIFOLen_1;
+ config->tx_cfg[1].FifoPriority = 1;
+ config->tx_cfg[2].FifoLen = TxFIFOLen_2;
+ config->tx_cfg[2].FifoPriority = 2;
+ config->tx_cfg[3].FifoLen = TxFIFOLen_3;
+ config->tx_cfg[3].FifoPriority = 3;
+ config->tx_cfg[4].FifoLen = TxFIFOLen_4;
+ config->tx_cfg[4].FifoPriority = 4;
+ config->tx_cfg[5].FifoLen = TxFIFOLen_5;
+ config->tx_cfg[5].FifoPriority = 5;
+ config->tx_cfg[6].FifoLen = TxFIFOLen_6;
+ config->tx_cfg[6].FifoPriority = 6;
+ config->tx_cfg[7].FifoLen = TxFIFOLen_7;
+ config->tx_cfg[7].FifoPriority = 7;
config->TxIntrType = TXD_INT_TYPE_UTILZ;
for (i = 0; i < config->TxFIFONum; i++) {
- if (config->TxCfg[i].FifoLen < 65) {
+ config->tx_cfg[i].fNoSnoop =
+ (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
+ if (config->tx_cfg[i].FifoLen < 65) {
config->TxIntrType = TXD_INT_TYPE_PER_LIST;
break;
}
}
-
- config->TxCfg[0].fNoSnoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
config->MaxTxDs = MAX_SKB_FRAGS;
config->TxFlow = TRUE;
/* Rx side parameters. */
- config->RxRingNum = ring_num ? ring_num : 1;
-
- if (ring_len[0]) {
- int cnt;
- for (cnt = 0; cnt < config->RxRingNum; cnt++) {
- config->RxCfg[cnt].NumRxd = ring_len[cnt];
- config->RxCfg[cnt].RingPriority = cnt;
- }
- } else {
- int id;
- if ((id = get_xena_rev_id(pdev)) == 1) {
- config->RxCfg[0].NumRxd = LARGE_RXD_CNT;
-
- } else {
- config->RxCfg[0].NumRxd = SMALL_RXD_CNT;
- }
- config->RxCfg[0].RingPriority = 0;
+ config->RxRingNum = RxRingNum;
+ config->rx_cfg[0].NumRxd = RxRingSz_0 * (MAX_RXDS_PER_BLOCK + 1);
+ config->rx_cfg[0].RingPriority = 0;
+ config->rx_cfg[1].NumRxd = RxRingSz_1 * (MAX_RXDS_PER_BLOCK + 1);
+ config->rx_cfg[1].RingPriority = 1;
+ config->rx_cfg[2].NumRxd = RxRingSz_2 * (MAX_RXDS_PER_BLOCK + 1);
+ config->rx_cfg[2].RingPriority = 2;
+ config->rx_cfg[3].NumRxd = RxRingSz_3 * (MAX_RXDS_PER_BLOCK + 1);
+ config->rx_cfg[3].RingPriority = 3;
+ config->rx_cfg[4].NumRxd = RxRingSz_4 * (MAX_RXDS_PER_BLOCK + 1);
+ config->rx_cfg[4].RingPriority = 4;
+ config->rx_cfg[5].NumRxd = RxRingSz_5 * (MAX_RXDS_PER_BLOCK + 1);
+ config->rx_cfg[5].RingPriority = 5;
+ config->rx_cfg[6].NumRxd = RxRingSz_6 * (MAX_RXDS_PER_BLOCK + 1);
+ config->rx_cfg[6].RingPriority = 6;
+ config->rx_cfg[7].NumRxd = RxRingSz_7 * (MAX_RXDS_PER_BLOCK + 1);
+ config->rx_cfg[7].RingPriority = 7;
+
+ for (i = 0; i < RxRingNum; i++) {
+ config->rx_cfg[i].RingOrg = RING_ORG_BUFF1;
+ config->rx_cfg[i].RxdThresh = DEFAULT_RXD_THRESHOLD;
+ config->rx_cfg[i].fNoSnoop =
+ (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
+ config->rx_cfg[i].RxD_BackOff_Interval = TBD;
}
- config->RxCfg[0].RingOrg = RING_ORG_BUFF1;
- config->RxCfg[0].RxdThresh = DEFAULT_RXD_THRESHOLD;
- config->RxCfg[0].fNoSnoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
- config->RxCfg[0].RxD_BackOff_Interval = TBD;
+
config->RxFlow = TRUE;
/* Miscellaneous parameters. */
@@ -4162,14 +4895,17 @@
/* Setting Mac Control parameters */
mac_control->txdl_len = MAX_SKB_FRAGS;
- mac_control->rmac_pause_time = 0;
+ mac_control->rmac_pause_time = rmac_pause_time;
+ mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
+ mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
+
/* Initialize Ring buffer parameters. */
for (i = 0; i < config->RxRingNum; i++)
atomic_set(&sp->rx_bufs_left[i], 0);
/* initialize the shared memory used by the NIC and the host */
- if (initSharedMem(sp)) {
+ if (init_shared_mem(sp)) {
DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
dev->name);
goto mem_alloc_failed;
@@ -4208,22 +4944,26 @@
dev->set_multicast_list = &s2io_set_multicast;
dev->do_ioctl = &s2io_ioctl;
dev->change_mtu = &s2io_change_mtu;
+#ifdef SET_ETHTOOL_OPS
SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
-
+#endif
/*
* will use eth_mac_addr() for dev->set_mac_address
* mac address will be set every time dev->open() is called
*/
#ifdef CONFIG_S2IO_NAPI
dev->poll = s2io_poll;
- dev->weight = 128; /* For now. */
+ dev->weight = 90; /* For now. */
#endif
- dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
+ dev->features |= NETIF_F_SG;
+ if (cksum_offload_enable)
+ dev->features |= NETIF_F_IP_CSUM;
if (sp->high_dma_flag == TRUE)
dev->features |= NETIF_F_HIGHDMA;
#ifdef NETIF_F_TSO
- dev->features |= NETIF_F_TSO;
+ if (lso_enable)
+ dev->features |= NETIF_F_TSO;
#endif
dev->tx_timeout = &s2io_tx_watchdog;
@@ -4233,11 +4973,6 @@
INIT_WORK(&sp->set_link_task,
(void (*)(void *)) s2io_set_link, sp);
- if (register_netdev(dev)) {
- DBG_PRINT(ERR_DBG, "Device registration failed\n");
- goto register_failed;
- }
-
pci_save_state(sp->pdev, sp->config_space);
/* Setting swapper control on the NIC, for proper reset operation */
@@ -4248,10 +4983,11 @@
}
/* Fix for all "FFs" MAC address problems observed on Alpha platforms */
- FixMacAddress(sp);
+ fix_mac_address(sp);
s2io_reset(sp);
- /* Setting swapper control on the NIC, so the MAC address can be read.
+ /*
+ * Setting swapper control on the NIC, so the MAC address can be read.
*/
if (s2io_set_swapper(sp)) {
DBG_PRINT(ERR_DBG,
@@ -4260,50 +4996,54 @@
goto set_swap_failed;
}
- /* MAC address initialization.
- * For now only one mac address will be read and used.
+ /*
+ * MAC address initialization.
+ * For now only one mac address will be read and used.
*/
bar0 = (XENA_dev_config_t *) sp->bar0;
val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
writeq(val64, &bar0->rmac_addr_cmd_mem);
- waitForCmdComplete(sp);
+ wait_for_cmd_complete(sp);
tmp64 = readq(&bar0->rmac_addr_data0_mem);
mac_down = (u32) tmp64;
mac_up = (u32) (tmp64 >> 32);
- memset(sp->defMacAddr[0].mac_addr, 0, sizeof(ETH_ALEN));
+ memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
- sp->defMacAddr[0].mac_addr[3] = (u8) (mac_up);
- sp->defMacAddr[0].mac_addr[2] = (u8) (mac_up >> 8);
- sp->defMacAddr[0].mac_addr[1] = (u8) (mac_up >> 16);
- sp->defMacAddr[0].mac_addr[0] = (u8) (mac_up >> 24);
- sp->defMacAddr[0].mac_addr[5] = (u8) (mac_down >> 16);
- sp->defMacAddr[0].mac_addr[4] = (u8) (mac_down >> 24);
+ sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
+ sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
+ sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
+ sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
+ sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
+ sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
DBG_PRINT(INIT_DBG,
"DEFAULT MAC ADDR:0x%02x-%02x-%02x-%02x-%02x-%02x\n",
- sp->defMacAddr[0].mac_addr[0],
- sp->defMacAddr[0].mac_addr[1],
- sp->defMacAddr[0].mac_addr[2],
- sp->defMacAddr[0].mac_addr[3],
- sp->defMacAddr[0].mac_addr[4],
- sp->defMacAddr[0].mac_addr[5]);
+ sp->def_mac_addr[0].mac_addr[0],
+ sp->def_mac_addr[0].mac_addr[1],
+ sp->def_mac_addr[0].mac_addr[2],
+ sp->def_mac_addr[0].mac_addr[3],
+ sp->def_mac_addr[0].mac_addr[4],
+ sp->def_mac_addr[0].mac_addr[5]);
/* Set the factory defined MAC address initially */
dev->addr_len = ETH_ALEN;
- memcpy(dev->dev_addr, sp->defMacAddr, ETH_ALEN);
+ memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
/* Initialize the tasklet status flag */
atomic_set(&(sp->tasklet_status), 0);
/* Initialize spinlocks */
- spin_lock_init(&sp->isr_lock);
spin_lock_init(&sp->tx_lock);
+#ifndef CONFIG_S2IO_NAPI
+ spin_lock_init(&sp->put_lock);
+#endif
- /* SXE-002: Configure link and activity LED to init state
+ /*
+ * SXE-002: Configure link and activity LED to init state
* on driver load.
*/
subid = sp->pdev->subsystem_device;
@@ -4316,27 +5056,47 @@
val64 = readq(&bar0->gpio_control);
}
- /* Make Link state as off at this point, when the Link change
+ sp->rx_csum = 1; /* Rx chksum verify enabled by default */
+
+#ifdef SNMP_SUPPORT
+ if (!s2io_bdsnmp_init(dev))
+ DBG_PRINT(INIT_DBG,
+ "Error Creating Proc directory for SNMP\n");
+
+ sp->nLinkStatus = 1;
+#ifdef NETIF_F_TSO
+ sp->nFeature = 1;
+#endif
+ memcpy(sp->cVersion, s2io_driver_version + 8, 20);
+ memcpy(sp->cName, s2io_driver_name, 20);
+ struct timeval tm;
+ do_gettimeofday(&tm);
+ sp->lDate = tm.tv_sec;
+#endif
+
+ if (register_netdev(dev)) {
+ DBG_PRINT(ERR_DBG, "Device registration failed\n");
+ goto register_failed;
+ }
+
+ /*
+ * Make Link state as off at this point, when the Link change
* interrupt comes the state will be automatically changed to
* the right state.
*/
netif_carrier_off(dev);
sp->last_link_state = LINK_DOWN;
- sp->rx_csum = 1; /* Rx chksum verify enabled by default */
-
return 0;
- set_swap_failed:
- unregister_netdev(dev);
register_failed:
+ set_swap_failed:
iounmap(sp->bar1);
bar1_remap_failed:
iounmap(sp->bar0);
bar0_remap_failed:
mem_alloc_failed:
- freeSharedMem(sp);
- init_failed:
+ free_shared_mem(sp);
pci_disable_device(pdev);
pci_release_regions(pdev);
pci_set_drvdata(pdev, NULL);
@@ -4345,16 +5105,15 @@
return -ENODEV;
}
-/*
-* Input Argument/s:
-* pdev - structure containing the PCI related information of the device.
-* Return value:
-* void
-* Description:
-* This function is called by the Pci subsystem to release a PCI device
-* and free up all resource held up by the device. This could be in response
-* to a Hot plug event or when the driver is to be removed from memory.
-*/
+/**
+ * s2io_rem_nic - Free the PCI device
+ * @pdev: structure containing the PCI related information of the device.
+ * Description: This function is called by the Pci subsystem to release a
+ * PCI device and free up all resource held up by the device. This could
+ * be in response to a Hot plug event or when the driver is to be removed
+ * from memory.
+ */
+
static void __devexit s2io_rem_nic(struct pci_dev *pdev)
{
struct net_device *dev =
@@ -4365,24 +5124,41 @@
DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
return;
}
+
sp = dev->priv;
- freeSharedMem(sp);
+ unregister_netdev(dev);
+
+ free_shared_mem(sp);
iounmap(sp->bar0);
iounmap(sp->bar1);
pci_disable_device(pdev);
pci_release_regions(pdev);
pci_set_drvdata(pdev, NULL);
-
- unregister_netdev(dev);
+#ifdef SNMP_SUPPORT
+ s2io_bdsnmp_rem(dev);
+#endif
free_netdev(dev);
}
+/**
+ * s2io_starter - Entry point for the driver
+ * Description: This function is the entry point for the driver. It verifies
+ * the module loadable parameters and initializes PCI configuration space.
+ */
+
int __init s2io_starter(void)
{
+ if (verify_load_parm())
+ return -ENODEV;
return pci_module_init(&s2io_driver);
}
+/**
+ * s2io_closer - Cleanup routine for the driver
+ * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
+ */
+
void s2io_closer(void)
{
pci_unregister_driver(&s2io_driver);
@@ -4391,3 +5167,571 @@
module_init(s2io_starter);
module_exit(s2io_closer);
+/**
+ * verify_load_parm - verifies the module loadable parameters
+ * Descriptions: Verifies the module loadable paramters and initializes the
+ * Tx Fifo, Rx Ring and other paramters.
+ */
+
+int verify_load_parm()
+{
+ int fail = 0;
+ if (!((lso_enable == 0) || (lso_enable == 1))) {
+ printk("lso_enable can be either '1' or '0'\n");
+ fail = 1;
+ }
+#ifndef CONFIG_S2IO_NAPI
+ if ((indicate_max_pkts > (0xFFFFFFFF))) {
+ printk
+ ("indicate_max_pkts can take value greater than zero but less than 2power(32)\n");
+ fail = 1;
+ }
+#endif
+ if (!((cksum_offload_enable == 0) || (cksum_offload_enable == 1))) {
+ printk("cksum_offload_enable can be only '0' or '1' \n");
+ fail = 1;
+ }
+ if ((TxFifoNum == 0) || (TxFifoNum > 8)) {
+ printk("TxFifoNum can take value from 1 to 8\n");
+ fail = 1;
+ }
+ switch (TxFifoNum) {
+ case 8:
+ if ((TxFIFOLen_7 == 0) || TxFIFOLen_7 > 8192) {
+ printk
+ ("TxFIFOLen_7 can take value from 1 to 8192\n");
+ fail = 1;
+ }
+ case 7:
+ if ((TxFIFOLen_6 == 0) || TxFIFOLen_6 > 8192) {
+ printk
+ ("TxFIFOLen_6 can take value from 1 to 8192\n");
+ fail = 1;
+ }
+ case 6:
+ if ((TxFIFOLen_5 == 0) || TxFIFOLen_5 > 8192) {
+ printk
+ ("TxFIFOLen_5 can take value from 1 to 8192\n");
+ fail = 1;
+ }
+ case 5:
+ if ((TxFIFOLen_4 == 0) || TxFIFOLen_4 > 8192) {
+ printk
+ ("TxFIFOLen_4 can take value from 1 to 8192\n");
+ fail = 1;
+ }
+ case 4:
+ if ((TxFIFOLen_3 == 0) || TxFIFOLen_3 > 8192) {
+ printk
+ ("TxFIFOLen_3 can take value from 1 to 8192\n");
+ fail = 1;
+ }
+ case 3:
+ if ((TxFIFOLen_2 == 0) || TxFIFOLen_2 > 8192) {
+ printk
+ ("TxFIFOLen_2 can take value from 1 to 8192\n");
+ fail = 1;
+ }
+ case 2:
+ if ((TxFIFOLen_1 == 0) || TxFIFOLen_1 > 8192) {
+ printk
+ ("TxFIFOLen_1 can take value from 1 to 8192\n");
+ fail = 1;
+ }
+ case 1:
+ if ((TxFIFOLen_0 == 0) || TxFIFOLen_0 > 8192) {
+ printk
+ ("TxFIFOLen_0 can take value from 1 to 8192\n");
+ fail = 1;
+ }
+ }
+ if ((MaxTxDs > 32) || (MaxTxDs < 1)) {
+ printk("MaxTxDs can take falue from 1 to 32\n");
+ fail = 1;
+ }
+ if ((RxRingNum > 8) || (RxRingNum < 1)) {
+ printk("RxRingNum can take falue from 1 to 8\n");
+ fail = 1;
+ }
+ switch (RxRingNum) {
+ case 8:
+ if (RxRingSz_7 < 1) {
+ printk
+ ("RxRingSz_7 can take value greater than 0\n");
+ fail = 1;
+ }
+ case 7:
+ if (RxRingSz_6 < 1) {
+ printk
+ ("RxRingSz_6 can take value greater than 0\n");
+ fail = 1;
+ }
+ case 6:
+ if (RxRingSz_5 < 1) {
+ printk
+ ("RxRingSz_5 can take value greater than 0\n");
+ fail = 1;
+ }
+ case 5:
+ if (RxRingSz_4 < 1) {
+ printk
+ ("RxRingSz_4 can take value greater than 0\n");
+ fail = 1;
+ }
+ case 4:
+ if (RxRingSz_3 < 1) {
+ printk
+ ("RxRingSz_3 can take value greater than 0\n");
+ fail = 1;
+ }
+ case 3:
+ if (RxRingSz_2 < 1) {
+ printk
+ ("RxRingSz_2 can take value greater than 0\n");
+ fail = 1;
+ }
+ case 2:
+ if (RxRingSz_1 < 1) {
+ printk
+ ("RxRingSz_1 can take value greater than 0\n");
+ fail = 1;
+ }
+ case 1:
+ if (RxRingSz_0 < 1) {
+ printk
+ ("RxRingSz_0 can take value greater than 0\n");
+ fail = 1;
+ }
+ }
+ if ((Stats_refresh_time < 1)) {
+ printk
+ ("Stats_refresh_time cannot be less than 1 second \n");
+ fail = 1;
+ }
+ if (((rmac_pause_time < 0x10) && (rmac_pause_time != 0)) ||
+ (rmac_pause_time > 0xFFFF)) {
+ printk
+ ("rmac_pause_time can take value from 16 to 65535\n");
+ fail = 1;
+ }
+ if ((max_splits_trans < 0) || (max_splits_trans > 7)) {
+ printk("max_splits_trans can take value from 0 to 7\n");
+ fail = 1;
+ }
+ if ((mc_pause_threshold_q0q3 > 0xFE)) {
+ printk("mc_pause_threshold_q0q3 cannot exceed 254\n");
+ fail = 1;
+ }
+ if ((mc_pause_threshold_q4q7 > 0xFE)) {
+ printk("mc_pause_threshold_q4q7 cannot exceed 254\n");
+ fail = 1;
+ }
+ if ((latency_timer)
+ && ((latency_timer < 8) || (latency_timer > 255))) {
+ printk("latency_timer can take value from 8 to 255\n");
+ fail = 1;
+ }
+ if (max_read_byte_cnt > 3) {
+ printk("max_read_byte_cnt can take value from 0 to 3\n");
+ fail = 1;
+ }
+ if ((shared_splits > 31)) {
+ printk("shared_splits cannot exceed 31\n");
+ fail = 1;
+ }
+ if (rmac_util_period > 0xF) {
+ printk("rmac_util_period cannot exceed 15\n");
+ fail = 1;
+ }
+ if (tmac_util_period > 0xF) {
+ printk("tmac_util_period cannot exceed 15\n");
+ fail = 1;
+ }
+ if ((tx_utilz_periodic > 1) || (rx_utilz_periodic > 1)) {
+ printk
+ ("tx_utilz_periodic & rx_utilz_periodic can be either "
+ "'0' or '1'\n");
+ fail = 1;
+ }
+ if ((tx_urange_a > 127) || (tx_urange_b > 127)
+ || (tx_urange_c > 127)) {
+ printk
+ ("tx_urange_a, tx_urange_b & tx_urange_c can take value "
+ "from 0 to 127\n");
+ fail = 1;
+ }
+ if ((rx_urange_a > 127) || (rx_urange_b > 127)
+ || (rx_urange_c > 127)) {
+ printk
+ ("rx_urange_a, rx_urange_b & rx_urange_c can take value "
+ "from 0 to 127\n");
+ fail = 1;
+ }
+ if ((tx_ufc_a > 0xffff) || (tx_ufc_b > 0xffff) ||
+ (tx_ufc_c > 0xffff) || (tx_ufc_d > 0xffff)) {
+ printk
+ (" tx_ufc_a, tx_ufc_b, tx_ufc_c, tx_ufc_d can take value"
+ "from 0 to 65535(0xFFFF)\n");
+ fail = 1;
+ }
+ if ((rx_ufc_a > 0xffff) || (rx_ufc_b > 0xffff) ||
+ (rx_ufc_c > 0xffff) || (rx_ufc_d > 0xffff)) {
+ printk
+ (" rx_ufc_a, rx_ufc_b, rx_ufc_c, rx_ufc_d can take value"
+ "from 0 to 65535(0xFFFF)\n");
+ fail = 1;
+ }
+ return fail;
+}
+
+#ifdef SNMP_SUPPORT
+/**
+ * fnBaseDrv - Get the driver information
+ * @pBaseDrv -Pointer to Base driver structure which contains the offset
+ * and length of each of the field.
+ * Description
+ * This function copies the driver specific information from the dev structure
+ * to the pBaseDrv stucture. It calculates the number of physical adapters by
+ * parsing the dev_base global variable maintained by the kernel. This
+ * variable has to read locked before accesing.This function is called by
+ * fnBaseReadProc function.
+ *
+ */
+
+static void fnBaseDrv(struct stBaseDrv *pBaseDrv, struct net_device *dev)
+{
+
+ struct pci_dev *pdev = NULL;
+ struct net_device *ndev;
+ int nCount = 0;
+ nic_t *sp = (nic_t *) dev->priv;
+
+ strncpy(pBaseDrv->m_cName, sp->cName, 20);
+ strncpy(pBaseDrv->m_cVersion, sp->cVersion, 20);
+ pBaseDrv->m_nStatus = sp->nLinkStatus;
+ pBaseDrv->m_nFeature = sp->nFeature;
+ pBaseDrv->m_nMemorySize = sp->nMemorySize;
+ sprintf(pBaseDrv->m_cDate, "%ld", sp->lDate);
+ /*
+ * Find all the ethernet devices on the system using
+ * pci_find_class. Get the private data which will be the
+ * net_device structure assigned by the driver.
+ */
+ while ((pdev =
+ pci_find_class((PCI_CLASS_NETWORK_ETHERNET << 8), pdev))) {
+ ndev = (struct net_device *) pci_get_drvdata(pdev);
+ if (ndev == NULL)
+ break;
+ memcpy(pBaseDrv->m_stPhyAdap[nCount].m_cName, ndev->name,
+ 20);
+ pBaseDrv->m_stPhyAdap[nCount].m_nIndex = ndev->ifindex;
+ nCount++;
+ }
+ pBaseDrv->m_nPhyCnt = nCount;
+}
+
+/*
+ * fnBaseReadProc - Read entry point for the proc file
+ * @page - Buffer pointer where the data is written
+ * @start- Pointer to buffer ptr . It is used if the data is more than a page
+ * @off- the offset to the page where data is written
+ * @count - number of bytes to write
+ * @eof - to indicate end of file
+ * @data - pointer to device structure.
+ *
+ * Description -
+ * This function gets Base driver specific information from the fnBaseDrv
+ * function and writes into the BDInfo file. This function is called whenever
+ * the user reads the file. The length of data written cannot exceed 4kb.
+ * If it exceeds then use the start pointer to write multiple pages
+ * Return - the length of the string written to proc file
+ */
+static int fnBaseReadProc(char *page, char **start, off_t off, int count,
+ int *eof, void *data)
+{
+ struct stBaseDrv *pBaseDrv;
+ int nLength = 0;
+ int nCount = 0;
+ struct net_device *dev = (struct net_device *) data;
+ int nIndex = 0;
+
+ pBaseDrv = kmalloc(sizeof(struct stBaseDrv), GFP_KERNEL);
+ if (pBaseDrv == NULL) {
+ printk("Error allocating memory\n");
+ return -ENOMEM;
+ }
+ fnBaseDrv(pBaseDrv, dev);
+ sprintf(page + nLength, "%-30s%-20s\n", "Base Driver Name",
+ pBaseDrv->m_cName);
+ nLength += 51;
+ if (pBaseDrv->m_nStatus == 1)
+ sprintf(page + nLength, "%-30s%-20s\n", "Load Status",
+ "Loaded");
+ else
+ sprintf(page + nLength, "%-30s%-20s\n", "Load Status",
+ "UnLoaded");
+ nLength += 51;
+ sprintf(page + nLength, "%-30s%-20s\n", "Base Driver Version",
+ pBaseDrv->m_cVersion);
+ nLength += 51;
+
+ sprintf(page + nLength, "%-30s%-20d\n", "Feature Supported",
+ pBaseDrv->m_nFeature);
+ nLength += 51;
+
+ sprintf(page + nLength, "%-30s%-20d\n",
+ "Base Driver Memrory in Bytes", pBaseDrv->m_nMemorySize);
+ nLength += 51;
+
+ sprintf(page + nLength, "%-30s%-20s\n", "Base Driver Date",
+ pBaseDrv->m_cDate);
+ nLength += 51;
+
+ sprintf(page + nLength, "%-30s%-20d\n", "No of Phy Adapter",
+ pBaseDrv->m_nPhyCnt);
+ nLength += 51;
+ sprintf(page + nLength, "%-20s%-20s\n\n", "Phy Adapter Index",
+ "Phy Adapter Name");
+ nLength += 42;
+
+ for (nIndex = 0, nCount = pBaseDrv->m_nPhyCnt; nCount != 0;
+ nCount--, nIndex++) {
+ sprintf(page + nLength, "%-20d%-20s\n",
+ pBaseDrv->m_stPhyAdap[nIndex].m_nIndex,
+ pBaseDrv->m_stPhyAdap[nIndex].m_cName);
+ nLength += 41;
+ }
+
+ *eof = 1;
+ kfree(pBaseDrv);
+ return nLength;
+}
+
+/*
+ * fnPhyAdapReadProc - Read entry point for the proc file
+ * @page - Buffer pointer where the data is written
+ * @start- Pointer to buffer ptr . It is used if the data is more than a page
+ * @off- the offset to the page where data is written
+ * @count - number of bytes to write
+ * @eof - to indicate end of file
+ * @data - pointer to device structure.
+ *
+ * Description -
+ * This function gets physical adapter information. This function is called
+ * whenever the use* r reads the file. The length of data written cannot
+ * exceed 4kb. If it exceeds then use the start pointer to write multiple page
+ *
+ * Return - the length of the string written to proc file
+ */
+static int fnPhyAdapReadProc(char *page, char **start, off_t off,
+ int count, int *eof, void *data)
+{
+
+ struct stPhyData *pPhyData;
+ pPhyData = kmalloc(sizeof(struct stPhyData), GFP_KERNEL);
+ if (pPhyData == NULL) {
+ printk("Error allocating memory\n");
+ return -ENOMEM;
+ }
+
+ struct net_device *pNetDev;
+ struct net_device_stats *pNetStat;
+ int nLength = 0;
+ unsigned char cMAC[20];
+
+ /* Print the header in the PhyAdap proc file */
+ sprintf(page + nLength,
+ "%-10s%-22s%-10s%-10s%-22s%-22s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s%-10s\n",
+ "Index", "Description", "Mode", "Type", "Speed", "MAC",
+ "Status", "Slot", "Bus", "IRQ", "Colis", "Multi",
+ "RxBytes", "RxDrop", "RxError", "RxPacket", "TRxBytes",
+ "TRxDrop", "TxError", "TxPacket");
+
+ /* 237 is the lenght of the above string copied in the page */
+ nLength += 237;
+
+ struct pci_dev *pdev = NULL;
+ /*
+ * pci_find_class will return to the pointer to the pdev structure
+ * for all the network devices using PCI_CLASS_NETWORK_ETHERNET.
+ * The third argument is pointer to previous pdev structure.Initailly
+ * it has to be null
+ */
+ while ((pdev =
+ pci_find_class((PCI_CLASS_NETWORK_ETHERNET << 8), pdev))) {
+ /* Private data will point to the netdevice structure */
+ pNetDev = (struct net_device *) pci_get_drvdata(pdev);
+ if (pNetDev == NULL)
+ continue;
+ if (pNetDev->addr_len != 0) {
+ pNetStat = pNetDev->get_stats(pNetDev);
+ pPhyData->m_nIndex = pNetDev->ifindex;
+ memcpy(pPhyData->m_cDesc, pNetDev->name, 20);
+ pPhyData->m_nMode = 0;
+ pPhyData->m_nType = 0;
+ switch (pPhyData->m_nType) {
+ /* case IFT_ETHER:
+ memcpy(pPhyData->m_cSpeed,"10000000",20);
+ break;
+
+ case 9:
+ memcpy(pPhyData->m_cSpeed,"4000000",20);
+ break; */
+ default:
+ memcpy(pPhyData->m_cSpeed, "10000000", 20);
+ break;
+ }
+ memcpy(pPhyData->m_cPMAC, pNetDev->dev_addr,
+ ETH_ALEN);
+ memcpy(pPhyData->m_cCMAC, pNetDev->dev_addr,
+ ETH_ALEN);
+ pPhyData->m_nLinkStatus =
+ test_bit(__LINK_STATE_START, &pNetDev->state);
+ pPhyData->m_nPCISlot = PCI_SLOT(pdev->devfn);
+ pPhyData->m_nPCIBus = pdev->bus->number;
+ pPhyData->m_nIRQ = pNetDev->irq;
+ pPhyData->m_nCollision = pNetStat->collisions;
+ pPhyData->m_nMulticast = pNetStat->multicast;
+
+ pPhyData->m_nRxBytes = pNetStat->rx_bytes;
+ pPhyData->m_nRxDropped = pNetStat->rx_dropped;
+ pPhyData->m_nRxErrors = pNetStat->rx_errors;
+ pPhyData->m_nRxPackets = pNetStat->rx_packets;
+
+ pPhyData->m_nTxBytes = pNetStat->tx_bytes;
+ pPhyData->m_nTxDropped = pNetStat->tx_dropped;
+ pPhyData->m_nTxErrors = pNetStat->tx_errors;
+ pPhyData->m_nTxPackets = pNetStat->tx_packets;
+
+ sprintf(cMAC, "%02x:%02x:%02x:%02x:%02x:%02x",
+ pPhyData->m_cPMAC[0], pPhyData->m_cPMAC[1],
+ pPhyData->m_cPMAC[2], pPhyData->m_cPMAC[3],
+ pPhyData->m_cPMAC[4],
+ pPhyData->m_cPMAC[5]);
+
+ sprintf(page + nLength,
+ "%-10d%-22s%-10d%-10d%-22s%-22s%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d%-10d\n",
+ pPhyData->m_nIndex, pPhyData->m_cDesc,
+ pPhyData->m_nMode, pPhyData->m_nType,
+ pPhyData->m_cSpeed, cMAC,
+ pPhyData->m_nLinkStatus,
+ pPhyData->m_nPCISlot, pPhyData->m_nPCIBus,
+ pPhyData->m_nIRQ, pPhyData->m_nCollision,
+ pPhyData->m_nMulticast,
+ pPhyData->m_nRxBytes,
+ pPhyData->m_nRxDropped,
+ pPhyData->m_nRxErrors,
+ pPhyData->m_nRxPackets,
+ pPhyData->m_nTxBytes,
+ pPhyData->m_nTxDropped,
+ pPhyData->m_nTxErrors,
+ pPhyData->m_nTxPackets);
+ nLength += 237;
+ }
+ }
+
+ *eof = 1;
+
+ kfree(pPhyData);
+ return nLength;
+}
+
+/*
+ * s2io_bdsnmp_init - Entry point to create proc file
+ * @dev- Pointer to net device structure passed by the driver.
+ * Return
+ * Success If creates all the files
+ * ERROR_PROC_ENTRY /ERROR_PROC_DIR Error If could not create all the files
+ * Description
+ * This functon is called when the driver is loaded. It creates the S2IO
+ * proc file system in the /proc/net/ directory. This directory is used to
+ * store the info about the base driver afm driver, lacp, vlan and nplus.
+ * It checks if S2IO directory already exists else creates it and creates
+ * the files BDInfo files and assiciates read function to each of the files.
+ */
+
+int s2io_bdsnmp_init(struct net_device *dev)
+{
+ struct proc_dir_entry *S2ioDir;
+ struct proc_dir_entry *BaseDrv;
+ struct proc_dir_entry *PhyAdap;
+ int nLength = 0;
+
+ nLength = strlen(S2IODIRNAME);
+ /* IF the directory already exists then just return */
+ for (S2ioDir = proc_net->subdir; S2ioDir != NULL;
+ S2ioDir = S2ioDir->next) {
+ if ((S2ioDir->namelen == nLength)
+ && (!memcmp(S2ioDir->name, S2IODIRNAME, nLength)))
+ break;
+ }
+ if (S2ioDir == NULL)
+ /* Create the s2io directory */
+ if (!
+ (S2ioDir =
+ create_proc_entry(S2IODIRNAME, S_IFDIR, proc_net))) {
+ DBG_PRINT(INIT_DBG,
+ "Error Creating Proc directory for SNMP\n");
+ return ERROR_PROC_DIR;
+ }
+ /*
+ * Create the BDInfo file to store driver info and associate
+ * read funtion.
+ */
+ if (!
+ (BaseDrv =
+ create_proc_read_entry(BDFILENAME, S_IFREG | S_IRUSR, S2ioDir,
+ fnBaseReadProc, (void *) dev))) {
+ DBG_PRINT(INIT_DBG,
+ "Error Creating Proc File for Base Drvr\n");
+ return ERROR_PROC_ENTRY;
+ }
+ if (!
+ (PhyAdap =
+ create_proc_read_entry(PADAPFILENAME, S_IFREG | S_IRUSR,
+ S2ioDir, fnPhyAdapReadProc,
+ (void *) dev))) {
+ DBG_PRINT(INIT_DBG,
+ "Error Creating Proc File for Phys Adap\n");
+ return ERROR_PROC_ENTRY;
+ }
+
+
+ return SUCCESS;
+}
+
+/**
+ * s2io_bdsnmp_rem : Removes the proc file entry
+ * @dev - pointer to netdevice structre
+ * Return - void
+ * Description
+ * This functon is called when the driver is Unloaded. It checks if the
+ * S2IO directoy exists and deletes the files in the reverse order of
+ * creation.
+ */
+
+void s2io_bdsnmp_rem(struct net_device *dev)
+{
+ int nLength = 0;
+ struct proc_dir_entry *S2ioDir;
+ nLength = strlen(S2IODIRNAME);
+ /*
+ * Check if the S2IO directory exists or not and then delete
+ * all the files in the S2IO Directory
+ */
+ for (S2ioDir = proc_net->subdir; S2ioDir != NULL;
+ S2ioDir = S2ioDir->next) {
+ if ((S2ioDir->namelen == nLength)
+ && (!memcmp(S2ioDir->name, S2IODIRNAME, nLength)))
+
+ break;
+ }
+ if (S2ioDir == NULL)
+ return;
+ remove_proc_entry(BDFILENAME, S2ioDir);
+ remove_proc_entry(PADAPFILENAME, S2ioDir);
+ if (S2ioDir->subdir == NULL) {
+ remove_proc_entry(S2IODIRNAME, proc_net);
+ }
+}
+#endif
diff -urN vanilla_linux-2.6.7/drivers/net/s2io.h linux-2.6.7/drivers/net/s2io.h
--- vanilla_linux-2.6.7/drivers/net/s2io.h 2004-06-15 22:19:09.000000000 -0700
+++ linux-2.6.7/drivers/net/s2io.h 2004-09-08 12:55:02.000000000 -0700
@@ -16,6 +16,7 @@
#define TBD 0
#define BIT(loc) (0x8000000000000000ULL >> (loc))
#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
+#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
#ifndef BOOL
#define BOOL int
@@ -49,11 +50,13 @@
#define ALIGN_SIZE 127
#define PCIX_COMMAND_REGISTER 0x62
+#ifndef SET_ETHTOOL_OPS
+#define SUPPORTED_10000baseT_Full (1 << 12)
+#endif
+
/*
* Debug related variables.
*/
-#define DEBUG_ON TRUE
-
/* different debug levels. */
#define ERR_DBG 0
#define INIT_DBG 1
@@ -375,7 +378,7 @@
u32 TxFIFONum; /*Number of Tx FIFOs */
#define MAX_TX_FIFOS 8
- tx_fifo_config_t TxCfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
+ tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
u32 MaxTxDs; /*Max no. of Tx buffer descriptor per TxDL */
BOOL TxVLANEnable; /*TRUE: Insert VLAN ID, FALSE: Don't insert */
#define TX_REQ_TIMEOUT_DEFAULT 0x0
@@ -403,7 +406,7 @@
#define MAX_RX_RINGS 8
#define MAX_RX_BLOCKS_PER_RING 150
- rx_ring_config_t RxCfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
+ rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
BOOL RxVLANEnable; /*TRUE: Strip off VLAN tag from the frame,
FALSE: Don't strip off VLAN tag */
@@ -492,6 +495,12 @@
u64 Host_Control; /* reserved for host */
} TxD_t;
+/* Structure to hold the phy and virt addr of every TxDL. */
+typedef struct list_info_hold {
+ dma_addr_t list_phy_addr;
+ void *list_virt_addr;
+} list_info_hold_t;
+
/* Rx descriptor structure */
typedef struct _RxD_t {
u64 Host_Control; /* reserved for host */
@@ -508,36 +517,80 @@
#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
u64 Control_2;
+#ifndef CONFIG_2BUFF_MODE
#define MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)
#define SET_BUFFER0_SIZE(val) vBIT(val,0,16)
+#else
+#define MASK_BUFFER0_SIZE vBIT(0xFF,0,16)
+#define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
+#define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
+#define SET_BUFFER0_SIZE(val) vBIT(val,8,8)
+#define SET_BUFFER1_SIZE(val) vBIT(val,16,16)
+#define SET_BUFFER2_SIZE(val) vBIT(val,32,16)
+#endif
+
#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
#define SET_VLAN_TAG(val) vBIT(val,48,16)
#define SET_NUM_TAG(val) vBIT(val,16,32)
+#ifndef CONFIG_2BUFF_MODE
#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16)))
-/*
-#define TXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) >> (63-31))
-#define TXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) >> (63-47))
-*/
+#else
+#define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \
+ >> 48)
+#define RXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) \
+ >> 32)
+#define RXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) \
+ >> 16)
+#define BUF0_LEN 40
+#define BUF1_LEN 1
+#endif
+
u64 Buffer0_ptr;
+#ifdef CONFIG_2BUFF_MODE
+ u64 Buffer1_ptr;
+ u64 Buffer2_ptr;
+#endif
} RxD_t;
-
/* Structure that represents the Rx descriptor block which contains
* 128 Rx descriptors.
*/
+#ifndef CONFIG_2BUFF_MODE
typedef struct _RxD_block {
#define MAX_RXDS_PER_BLOCK 127
RxD_t rxd[MAX_RXDS_PER_BLOCK];
u64 reserved_0;
#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
- u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd in this blk */
- u64 reserved_2_pNext_RxD_block; /*@ Logical ptr to next */
- u64 pNext_RxD_Blk_physical; /* Buff0_ptr.
- In a 32 bit arch the upper 32 bits
- should be 0 */
+ u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
+ * Rxd in this blk */
+ u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
+ u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
+ * the upper 32 bits should
+ * be 0 */
+} RxD_block_t;
+#else
+typedef struct _RxD_block {
+#define MAX_RXDS_PER_BLOCK 85
+ RxD_t rxd[MAX_RXDS_PER_BLOCK];
+
+#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
+ u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd
+ * in this blk */
+ u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */
} RxD_block_t;
+#define SIZE_OF_BLOCK 4096
+
+/* Structure to hold virtual addresses of Buf0 and Buf1 in
+ * 2buf mode. */
+typedef struct bufAdd {
+ void *ba_0_org;
+ void *ba_1_org;
+ void *ba_0;
+ void *ba_1;
+} buffAdd_t;
+#endif
/* Structure which stores all the MAC control parameters */
@@ -570,8 +623,6 @@
typedef struct mac_info {
/* rx side stuff */
u32 rxd_ring_mem_sz;
- RxD_t *RxRing[MAX_RX_RINGS]; /* Logical Rx ring pointers */
- dma_addr_t RxRing_Phy[MAX_RX_RINGS];
/* Put pointer info which indictes which RxD has to be replenished
* with a new buffer.
@@ -584,6 +635,9 @@
rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS];
u16 rmac_pause_time;
+ u16 mc_pause_threshold_q0q3;
+ u16 mc_pause_threshold_q4q7;
+
/* this will be used in receive function, this decides which ring would
be processed first. eg: ring with priority value 0 (highest) should
@@ -618,7 +672,7 @@
void *stats_mem; /* orignal pointer to allocated mem */
dma_addr_t stats_mem_phy; /* Physical address of the stat block */
u32 stats_mem_sz;
- StatInfo_t *StatsInfo; /* Logical address of the stat block */
+ StatInfo_t *stats_info; /* Logical address of the stat block */
} mac_info_t;
/* structure representing the user defined MAC addresses */
@@ -633,13 +687,20 @@
dma_addr_t block_dma_addr;
} rx_block_info_t;
+/* Default Tunable parameters of the NIC. */
+#define DEFAULT_FIFO_LEN 4096
+#define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1)
+#define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1)
+#define SMALL_BLK_CNT 30
+#define LARGE_BLK_CNT 100
+
/* Structure representing one instance of the NIC */
typedef struct s2io_nic {
#define MAX_MAC_SUPPORTED 16
#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
- macaddr_t defMacAddr[MAX_MAC_SUPPORTED];
- macaddr_t preMacAddr[MAX_MAC_SUPPORTED];
+ macaddr_t def_mac_addr[MAX_MAC_SUPPORTED];
+ macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];
struct net_device_stats stats;
caddr_t bar0;
@@ -672,8 +733,10 @@
u32 irq;
atomic_t rx_bufs_left[MAX_RX_RINGS];
- spinlock_t isr_lock;
spinlock_t tx_lock;
+#ifndef CONFIG_S2IO_NAPI
+ spinlock_t put_lock;
+#endif
#define PROMISC 1
#define ALL_MULTI 2
@@ -692,23 +755,22 @@
u16 tx_err_count;
u16 rx_err_count;
-#if DEBUG_ON
- u64 rxpkt_bytes;
- u64 txpkt_bytes;
- int int_cnt;
- int rxint_cnt;
- int txint_cnt;
- u64 rxpkt_cnt;
+#ifndef CONFIG_S2IO_NAPI
+ /* Index to the absolute position of the put pointer of Rx ring. */
+ int put_pos;
#endif
- /* Place holders for the virtual and physical addresses of
+ /*
+ * Place holders for the virtual and physical addresses of
* all the Rx Blocks
*/
- struct rx_block_info
- rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
+ rx_block_info_t rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
int block_count[MAX_RX_RINGS];
int pkt_cnt[MAX_RX_RINGS];
+ /* Place holder of all the TX List's Phy and Virt addresses. */
+ list_info_hold_t *list_info[MAX_TX_FIFOS];
+
/* Id timer, used to blink NIC to physically identify NIC. */
struct timer_list id_timer;
@@ -738,24 +800,34 @@
u16 last_link_state;
#define LINK_DOWN 1
#define LINK_UP 2
+
+#ifdef CONFIG_2BUFF_MODE
+ /* Buffer Address store. */
+ buffAdd_t **ba[MAX_RX_RINGS];
+#endif
+ int task_flag;
+#ifdef SNMP_SUPPORT
+ char cName[20];
+ int nMemorySize;
+ int nLinkStatus;
+ int nFeature;
+ char cVersion[20];
+ long lDate;
+#endif
+
} nic_t;
#define RESET_ERROR 1;
#define CMD_ERROR 2;
-/* Default Tunable parameters of the NIC. */
-#define DEFAULT_FIFO_LEN 4096
-#define SMALL_RXD_CNT 40 * (MAX_RXDS_PER_BLOCK+1)
-#define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1)
-
/* OS related system calls */
#ifndef readq
static inline u64 readq(void *addr)
{
u64 ret = 0;
ret = readl(addr + 4);
- ret <<= 32;
- ret |= readl(addr);
+ (u64) ret <<= 32;
+ (u64) ret |= readl(addr);
return ret;
}
@@ -767,6 +839,25 @@
writel((u32) (val), addr);
writel((u32) (val >> 32), (addr + 4));
}
+
+/* In 32 bit modes, some registers have to be written in a
+ * particular order to expect correct hardware operation. The
+ * macro SPECIAL_REG_WRITE is used to perform such ordered
+ * writes. Defines UF (Upper First) and LF (Lower First) will
+ * be used to specify the required write order.
+ */
+#define UF 1
+#define LF 2
+#define SPECIAL_REG_WRITE(val, addr, order) \
+ if (order == LF) { \
+ writel((u32) (val), addr); \
+ writel((u32) (val >> 32), (addr + 4)); \
+ } else { \
+ writel((u32) (val >> 32), (addr + 4)); \
+ writel((u32) (val), addr); \
+ }
+#else
+#define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr)
#endif
/* Interrupt related values of Xena */
@@ -817,30 +908,41 @@
/* DMA level Inressupts */
#define TXDMA_PFC_INT_M BIT(0)
- /* PFC block interrupts */
+#define TXDMA_PCC_INT_M BIT(2)
+
+/* PFC block interrupts */
#define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
+/* PCC block interrupts. */
+#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
+ PCC_FB_ECC Error. */
+
/*
* Prototype declaration.
*/
static int __devinit s2io_init_nic(struct pci_dev *pdev,
const struct pci_device_id *pre);
static void __devexit s2io_rem_nic(struct pci_dev *pdev);
-static int initSharedMem(struct s2io_nic *sp);
-static void freeSharedMem(struct s2io_nic *sp);
-static int initNic(struct s2io_nic *nic);
+static int init_shared_mem(struct s2io_nic *sp);
+static void free_shared_mem(struct s2io_nic *sp);
+static int init_nic(struct s2io_nic *nic);
#ifndef CONFIG_S2IO_NAPI
-static void rxIntrHandler(struct s2io_nic *sp);
+static void rx_intr_handler(struct s2io_nic *sp);
#endif
-static void txIntrHandler(struct s2io_nic *sp);
-static void alarmIntrHandler(struct s2io_nic *sp);
+static void tx_intr_handler(struct s2io_nic *sp);
+static void alarm_intr_handler(struct s2io_nic *sp);
static int s2io_starter(void);
void s2io_closer(void);
static void s2io_tx_watchdog(struct net_device *dev);
static void s2io_tasklet(unsigned long dev_addr);
static void s2io_set_multicast(struct net_device *dev);
-static int rxOsmHandler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);
+#ifndef CONFIG_2BUFF_MODE
+static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);
+#else
+static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
+ buffAdd_t * ba);
+#endif
void s2io_link(nic_t * sp, int link);
void s2io_reset(nic_t * sp);
#ifdef CONFIG_S2IO_NAPI
@@ -850,6 +952,70 @@
int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
static int verify_xena_quiescence(u64 val64, int flag);
+int verify_load_parm(void);
+#ifdef SET_ETHTOOL_OPS
static struct ethtool_ops netdev_ethtool_ops;
+#endif
+static void s2io_set_link(unsigned long data);
+
+#ifdef SNMP_SUPPORT
+
+#define S2IODIRNAME "S2IO"
+#define BDFILENAME "BDInfo"
+#define PADAPFILENAME "PhyAdap"
+#define ERROR_PROC_DIR -20
+#define ERROR_PROC_ENTRY -21
+
+struct stDrvData {
+ struct stBaseDrv *pBaseDrv;
+};
+
+struct stPhyAdap {
+ int m_nIndex;
+ char m_cName[20];
+};
+struct stBaseDrv {
+ char m_cName[21];
+ int m_nStatus;
+ char m_cVersion[21];
+ int m_nFeature;
+ int m_nMemorySize;
+ char m_cDate[21];
+ int m_nPhyCnt;
+ char m_cPhyIndex[21];
+ struct stPhyAdap m_stPhyAdap[5];
+};
+
+struct stPhyData {
+ int m_nIndex;
+ unsigned char m_cDesc[20];
+ int m_nMode;
+ int m_nType;
+ char m_cSpeed[20];
+ unsigned char m_cPMAC[20];
+ unsigned char m_cCMAC[20];
+ int m_nLinkStatus;
+ int m_nPCISlot;
+ int m_nPCIBus;
+ int m_nIRQ;
+ int m_nCollision;
+ int m_nMulticast;
+
+ int m_nRxBytes;
+ int m_nRxDropped;
+ int m_nRxErrors;
+ int m_nRxPackets;
+ int m_nTxBytes;
+ int m_nTxDropped;
+ int m_nTxErrors;
+ int m_nTxPackets;
+
+
+};
+
+static int s2io_bdsnmp_init(struct net_device *dev);
+static void s2io_bdsnmp_rem(struct net_device *dev);
+#endif
+
#endif /* _S2IO_H */
next prev parent reply other threads:[~2004-09-13 17:09 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-08-14 0:19 Patch submission for S2io Xframe driver to 2.6 kernel Ravinandan Arakali
2004-08-14 4:27 ` TCP hardware assists Leonid Grossman
2004-08-21 6:21 ` Patch submission for S2io Xframe driver to 2.6 kernel Randy.Dunlap
2004-08-21 23:43 ` Francois Romieu
2004-08-28 23:36 ` Jeff Garzik
2004-08-29 5:53 ` Leonid Grossman
2004-08-30 17:25 ` Ravinandan Arakali
2004-09-13 17:09 ` Ravinandan Arakali [this message]
2004-09-17 0:38 ` Jeff Garzik
2004-09-17 0:53 ` Ravinandan Arakali
2004-09-17 0:52 ` Jeff Garzik
2004-09-17 3:07 ` Randy.Dunlap
2004-09-28 0:42 ` Ravinandan Arakali
2004-09-28 3:54 ` Randy.Dunlap
2004-09-28 15:05 ` Jeff Garzik
2004-09-28 17:13 ` Ravinandan Arakali
2004-10-06 20:14 ` Ravinandan Arakali
2004-10-06 20:09 ` Jeff Garzik
2004-10-06 20:20 ` Francois Romieu
2004-10-06 22:52 ` Jeff Garzik
2004-10-07 1:04 ` [PATCH 2.6.9-rc2 1/8] S2io: cosmetic changes Ravinandan Arakali
2004-09-17 3:58 ` Patch submission for S2io Xframe driver to 2.6 kernel Randy.Dunlap
-- strict thread matches above, loose matches on Subject: below --
2004-09-13 22:45 Ravinandan Arakali
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