Re: [PATCH net-next v6 2/2] net: macb: distribute evenly Tx SRAM segments

[Nicolai Buchwitz <nb@tipi-net.de>]

On 13.11.2026 18:32, Théo Lebrun wrote:
> GEM has registers to configure the Tx SRAM segments distribution across
> queues. The reset value is apprioriate (even spread) but we need to
> care if/when number of active queues is modified (or if we inherited
> unevenly initialised hardware from bootloader).
> 
> To distribute segments, we take as input the number of queues
> (ctx->num_queues) and the number of segments (found inside DCFG6).
> Its output is a number of segments for each queue, formatted as
> powers-of-two (eg 2 for queue 0 means it has 2^2=4 segments).
> 
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
>  drivers/net/ethernet/cadence/macb.h      | 14 ++++++
>  drivers/net/ethernet/cadence/macb_main.c | 76 
> +++++++++++++++++++++++++++++++-

> [...]

>  static void macb_init_hw(struct macb *bp)
>  {
>  	u32 config;
> @@ -3465,6 +3522,20 @@ static void macb_init_hw(struct macb *bp)
>  	if (bp->caps & MACB_CAPS_JUMBO)
>  		bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
> 
> +	/* Distribute Tx SRAM segments evenly based on active number of 
> queues.
> +	 * TXQSEGALLOC is only documented for some GEM integrations.
> +	 */
> +	if (bp->caps & MACB_CAPS_TXQSEGALLOC) {
> +		unsigned int num_segments;
> +		u32 val;
> +
> +		num_segments = 1U << GEM_BFEXT(SEGMENTS_BIT_SIZE,
> +					       gem_readl(bp, DCFG6));
> +		val = gem_sram_distribute_segments(bp->ctx->num_queues,
> +						   num_segments);
> +		gem_writel(bp, TXQSEGALLOC_LOWER, val);

This only runs on open, not on a context swap. So ethtool -L on a
running interface keeps the old split until the next down/up?

> [...]

Regards,
Nicolai