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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org References: <20261010105900.247342-1-tanure@linux.com> <20261010105900.247342-5-tanure@linux.com> Content-Language: en-US From: Lucas Tanure In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 12/10/2026 13:30, Andrew Lunn wrote: >> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c >> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c >> @@ -82,6 +82,7 @@ struct meson8b_dwmac_data { >> int (*set_phy_mode)(struct meson8b_dwmac *dwmac); >> bool has_prg_eth1_rgmii_rx_delay; >> bool has_pipeline_clk; >> + bool mac_applies_dt_delays; > > Please can you invert this and call it broken delays. > > We should make it clear that new devices should not set this, because > it wrong, broken. Moved to a function for T7. And the previous SoCs have their own function which gets a comment that new SoCs must not use it. > >> +static int meson_dwmac_init_dt_delays(struct meson8b_dwmac *dwmac, >> + struct plat_stmmacenet_data *plat_dat) >> +{ >> + struct device_node *np = dwmac->dev->of_node; >> + u32 tx_delay_ps = 0, rx_delay_ps = 0; >> + phy_interface_t phy_mode; >> + bool mac_tx, mac_rx; >> + >> + mac_tx = !of_property_read_u32(np, "tx-internal-delay-ps", &tx_delay_ps); >> + mac_rx = !of_property_read_u32(np, "rx-internal-delay-ps", &rx_delay_ps); >> + >> + /* one step is a quarter of the RGMII clock period, 2ns at 1Gbit/s */ >> + if (tx_delay_ps > 6000 || tx_delay_ps % 2000) >> + return dev_err_probe(dwmac->dev, -EINVAL, >> + "The RGMII TX delay must be 0, 2000, 4000 or 6000ps\n"); > > tx-internal-delay is not listed in amlogic,meson-dwmac.yaml. Please > could you add it, and list the valid values. Patch 2 of this series adds it to the T7 block with the valid values. That changes in v4, see below. > > Do you have access to the datasheet? Could you check these numbers are > correct, because they are larger than typical. 4ns, and 6ns makes no > sense, the RGMII standard only calls for 2ns. Yes. The field is not a delay line. It selects the phase of the TX clock sent to the PHY: 0, 1/4, 1/2 or 3/4 of the clock period. At 1Gbit/s that is 0, 2, 4 or 6ns, which is where the numbers come from (the existing amlogic,tx-delay-ns property lists the same four). Only 1/4 is a usable RGMII delay; 1/2 is an inverted clock and 3/4 is a 2ns lead. And since it is a fraction of the period, the 2ns is only true at 1Gbit/s, at 100Mbit/s the same setting is 10ns. I agree 4000 and 6000 make no sense. > >> + >> + /* the RX delay line moves in 200ps steps and reaches 3000ps */ >> + if (rx_delay_ps > 3000 || rx_delay_ps % 200) >> + return dev_err_probe(dwmac->dev, -EINVAL, >> + "The RGMII RX delay range is 0..3000ps in 200ps steps\n"); > > Please could you listing these values in the binding. > > Also, mark that amlogic,tx-delay-ns & amlogic,rx-delay-ns are not > valid for this compatible. The RX values are in patch 2 as well, the T7 shares the G12A list (0..3000ps in 200ps steps); v4 drops the 0. The two vendor properties are already rejected for the T7: they are only defined for the older compatibles and the schema has unevaluatedProperties: false. v4 adds an explicit "false" for both in the T7 block so that it is visible. > >> + >> + phy_mode = phy_fix_phy_mode_for_mac_delays(dwmac->phy_mode, mac_tx, >> + mac_rx); > > This is not correct. This function assumes mac_tx and mac_rx are > Boolean values, the MAC is applying the full 2ns delay. However, if > rx-internal-delay-ps is only providing 200ps, that is not true. > > I would prefer you keep to the usual way of doing things. Allow the > MAC to apply small tuning delays, but have the PHY do the 2ns. So > don't make any modification to phy-mode. > OK. v4 does not touch phy-mode. rx-internal-delay-ps becomes the tuning the MAC adds on top, 200..3000ps. On the TX side the T7 has nothing small to offer, the only step is the 2ns phase, so v4 does not accept tx-internal-delay-ps on the T7 at all, in the binding and in the driver. The VIM4 then uses plain rgmii-id with the PHY adding both delays. That also removes the wrong claim in patch 7 that the RTL8211F TX delay does not work; the real cause was a bootloader value left in the glue register, details in my reply to Martin on patch 7. >> static int meson8b_init_rgmii_delays(struct meson8b_dwmac *dwmac) >> { >> u32 tx_dly_config, rx_adj_config, cfg_rxclk_dly, delay_config; >> @@ -411,32 +455,34 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) >> dwmac->dev = &pdev->dev; >> dwmac->phy_mode = plat_dat->phy_interface; >> >> - /* use 2ns as fallback since this value was previously hardcoded */ >> - if (of_property_read_u32(pdev->dev.of_node, "amlogic,tx-delay-ns", >> - &dwmac->tx_delay_ns)) >> - dwmac->tx_delay_ns = 2; >> - >> - /* RX delay defaults to 0ps since this is what many boards use */ >> - if (of_property_read_u32(pdev->dev.of_node, "rx-internal-delay-ps", >> - &dwmac->rx_delay_ps)) { >> - if (!of_property_read_u32(pdev->dev.of_node, >> - "amlogic,rx-delay-ns", >> - &dwmac->rx_delay_ps)) >> - /* convert ns to ps */ >> - dwmac->rx_delay_ps *= 1000; >> - } >> - >> - if (dwmac->data->has_prg_eth1_rgmii_rx_delay) { >> - if (dwmac->rx_delay_ps > 3000 || dwmac->rx_delay_ps % 200) { >> - dev_err(dwmac->dev, >> - "The RGMII RX delay range is 0..3000ps in 200ps steps"); >> - return -EINVAL; >> + if (!dwmac->data->mac_applies_dt_delays) { > > I suggest you do this at a higher level. Either call this function if > _broken_delay is set, or the other one. Done through the callback. Probe makes one call, and the parsing of the vendor properties moves into the older function. > > Andrew