From: "Jiawen Wu" <jiawenwu@trustnetic.com>
To: "'Andrew Lunn'" <andrew@lunn.ch>
Cc: <netdev@vger.kernel.org>, <jarkko.nikula@linux.intel.com>,
<andriy.shevchenko@linux.intel.com>,
<mika.westerberg@linux.intel.com>, <jsd@semihalf.com>,
<Jose.Abreu@synopsys.com>, <hkallweit1@gmail.com>,
<linux@armlinux.org.uk>, <linux-i2c@vger.kernel.org>,
<linux-gpio@vger.kernel.org>, <mengyuanlou@net-swift.com>
Subject: RE: [PATCH net-next v7 6/9] net: txgbe: Support GPIO to SFP socket
Date: Fri, 12 May 2023 14:35:38 +0800 [thread overview]
Message-ID: <019101d9849b$f7354100$e59fc300$@trustnetic.com> (raw)
In-Reply-To: <f9e0da51-6c55-4768-aa27-437bb7f19888@lunn.ch>
On Thursday, May 11, 2023 8:39 PM, Andrew Lunn wrote:
> > +static int txgbe_gpio_set_type(struct irq_data *d, unsigned int type)
> > +{
> > + struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
> > + irq_hw_number_t hwirq = irqd_to_hwirq(d);
> > + struct wx *wx = gpiochip_get_data(gc);
> > + u32 level, polarity;
> > +
> > + level = rd32(wx, WX_GPIO_INTTYPE_LEVEL);
> > + polarity = rd32(wx, WX_GPIO_POLARITY);
> > +
> > + switch (type) {
> > + case IRQ_TYPE_EDGE_BOTH:
> > + level |= BIT(hwirq);
> > + break;
> > + case IRQ_TYPE_EDGE_RISING:
> > + level |= BIT(hwirq);
> > + polarity |= BIT(hwirq);
> > + break;
> > + case IRQ_TYPE_EDGE_FALLING:
> > + level |= BIT(hwirq);
> > + polarity &= ~BIT(hwirq);
> > + break;
> > + case IRQ_TYPE_LEVEL_HIGH:
> > + level &= ~BIT(hwirq);
> > + polarity |= BIT(hwirq);
> > + break;
> > + case IRQ_TYPE_LEVEL_LOW:
> > + level &= ~BIT(hwirq);
> > + polarity &= ~BIT(hwirq);
> > + break;
> > + }
>
> You have two configuration bits, level and polarity, yet handle 5 different types?
>
> > + wr32m(wx, WX_GPIO_INTEN, BIT(hwirq), BIT(hwirq));
> > + wr32(wx, WX_GPIO_INTTYPE_LEVEL, level);
> > + if (type != IRQ_TYPE_EDGE_BOTH)
> > + wr32(wx, WX_GPIO_POLARITY, polarity);
>
> If we are interested in both edges, then polarity is meaningless. So i can
> understand not writing it. But how does the hardware know polarity should not
> be used?
I will add toggle trigger to set polarity in both edges, to solve the hysteretic
interrupts problem that has been bothering me.
next prev parent reply other threads:[~2023-05-12 6:38 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-09 2:27 [PATCH net-next v7 0/9] TXGBE PHYLINK support Jiawen Wu
2023-05-09 2:27 ` [PATCH net-next v7 1/9] net: txgbe: Add software nodes to support phylink Jiawen Wu
2023-05-09 12:38 ` Piotr Raczynski
2023-05-09 2:27 ` [PATCH net-next v7 2/9] i2c: designware: Add driver support for Wangxun 10Gb NIC Jiawen Wu
2023-05-09 13:52 ` Piotr Raczynski
2023-05-10 6:43 ` Jiawen Wu
2023-05-10 7:47 ` andy.shevchenko
2023-05-10 8:00 ` Jiawen Wu
2023-05-09 2:27 ` [PATCH net-next v7 3/9] net: txgbe: Register fixed rate clock Jiawen Wu
2023-05-09 15:32 ` Simon Horman
2023-05-10 6:47 ` Jiawen Wu
2023-05-09 2:27 ` [PATCH net-next v7 4/9] net: txgbe: Register I2C platform device Jiawen Wu
2023-05-11 12:13 ` Andrew Lunn
2023-05-11 20:16 ` Piotr Raczynski
2023-05-09 2:27 ` [PATCH net-next v7 5/9] net: txgbe: Add SFP module identify Jiawen Wu
2023-05-11 12:13 ` Andrew Lunn
2023-05-11 20:18 ` Piotr Raczynski
2023-05-09 2:27 ` [PATCH net-next v7 6/9] net: txgbe: Support GPIO to SFP socket Jiawen Wu
2023-05-11 12:31 ` Andrew Lunn
2023-05-12 6:38 ` Jiawen Wu
2023-05-12 14:20 ` Andrew Lunn
2023-05-11 12:38 ` Andrew Lunn
2023-05-12 6:35 ` Jiawen Wu [this message]
2023-05-11 20:45 ` andy.shevchenko
2023-05-12 8:57 ` Jiawen Wu
2023-05-12 9:43 ` Andy Shevchenko
2023-05-12 9:32 ` Russell King (Oracle)
2023-05-12 10:46 ` Jiawen Wu
2023-05-09 2:27 ` [PATCH net-next v7 7/9] net: pcs: Add 10GBASE-R mode for Synopsys Designware XPCS Jiawen Wu
2023-05-11 12:40 ` Andrew Lunn
2023-05-09 2:27 ` [PATCH net-next v7 8/9] net: txgbe: Implement phylink pcs Jiawen Wu
2023-05-11 19:33 ` Andrew Lunn
2023-05-11 20:32 ` Piotr Raczynski
2023-05-12 9:22 ` Jiawen Wu
2023-05-09 2:27 ` [PATCH net-next v7 9/9] net: txgbe: Support phylink MAC layer Jiawen Wu
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