From: "Jiawen Wu" <jiawenwu@trustnetic.com>
To: "'Russell King \(Oracle\)'" <linux@armlinux.org.uk>
Cc: "'Simon Horman'" <simon.horman@corigine.com>, <kabel@kernel.org>,
<andrew@lunn.ch>, <hkallweit1@gmail.com>, <davem@davemloft.net>,
<edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>,
<netdev@vger.kernel.org>
Subject: RE: [PATCH net] net: phy: marvell10g: fix 88x3310 power up
Date: Wed, 19 Jul 2023 16:38:36 +0800 [thread overview]
Message-ID: <01b701d9ba1c$691d9fa0$3b58dee0$@trustnetic.com> (raw)
In-Reply-To: <ZLeeZMU4HeiHthQ2@shell.armlinux.org.uk>
On Wednesday, July 19, 2023 4:27 PM, Russell King (Oracle) wrote:
> On Wed, Jul 19, 2023 at 03:57:30PM +0800, Jiawen Wu wrote:
> > > According to this read though (which is in get_mactype), the write
> > > didn't take effect.
> > >
> > > If you place a delay of 1ms after phy_clear_bits_mmd() in
> > > mv3310_power_up(), does it then work?
> >
> > Yes, I just experimented, it works well.
>
> Please send a patch adding it, with a comment along the lines of:
>
> /* Sometimes, the power down bit doesn't clear immediately, and
> * a read of this register causes the bit not to clear. Delay
> * 1ms to allow the PHY to come out of power down mode before
> * the next access.
> */
After multiple experiments, I determined that the minimum delay it required
is 55us. Does the delay need to be reduced? But I'm not sure whether it is
related to the system. I use udelay(55) in the test.
next prev parent reply other threads:[~2023-07-19 8:40 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-12 6:26 [PATCH net] net: phy: marvell10g: fix 88x3310 power up Jiawen Wu
2023-07-13 10:26 ` Simon Horman
2023-07-13 10:35 ` Russell King (Oracle)
2023-07-13 10:45 ` Simon Horman
2023-07-13 10:53 ` Russell King (Oracle)
2023-07-13 11:30 ` Jiawen Wu
2023-07-13 11:41 ` Russell King (Oracle)
2023-07-13 11:50 ` Jiawen Wu
2023-07-17 10:51 ` Jiawen Wu
2023-07-17 12:22 ` Russell King (Oracle)
2023-07-18 9:12 ` Jiawen Wu
2023-07-18 9:49 ` Russell King (Oracle)
2023-07-18 9:58 ` Jiawen Wu
2023-07-18 11:47 ` Russell King (Oracle)
2023-07-19 2:29 ` Jiawen Wu
2023-07-19 3:53 ` Jiawen Wu
2023-07-19 6:50 ` Russell King (Oracle)
2023-07-19 7:57 ` Jiawen Wu
2023-07-19 8:27 ` Russell King (Oracle)
2023-07-19 8:38 ` Jiawen Wu [this message]
2023-07-19 8:52 ` Russell King (Oracle)
2023-07-13 12:18 ` Simon Horman
2023-07-13 10:46 ` Russell King (Oracle)
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