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From: "Cheatham, Benjamin" <benjamin.cheatham@amd.com>
To: <alejandro.lucero-palau@amd.com>
Cc: Alejandro Lucero <alucerop@amd.com>, <linux-cxl@vger.kernel.org>,
	<netdev@vger.kernel.org>, <dan.j.williams@intel.com>,
	<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
	<pabeni@redhat.com>, <edumazet@google.com>,
	<dave.jiang@intel.com>
Subject: Re: [PATCH v23 08/22] cxl/hdm: Add support for getting region from committed decoder
Date: Wed, 11 Feb 2026 16:11:55 -0600	[thread overview]
Message-ID: <03ab7820-a6e0-4655-bae7-61d2d0b7dfd6@amd.com> (raw)
In-Reply-To: <20260201155438.2664640-9-alejandro.lucero-palau@amd.com>

On 2/1/2026 9:54 AM, alejandro.lucero-palau@amd.com wrote:
> From: Alejandro Lucero <alucerop@amd.com>
> 
> A Type2 device configured by the BIOS can already have its HDM
> committed. Add a cxl_get_committed_decoder() function for cheking
> so after memdev creation. A CXL region should have been created
> during memdev initialization, therefore a Type2 driver can ask for
> such a region for working with the HPA. If the HDM is not committed,
> a Type2 driver will create the region after obtaining proper HPA
> and DPA space.
> 
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> ---
>  drivers/cxl/core/hdm.c | 39 +++++++++++++++++++++++++++++++++++++++
>  include/cxl/cxl.h      |  3 +++
>  2 files changed, 42 insertions(+)
> 
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 6e516c69b2d2..a172ce4e9b19 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -686,6 +686,45 @@ int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, u64 size)
>  	return devm_add_action_or_reset(&port->dev, cxl_dpa_release, cxled);
>  }
>  
> +static int find_committed_endpoint_decoder(struct device *dev, const void *data)
> +{
> +	struct cxl_endpoint_decoder *cxled;
> +	struct cxl_port *port;
> +
> +	if (!is_endpoint_decoder(dev))
> +		return 0;
> +
> +	cxled = to_cxl_endpoint_decoder(dev);
> +	port = cxled_to_port(cxled);
> +
> +	return cxled->cxld.id == port->hdm_end;

Is this the way you're supposed to check if a decoder is committed? The doc comment for @hdm_end in
struct cxl_port says it's just the last allocated decoder. If allocated decoders are always committed then
I'm fine with this, otherwise I think you'd want to a register read or something to find the commit state.
> +}
> +
> +struct cxl_endpoint_decoder *cxl_get_committed_decoder(struct cxl_memdev *cxlmd,
> +						       struct cxl_region **cxlr)
> +{
> +	struct cxl_port *endpoint = cxlmd->endpoint;
> +	struct cxl_endpoint_decoder *cxled;
> +	struct device *cxled_dev;
> +
> +	if (!endpoint)
> +		return NULL;
> +
> +	guard(rwsem_read)(&cxl_rwsem.dpa);
> +	cxled_dev = device_find_child(&endpoint->dev, NULL,
> +				      find_committed_endpoint_decoder);
> +
> +	if (!cxled_dev)
> +		return NULL;
> +
> +	cxled = to_cxl_endpoint_decoder(cxled_dev);
> +	*cxlr = cxled->cxld.region;
> +
> +	put_device(cxled_dev);
> +	return cxled;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_get_committed_decoder, "CXL");
> +
>  static void cxld_set_interleave(struct cxl_decoder *cxld, u32 *ctrl)
>  {
>  	u16 eig;
> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> index 6f8d365067af..928276dba952 100644
> --- a/include/cxl/cxl.h
> +++ b/include/cxl/cxl.h
> @@ -249,4 +249,7 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
>  int cxl_set_capacity(struct cxl_dev_state *cxlds, u64 capacity);
>  struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds,
>  				       const struct cxl_memdev_attach *attach);
> +struct cxl_region;
> +struct cxl_endpoint_decoder *cxl_get_committed_decoder(struct cxl_memdev *cxlmd,
> +						       struct cxl_region **cxlr);
>  #endif /* __CXL_CXL_H__ */


  reply	other threads:[~2026-02-11 22:12 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-01 15:54 [PATCH v23 00/22] Type2 device basic support alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 01/22] cxl: Add type2 " alejandro.lucero-palau
2026-02-11 22:11   ` Cheatham, Benjamin
2026-02-19  8:52     ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 02/22] sfc: add cxl support alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 03/22] cxl: Move pci generic code alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 04/22] cxl/sfc: Map cxl component regs alejandro.lucero-palau
2026-03-20 17:22   ` Edward Cree
2026-02-01 15:54 ` [PATCH v23 05/22] cxl/sfc: Initialize dpa without a mailbox alejandro.lucero-palau
2026-03-20 17:24   ` Edward Cree
2026-02-01 15:54 ` [PATCH v23 06/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 07/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 08/22] cxl/hdm: Add support for getting region from committed decoder alejandro.lucero-palau
2026-02-11 22:11   ` Cheatham, Benjamin [this message]
2026-02-12  9:16     ` Alejandro Lucero Palau
2026-03-09 22:49       ` PJ Waskiewicz
2026-03-10 13:54         ` Alejandro Lucero Palau
2026-03-13  2:03         ` Dan Williams
2026-03-13 13:10           ` Alejandro Lucero Palau
2026-03-16 14:33             ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 09/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 10/22] cxl: Export function for unwinding cxl by accelerators alejandro.lucero-palau
2026-02-19 23:16   ` Dave Jiang
2026-02-21  4:48   ` Gregory Price
2026-02-01 15:54 ` [PATCH v23 11/22] sfc: obtain decoder and region if committed by firmware alejandro.lucero-palau
2026-02-11 22:10   ` Cheatham, Benjamin
2026-02-19  8:55     ` Alejandro Lucero Palau
2026-02-19 23:31   ` Dave Jiang
2026-02-20  8:08     ` Alejandro Lucero Palau
2026-03-20 17:25   ` Edward Cree
2026-02-01 15:54 ` [PATCH v23 12/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2026-02-11 22:10   ` Cheatham, Benjamin
2026-02-19  9:58     ` Alejandro Lucero Palau
2026-02-19 17:29       ` Cheatham, Benjamin
2026-02-20 15:42   ` Dave Jiang
2026-02-26 16:13   ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 13/22] sfc: get root decoder alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 14/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2026-02-11 22:10   ` Cheatham, Benjamin
2026-02-11 22:12   ` Cheatham, Benjamin
2026-02-19 10:26     ` Alejandro Lucero Palau
2026-02-13 16:14   ` [PATCH " Gregory Price
2026-02-16 12:34     ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 15/22] sfc: get endpoint decoder alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 16/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2026-02-11 22:11   ` Cheatham, Benjamin
2026-02-01 15:54 ` [PATCH v23 17/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2026-02-11 22:11   ` Cheatham, Benjamin
2026-02-19 10:40     ` Alejandro Lucero Palau
2026-02-19 17:29       ` Cheatham, Benjamin
2026-02-01 15:54 ` [PATCH v23 18/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2026-02-11 22:11   ` Cheatham, Benjamin
2026-02-01 15:54 ` [PATCH v23 19/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2026-02-11 22:11   ` Cheatham, Benjamin
2026-02-19 10:48     ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 20/22] cxl: Avoid dax creation for accelerators alejandro.lucero-palau
2026-02-11 22:10   ` Cheatham, Benjamin
2026-02-19 10:50     ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 21/22] sfc: create cxl region alejandro.lucero-palau
2026-02-13 16:14   ` [PATCH " Gregory Price
2026-02-20  8:00     ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2026-02-13 16:14   ` [PATCH " Gregory Price
2026-02-20  8:04     ` Alejandro Lucero Palau
2026-02-11 22:12 ` [PATCH v23 00/22] Type2 device basic support Cheatham, Benjamin
2026-03-09 22:43 ` PJ Waskiewicz
2026-03-10 14:02   ` Alejandro Lucero Palau

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