From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B7EE54F8A; Mon, 29 Jan 2024 09:13:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.191 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706519595; cv=none; b=IuTrb4sEhLjpVKsQX29kUy9kKVLK8i25cAx1ytEqKhi/thP7vBR+6G0nIBR15vPA2KUydqUEbkRtE2Q2Ght4ev2BkPax3KDQhZN0FlhkHTi2YV+cglYBZ7PgwsHHWt06wK3mFIr6BB+Tvjbpe2MVfdezPfSa+cAjq/LwVwHp9Aw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706519595; c=relaxed/simple; bh=fUwawlo+6mog1liGVL6Imvc8CtK/LPifYJCNZrjGVdE=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=XWYuZgm682WrXodWnoLehwPJNLuuMLr88zjdwnCqEle8eZ1i7B//p1m4K4BrJfr3JgzA7e5Mdyl4+012zNBkog1LS+UtQlkKGhuM4bVuKDNfkO0/3/sCWdgASaBtSWlW6jAJZXQyxT8Jx54YLT1+Ar2nvhe5EW5LFy0IYWAcMuk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.191 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.234]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4TNjGJ63hCz1gy0l; Mon, 29 Jan 2024 17:11:20 +0800 (CST) Received: from kwepemd100009.china.huawei.com (unknown [7.221.188.135]) by mail.maildlp.com (Postfix) with ESMTPS id 4393E14011D; Mon, 29 Jan 2024 17:13:09 +0800 (CST) Received: from [10.67.109.184] (10.67.109.184) by kwepemd100009.china.huawei.com (7.221.188.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.1258.28; Mon, 29 Jan 2024 17:13:08 +0800 Message-ID: <03ebc63f-7b96-4a70-ad10-a4ffc1d5b1cc@huawei.com> Date: Mon, 29 Jan 2024 17:13:07 +0800 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RESEND bpf-next v3 4/6] riscv, bpf: Add necessary Zbb instructions Content-Language: en-US To: =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Pu Lehui , , , CC: Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Palmer Dabbelt , Conor Dooley , Luke Nelson References: <20240115131235.2914289-1-pulehui@huaweicloud.com> <20240115131235.2914289-5-pulehui@huaweicloud.com> <871qa2zog6.fsf@all.your.base.are.belong.to.us> From: Pu Lehui In-Reply-To: <871qa2zog6.fsf@all.your.base.are.belong.to.us> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemd100009.china.huawei.com (7.221.188.135) On 2024/1/28 1:16, Björn Töpel wrote: > Pu Lehui writes: > >> From: Pu Lehui >> >> Add necessary Zbb instructions introduced by [0] to reduce code size and >> improve performance of RV64 JIT. Meanwhile, a runtime deteted helper is >> added to check whether the CPU supports Zbb instructions. >> >> Link: https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf [0] >> Signed-off-by: Pu Lehui >> --- >> arch/riscv/net/bpf_jit.h | 32 ++++++++++++++++++++++++++++++++ >> 1 file changed, 32 insertions(+) >> >> diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h >> index e30501b46f8f..51f6d214086f 100644 >> --- a/arch/riscv/net/bpf_jit.h >> +++ b/arch/riscv/net/bpf_jit.h >> @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void) >> return IS_ENABLED(CONFIG_RISCV_ISA_C); >> } >> >> +static inline bool rvzbb_enabled(void) >> +{ >> + return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); > > Hmm, I'm thinking about the IS_ENABLED(CONFIG_RISCV_ISA_ZBB) semantics > for a kernel JIT compiler. > > IS_ENABLED(CONFIG_RISCV_ISA_ZBB) affects the kernel compiler flags. > Should it be enough to just have the run-time check? Should a kernel > built w/o Zbb be able to emit Zbb from the JIT? > Not enough, because riscv_has_extension_likely(RISCV_ISA_EXT_ZBB) is a platform capability check, and the other one is a kernel image capability check. We can pass the check riscv_has_extension_likely(RISCV_ISA_EXT_ZBB) when CONFIG_RISCV_ISA_ZBB=n. And my local test prove it. > > Björn