From: "Jason-JH Lin (林睿祥)" <Jason-JH.Lin@mediatek.com>
To: Laura Nao <laura.nao@collabora.com>
Cc: "Guangjie Song (宋光杰)" <Guangjie.Song@mediatek.com>,
"robh@kernel.org" <robh@kernel.org>,
"kernel@collabora.com" <kernel@collabora.com>,
"Sirius Wang (王皓昱)" <Sirius.Wang@mediatek.com>,
"Nancy Lin (林欣螢)" <Nancy.Lin@mediatek.com>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"Paul-pl Chen (陳柏霖)" <Paul-pl.Chen@mediatek.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"richardcochran@gmail.com" <richardcochran@gmail.com>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"mturquette@baylibre.com" <mturquette@baylibre.com>,
"Nicolas Prado" <nfraprado@collabora.com>,
"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
"Singo Chang (張興國)" <Singo.Chang@mediatek.com>,
"wenst@chromium.org" <wenst@chromium.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
"sboyd@kernel.org" <sboyd@kernel.org>
Subject: Re: [PATCH v5 23/27] clk: mediatek: Add MT8196 disp-ao clock support
Date: Fri, 3 Apr 2026 08:54:39 +0000 [thread overview]
Message-ID: <04a1848e3ffb43fae727ca0110d57e81fe88a4a1.camel@mediatek.com> (raw)
In-Reply-To: <20260402100538.27291-1-laura.nao@collabora.com>
[snip]
> > > +static const struct of_device_id of_match_clk_mt8196_vdisp_ao[]
> > > = {
> > > + { .compatible = "mediatek,mt8196-vdisp-ao", .data =
> > > &mm_v_mcd },
> >
> > Hi Laura,
> >
> > We are going to send mtk-mmsys driver for MT8196 recently, but we
> > found
> > the compatible name is used here.
> >
> > As your commit message, vdisp-ao is integrated with the mtk-mmsys
> > driver, which registers the vdisp-ao clock driver via
> > platform_device_register_data().
> >
> > Shouldn't this compatible name belong to mmsys driver for MT8196?
> >
>
> That's right, my fault for missing that! Thanks for the heads up.
>
> I'm aware Angelo is currently restructuring mediatek-drm (including
> mmsys and mutex), and that might affect the way vdisp-ao is loaded
> too.
> So I'm not sure whether it makes sense to send a patch to fix this
> right away.
OK, we'll try to contact Angelo from other places.
Thanks for your confirmation!
Regards,
Jason-JH.Lin
>
> Best,
>
> Laura
>
next prev parent reply other threads:[~2026-04-03 8:54 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-29 9:18 [PATCH v5 00/27] Add support for MT8196 clock controllers Laura Nao
2025-08-29 9:18 ` [PATCH v5 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-08-29 9:18 ` [PATCH v5 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-08-29 9:18 ` [PATCH v5 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-09-05 4:09 ` Chen-Yu Tsai
2025-08-29 9:18 ` [PATCH v5 04/27] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() Laura Nao
2025-08-29 9:18 ` [PATCH v5 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC Laura Nao
2025-09-05 4:11 ` Chen-Yu Tsai
2025-08-29 9:18 ` [PATCH v5 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-09-05 4:13 ` Chen-Yu Tsai
2025-09-05 8:20 ` AngeloGioacchino Del Regno
2025-08-29 9:18 ` [PATCH v5 07/27] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-09-05 4:25 ` Chen-Yu Tsai
2025-08-29 9:18 ` [PATCH v5 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-08-29 9:18 ` [PATCH v5 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers Laura Nao
2025-08-29 9:18 ` [PATCH v5 10/27] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-08-29 9:18 ` [PATCH v5 11/27] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-08-29 9:18 ` [PATCH v5 12/27] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-08-29 9:18 ` [PATCH v5 13/27] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-09-05 5:01 ` Chen-Yu Tsai
2025-09-05 8:20 ` AngeloGioacchino Del Regno
2025-08-29 9:19 ` [PATCH v5 14/27] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-09-05 5:05 ` Chen-Yu Tsai
2025-09-05 8:11 ` AngeloGioacchino Del Regno
2025-08-29 9:19 ` [PATCH v5 15/27] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-09-05 6:36 ` Chen-Yu Tsai
2025-09-05 8:40 ` AngeloGioacchino Del Regno
2025-08-29 9:19 ` [PATCH v5 16/27] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-09-05 7:24 ` Chen-Yu Tsai
2025-08-29 9:19 ` [PATCH v5 17/27] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-08-29 9:19 ` [PATCH v5 18/27] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-08-29 9:19 ` [PATCH v5 19/27] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-09-05 8:04 ` Chen-Yu Tsai
2025-09-05 8:39 ` AngeloGioacchino Del Regno
2025-09-05 8:53 ` Chen-Yu Tsai
2025-09-15 10:33 ` AngeloGioacchino Del Regno
2025-08-29 9:19 ` [PATCH v5 20/27] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-08-29 9:19 ` [PATCH v5 21/27] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-08-29 9:19 ` [PATCH v5 22/27] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-09-05 8:03 ` Chen-Yu Tsai
2025-09-05 8:40 ` AngeloGioacchino Del Regno
2025-08-29 9:19 ` [PATCH v5 23/27] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2026-04-02 6:30 ` Jason-JH Lin (林睿祥)
2026-04-02 10:05 ` Laura Nao
2026-04-03 8:54 ` Jason-JH Lin (林睿祥) [this message]
[not found] ` <CAHCN7x+K25H-QWLDA6SoGSzxv9koO0wFOrjfWNePc+0AfjCVZg@mail.gmail.com>
2026-04-09 6:30 ` Jason-JH Lin (林睿祥)
2025-08-29 9:19 ` [PATCH v5 24/27] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-08-29 9:19 ` [PATCH v5 25/27] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-08-29 9:19 ` [PATCH v5 26/27] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-08-29 9:19 ` [PATCH v5 27/27] clk: mediatek: Add MT8196 vencsys " Laura Nao
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=04a1848e3ffb43fae727ca0110d57e81fe88a4a1.camel@mediatek.com \
--to=jason-jh.lin@mediatek.com \
--cc=Guangjie.Song@mediatek.com \
--cc=Nancy.Lin@mediatek.com \
--cc=Paul-pl.Chen@mediatek.com \
--cc=Project_Global_Chrome_Upstream_Group@mediatek.com \
--cc=Singo.Chang@mediatek.com \
--cc=Sirius.Wang@mediatek.com \
--cc=angelogioacchino.delregno@collabora.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=kernel@collabora.com \
--cc=krzk+dt@kernel.org \
--cc=laura.nao@collabora.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=mturquette@baylibre.com \
--cc=netdev@vger.kernel.org \
--cc=nfraprado@collabora.com \
--cc=p.zabel@pengutronix.de \
--cc=richardcochran@gmail.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=wenst@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox