RE: [PATCH net-next 4/7] net: pcs: xpcs: adapt Wangxun NICs for SGMII mode

["Jiawen Wu" <jiawenwu@trustnetic.com>]

On Thursday, August 3, 2023 7:11 PM, Russell King (Oracle) wrote:
> On Thu, Aug 03, 2023 at 10:20:22AM +0800, Jiawen Wu wrote:
> > > No there isn't, and it conforms with the above.
> > >
> > > A read looks like this:
> > >
> > >       Address  Data                   Address  Data     Data
> > > Start 10101100 000yyyyy RepeatedStart 10101101 DDDDDDDD DDDDDDDD Stop
> > >                       or Stop followed
> > > 		          by Start
> > >
> > > The terms "Address" and "Data" here are as per the I²C specification.
> > > You will notice that the first part has one byte of address and *one*
> > > byte of data to convey the register address. This is what the "1" you
> > > are referring to above is for.
> > >
> > > For completness, a write looks like this:
> > >
> > >       Address  Data     Data     Data
> > > Start 10101100 000yyyyy DDDDDDDD DDDDDDDD Stop
> > >
> > > Essentially, in all cases, when 0x56 is addressed with the data
> > > direction in write mode, the very first byte is _always_ the register
> > > address and the remainder contain the data. When the data direction is
> > > in read mode, the bytes are always data.
> > >
> > > The description you quote above is poor because it doesn't make it
> > > clear whether "read" and "write" apply to the bus transactions or to
> > > the device operations. However, I can assure you that what is
> > > implemented is correct, since this is the standard small 24xx memory
> > > device protocol, and I've been programming that on various
> > > microcontrollers and such like for the last 30 years.
> > >
> > > Are you seeing a problem with the data read or written to the PHY?
> >
> > Hi Russell,
> >
> > I really don't know how to deal with "MAC side SGMII", could you please
> > help me?
> >
> > From the test results, when I config PCS in "PHY side SGMII", the link status
> > of PHY in copper SFP is read by I2C after AN complete. Then PHY's link up
> > status is informed to PHYLINK, then PCS will check its status. But when I just
> > change PCS to "MAC side SGMII", I2C will keep reading timeouts since AN
> > complete. I checked the register of PCS to confirm AN complete, but PHY's
> > link status would never be updated in PHYLINK.
> 
> I don't understand what is going on here either - but what I do know
> is that there is _zero_ difference as far as the network link is
> concerned between an on-board PHY using SGMII to the MAC/PCS and a SFP
> with a PHY using SGMII.
> 
> In both situations the PHY behaves the same - it presents a PHY-side
> SGMII interface, so it sends to the MAC/PCS the speed and duplex
> settings, and expects the MAC/PCS to acknowledge them.
> 
> The name "MAC side SGMII" suggests that this mode provides the
> acknowledgement, whereas "PHY side SGMII" suggests that this mode
> provides a speed and duplex.
> 
> Given all this, using "PHY side SGMII" with a SFP, and "MAC side
> SGMII" for an on-board PHY just seems utterly wrong - and I can't
> make head nor tail of it.

Since no reasonable explanation can be given, can we assume that there is a
design flaw in the hardware? Although it's not clear to the designers...

> 
> > It's kind of weird to me, how does the configuration of PCS relate to I2C?
> 
> I2C is just the access method for PHYs on SFPs - because there are
> no MDIO bus pins on SFP modules, only I2C pins mainly for accessing
> the identification EEPROM and diagnostics, but many copper SFPs have
> a way to access the PHY.
> 
> I2C is transparent as far as phylib is concerned - the mdio-i2c
> driver makes the PHY "appear" as if it is on a conventional MDIO
> bus.