From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 054FB27F18F; Wed, 25 Jun 2025 08:57:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750841857; cv=none; b=NSISRoSCIyJnRbzweNLYo42u7a7ikuR/E5R33E5yfOfuxVyce5lOzr+kSIxVgKVacOdrI/TLkzejXjAkZGlX/cTAE09ckBcmcDlMb1uJTjLkHH8up/aTIAjDy/IHcjwegL4i6ey9ft8VcIyMJ2T9H8Od3XyforNSmBzqOuxzipE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750841857; c=relaxed/simple; bh=0QgB6O4O/sYU4iRucJ8iotwxezNS2MkmRTc3/U3q/9w=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=B+QuOWC26dQGwzDxme+03uaQwponS8676OQvErxW+umPdG6gKTN5lTFq+t/63qus3MkDYjAHUizopf4t/uPmVYvX36Nt9x7ktQPDHWDFsrnnBj3QNLv+0b7WQEVsAFuurIbW3mF0jMkCYnfTuG/TOpLMNNn+cZXt7bU5I3wogDI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DW1bIPn8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DW1bIPn8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5C0FFC4CEEA; Wed, 25 Jun 2025 08:57:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750841856; bh=0QgB6O4O/sYU4iRucJ8iotwxezNS2MkmRTc3/U3q/9w=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=DW1bIPn8+wO1CO4ERNB9TZT6bfg+jmleh0swnm693vd3NvFbpG/OZSMRc56gGicV5 ZtF7p9vu8eh+rQYXLenH3rs2RhhmlE9o0vVCOz+uayDuNHhm5pY7OMLtBen1qooAdO swoHx7Fsv/3l93q4QM3UpIHr5oMR8YjS2SZiaOWfWBz+5DGG14NuG0sKv85YiG7/ij vGVG+davd9Q+wMxOEA5GnRmH3+7VbFNZxjoH7cJD02Och3vEOKe9Mb26Kz9twdi5FF SbbQBlLN9MJ8GnBrTroEgtrrLQsM8HbBaIDLDQM3JE8sWH4tYrjmraF36T9AnpVF+L bps/xM9fsAw2w== Message-ID: <0870a2ba-936b-4eb2-a570-f2c9dea471b8@kernel.org> Date: Wed, 25 Jun 2025 10:57:30 +0200 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 09/29] dt-bindings: clock: mediatek: Describe MT8196 peripheral clock controllers To: AngeloGioacchino Del Regno , Laura Nao , mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com References: <20250624143220.244549-1-laura.nao@collabora.com> <20250624143220.244549-10-laura.nao@collabora.com> <7dfba01a-6ede-44c2-87e3-3ecb439b48e3@kernel.org> <284a4ee5-806b-45f9-8d57-d02ec291e389@collabora.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 25/06/2025 10:20, AngeloGioacchino Del Regno wrote: > Il 24/06/25 18:02, Krzysztof Kozlowski ha scritto: >> On 24/06/2025 16:32, Laura Nao wrote: >>> + '#reset-cells': >>> + const: 1 >>> + description: >>> + Reset lines for PEXTP0/1 and UFS blocks. >>> + >>> + mediatek,hardware-voter: >>> + $ref: /schemas/types.yaml#/definitions/phandle >>> + description: >>> + On the MT8196 SoC, a Hardware Voter (HWV) backed by a fixed-function >>> + MCU manages clock and power domain control across the AP and other >>> + remote processors. By aggregating their votes, it ensures clocks are >>> + safely enabled/disabled and power domains are active before register >>> + access. >> >> Resource voting is not via any phandle, but either interconnects or >> required opps for power domain. > > Sorry, I'm not sure who is actually misunderstanding what, here... let me try to > explain the situation: > > This is effectively used as a syscon - as in, the clock controllers need to perform > MMIO R/W on both the clock controller itself *and* has to place a vote to the clock > controller specific HWV register. syscon is not the interface to place a vote for clocks. "clocks" property is. > > This is done for MUX-GATE and GATE clocks, other than for power domains. > > Note that the HWV system is inside of the power domains controller, and it's split > on a per hardware macro-block basis (as per usual MediaTek hardware layout...). > > The HWV, therefore, does *not* vote for clock *rates* (so, modeling OPPs would be > a software quirk, I think?), does *not* manage bandwidth (and interconnect is for > voting BW only?), and is just a "switch to flip". That's still clocks. Gate is a clock. > > Is this happening because the description has to be improved and creating some > misunderstanding, or is it because we are underestimating and/or ignoring something > here? > Other vendors, at least qcom, represent it properly - clocks. Sometimes they mix up and represent it as power domains, but that's because downstream is a mess and because we actually (at upstream) don't really know what is inside there - is it a clock or power domain. Best regards, Krzysztof