From: "Tauro, Riana" <riana.tauro@intel.com>
To: Raag Jadav <raag.jadav@intel.com>,
<intel-xe@lists.freedesktop.org>,
<dri-devel@lists.freedesktop.org>, <netdev@vger.kernel.org>
Cc: <simona.vetter@ffwll.ch>, <airlied@gmail.com>, <kuba@kernel.org>,
<lijo.lazar@amd.com>, <Hawking.Zhang@amd.com>,
<davem@davemloft.net>, <pabeni@redhat.com>, <edumazet@google.com>,
<dev@lankhorst.se>, <zachary.mckevitt@oss.qualcomm.com>,
<rodrigo.vivi@intel.com>, <michal.wajdeczko@intel.com>,
<matthew.d.roper@intel.com>, <mallesh.koujalagi@intel.com>
Subject: Re: [PATCH v4 3/5] drm/xe/ras: Add support for error threshold
Date: Fri, 3 Jul 2026 13:00:16 +0530 [thread overview]
Message-ID: <09869e95-4526-428d-808e-74c6b1ebc207@intel.com> (raw)
In-Reply-To: <20260623101043.255897-4-raag.jadav@intel.com>
On 23-06-2026 15:39, Raag Jadav wrote:
> System controller allows getting/setting per counter threshold for
> correctable errors, which it uses to raise error events to the driver.
> Get/set it using the respective mailbox command.
>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
> ---
> v2: Add RAS operation status codes (Riana)
> v3: Reuse status codes and uapi mapping from counter series (Riana)
> Access request/response counter using local pointer (Riana)
> Mark unused field as reserved (Riana)
> v4: Make debug logs consistent (Riana)
> Update kdoc (Riana)
> ---
> drivers/gpu/drm/xe/xe_ras.c | 105 ++++++++++++++++++
> drivers/gpu/drm/xe/xe_ras.h | 2 +
> drivers/gpu/drm/xe/xe_ras_types.h | 51 +++++++++
> drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 4 +
> 4 files changed, 162 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 44f4e1a3455b..afee8202d24e 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -270,6 +270,111 @@ int xe_ras_clear_counter(struct xe_device *xe, u8 severity, u8 component)
> return 0;
> }
>
> +/**
> + * xe_ras_get_threshold() - Get error counter threshold
> + * @xe: Xe device instance
> + * @severity: Error severity to be queried (&enum drm_xe_ras_error_severity)
> + * @component: Error component to be queried (&enum drm_xe_ras_error_component)
> + * @threshold: Counter threshold
> + *
> + * This function retrieves the error threshold of a specific counter based on
> + * severity and component.
> + *
> + * Return: 0 on success, negative error code on failure.
> + */
> +int xe_ras_get_threshold(struct xe_device *xe, u8 severity, u8 component, u32 *threshold)
> +{
> + struct xe_ras_get_threshold_response response = {};
> + struct xe_ras_get_threshold_request request = {};
> + struct xe_sysctrl_mailbox_command command = {};
> + struct xe_ras_error_class *counter;
> + size_t len;
> + int ret;
> +
> + counter = &request.counter;
> + counter->common.severity = drm_to_xe_ras_severity(severity);
> + counter->common.component = drm_to_xe_ras_component(component);
> +
> + xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP, XE_SYSCTRL_CMD_GET_THRESHOLD,
> + &request, sizeof(request), &response, sizeof(response));
> +
> + guard(xe_pm_runtime)(xe);
> + ret = xe_sysctrl_send_command(&xe->sc, &command, &len);
> + if (ret) {
> + xe_err(xe, "sysctrl: failed to get threshold %d\n", ret);
> + return ret;
> + }
> +
> + if (len != sizeof(response)) {
> + xe_err(xe, "sysctrl: unexpected get threshold response length %zu (expected %zu)\n",
> + len, sizeof(response));
> + return -EIO;
> + }
> +
> + counter = &response.counter;
> + *threshold = response.threshold;
> +
> + xe_dbg(xe, "[RAS]: get threshold %u for %s %s\n", *threshold,
> + comp_to_str(counter->common.component), sev_to_str(counter->common.severity));
> + return 0;
> +}
> +
> +/**
> + * xe_ras_set_threshold() - Set error counter threshold
> + * @xe: Xe device instance
> + * @severity: Error severity to be set (&enum drm_xe_ras_error_severity)
> + * @component: Error component to be set (&enum drm_xe_ras_error_component)
> + * @threshold: Counter threshold
> + *
> + * This function sets the error threshold of a specific counter based on
> + * severity and component.
> + *
> + * Return: 0 on success, negative error code on failure.
> + */
> +int xe_ras_set_threshold(struct xe_device *xe, u8 severity, u8 component, u32 threshold)
> +{
> + struct xe_ras_set_threshold_response response = {};
> + struct xe_ras_set_threshold_request request = {};
> + struct xe_sysctrl_mailbox_command command = {};
> + struct xe_ras_error_class *counter;
> + size_t len;
> + int ret;
> +
> + counter = &request.counter;
> + counter->common.severity = drm_to_xe_ras_severity(severity);
> + counter->common.component = drm_to_xe_ras_component(component);
> + request.threshold = threshold;
> +
> + xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP, XE_SYSCTRL_CMD_SET_THRESHOLD,
> + &request, sizeof(request), &response, sizeof(response));
> +
> + guard(xe_pm_runtime)(xe);
> + ret = xe_sysctrl_send_command(&xe->sc, &command, &len);
> + if (ret) {
> + xe_err(xe, "sysctrl: failed to set threshold %d\n", ret);
> + return ret;
> + }
> +
> + if (len != sizeof(response)) {
> + xe_err(xe, "sysctrl: unexpected set threshold response length %zu (expected %zu)\n",
> + len, sizeof(response));
> + return -EIO;
> + }
> +
> + ret = ras_status_to_errno(response.status);
> + if (ret) {
> + xe_err(xe, "sysctrl: set threshold command failed with status %#x\n",
> + response.status);
> + return ret;
> + }
> +
> + counter = &response.counter;
> +
> + xe_dbg(xe, "[RAS]: set threshold %u for %s %s\n", response.threshold,
> + comp_to_str(counter->common.component), sev_to_str(counter->common.severity));
> + return 0;
> +}
> +
> /**
> * xe_ras_init - Initialize Xe RAS
> * @xe: xe device instance
> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> index ba0b0224df23..1aa43c54b710 100644
> --- a/drivers/gpu/drm/xe/xe_ras.h
> +++ b/drivers/gpu/drm/xe/xe_ras.h
> @@ -15,6 +15,8 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
> struct xe_sysctrl_event_response *response);
> int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *value);
> int xe_ras_clear_counter(struct xe_device *xe, u8 severity, u8 component);
> +int xe_ras_get_threshold(struct xe_device *xe, u8 severity, u8 component, u32 *threshold);
> +int xe_ras_set_threshold(struct xe_device *xe, u8 severity, u8 component, u32 threshold);
> void xe_ras_init(struct xe_device *xe);
>
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> index 6688e11f57a8..747b651880cd 100644
> --- a/drivers/gpu/drm/xe/xe_ras_types.h
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -121,4 +121,55 @@ struct xe_ras_clear_counter_response {
> /** @reserved1: Reserved for future use */
> u32 reserved1[3];
> } __packed;
> +
> +/**
> + * struct xe_ras_get_threshold_request - Request structure for get threshold
> + */
> +struct xe_ras_get_threshold_request {
> + /** @counter: Counter to get threshold for */
> + struct xe_ras_error_class counter;
> + /** @reserved: Reserved for future use */
> + u32 reserved;
> +} __packed;
> +
> +/**
> + * struct xe_ras_get_threshold_response - Response structure for get threshold
> + */
> +struct xe_ras_get_threshold_response {
> + /** @counter: Counter ID */
> + struct xe_ras_error_class counter;
> + /** @threshold: Current threshold of the counter */
> + u32 threshold;
> + /** @reserved: Reserved for future use */
> + u32 reserved[4];
> +} __packed;
> +
> +/**
> + * struct xe_ras_set_threshold_request - Request structure for set threshold
> + */
> +struct xe_ras_set_threshold_request {
> + /** @counter: Counter to set threshold for */
> + struct xe_ras_error_class counter;
> + /** @threshold: Threshold to be set */
> + u32 threshold;
> + /** @reserved: Reserved for future use */
> + u32 reserved;
> +} __packed;
> +
> +/**
> + * struct xe_ras_set_threshold_response - Response structure for set threshold
> + */
> +struct xe_ras_set_threshold_response {
> + /** @counter: Counter ID */
> + struct xe_ras_error_class counter;
> + /** @reserved: Reserved */
> + u32 reserved;
> + /** @threshold: Updated threshold */
> + u32 threshold;
> + /** @status: Operation status */
> + u32 status;
> + /** @reserved1: Reserved for future use */
> + u32 reserved1[2];
> +} __packed;
> +
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> index 6e3753554510..10f06aa5c4b5 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> @@ -24,11 +24,15 @@ enum xe_sysctrl_group {
> *
> * @XE_SYSCTRL_CMD_GET_COUNTER: Get error counter value
> * @XE_SYSCTRL_CMD_CLEAR_COUNTER: Clear error counter value
> + * @XE_SYSCTRL_CMD_GET_THRESHOLD: Retrieve error threshold
> + * @XE_SYSCTRL_CMD_SET_THRESHOLD: Set error threshold
> * @XE_SYSCTRL_CMD_GET_PENDING_EVENT: Retrieve pending event
> */
> enum xe_sysctrl_gfsp_cmd {
> XE_SYSCTRL_CMD_GET_COUNTER = 0x03,
> XE_SYSCTRL_CMD_CLEAR_COUNTER = 0x04,
> + XE_SYSCTRL_CMD_GET_THRESHOLD = 0x05,
> + XE_SYSCTRL_CMD_SET_THRESHOLD = 0x06,
> XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
> };
>
next prev parent reply other threads:[~2026-07-03 7:30 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-23 10:09 [PATCH v4 0/5] Introduce error threshold to drm_ras Raag Jadav
2026-06-23 10:09 ` [PATCH v4 1/5] drm/ras: Cancel and free message on get counter failure Raag Jadav
2026-06-23 10:09 ` [PATCH v4 2/5] drm/ras: Introduce error threshold Raag Jadav
2026-07-03 5:13 ` Tauro, Riana
2026-06-23 10:09 ` [PATCH v4 3/5] drm/xe/ras: Add support for " Raag Jadav
2026-07-03 7:30 ` Tauro, Riana [this message]
2026-06-23 10:09 ` [PATCH v4 4/5] drm/xe/drm_ras: Wire up error threshold callbacks Raag Jadav
2026-06-23 10:09 ` [PATCH v4 5/5] drm/xe/sysctrl: Reuse xe_sysctrl_create_command() Raag Jadav
2026-07-01 9:50 ` Tauro, Riana
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