From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: akepner@sgi.com
Cc: "David S. Miller" <davem@davemloft.net>,
Jesse Barnes <jbarnes@engr.sgi.com>,
Andrew Morton <akpm@osdl.org>,
Linux Kernel list <linux-kernel@vger.kernel.org>,
netdev@oss.sgi.com, Jeff Garzik <jgarzik@pobox.com>,
gnb@sgi.com
Subject: Re: [PATCH] use mmiowb in tg3.c
Date: Fri, 22 Oct 2004 12:07:24 +1000 [thread overview]
Message-ID: <1098410843.6028.45.camel@gaston> (raw)
In-Reply-To: <Pine.LNX.4.33.0410211826480.392-100000@localhost.localdomain>
On Fri, 2004-10-22 at 11:33, akepner@sgi.com wrote:
> On Fri, 22 Oct 2004, Benjamin Herrenschmidt wrote:
>
> > ...
> > Typically, our normal "light" write barrier doesn't reorder between cacheable
> > and non-cacheable (MMIO) stores, which is why we had to put some heavy sync
> > barrier in our MMIO writes macros.
> > ...
>
> Do you mean "impose order" rather than "reorder" here?
Right.
Ben.
next prev parent reply other threads:[~2004-10-22 2:07 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <200410211613.19601.jbarnes@engr.sgi.com>
2004-10-21 23:28 ` [PATCH] use mmiowb in tg3.c Jesse Barnes
2004-10-21 23:40 ` David S. Miller
2004-10-22 1:16 ` Benjamin Herrenschmidt
2004-10-22 1:33 ` akepner
2004-10-22 2:07 ` Benjamin Herrenschmidt [this message]
2004-10-22 3:01 ` Jesse Barnes
2004-10-22 4:00 ` Paul Mackerras
2004-10-22 20:51 ` [PATCH] use mmiowb in tg3_poll akepner
2005-05-28 23:12 ` Lennert Buytenhek
2005-05-30 16:30 ` Arthur Kepner
2005-05-31 12:53 ` jamal
2005-05-31 16:45 ` Jesse Barnes
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