[PATCH 3/6] bnx2: Fix excessive udelay

["Michael Chan" <mchan@broadcom.com>]

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Replaced one excessive udelay of 15msec with msleep since the calling
context is always process. Also replaced some schedule_timeout calls
with msleep/msleep_interruptible.

Spotted by Jeff Garzik.

Signed-off-by: Michael Chan <mchan@broadcom.com>

[-- Attachment #2: bnx2-13.patch --]
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diff -Nru 12/drivers/net/bnx2.c 13/drivers/net/bnx2.c
--- 12/drivers/net/bnx2.c	2005-05-23 10:29:02.000000000 -0700
+++ 13/drivers/net/bnx2.c	2005-05-23 10:57:41.000000000 -0700
@@ -2011,11 +2011,9 @@
 			(pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
 			PCI_PM_CTRL_PME_STATUS);
 
-		if (pmcsr & PCI_PM_CTRL_STATE_MASK) {
+		if (pmcsr & PCI_PM_CTRL_STATE_MASK)
 			/* delay required during transition out of D3hot */
-			current->state = TASK_UNINTERRUPTIBLE;
-			schedule_timeout(HZ / 50);
-		}
+			msleep(20);
 
 		val = REG_RD(bp, BNX2_EMAC_MODE);
 		val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
@@ -2751,12 +2749,8 @@
 	REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
 
 	if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
-	    (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
-
-	        for (i = 0; i < 500; i++) {
-			udelay(30);
-		}
-	}
+	    (CHIP_ID(bp) == CHIP_ID_5706_A1))
+		msleep(15);
 
 	/* Reset takes approximate 30 usec */
 	for (i = 0; i < 10; i++) {
@@ -3785,8 +3779,6 @@
 	REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
 	REG_RD(bp, BNX2_HC_COMMAND);
 
-	udelay(80);
-
 	for (i = 0; i < 10; i++) {
 		if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
 			status_idx) {
@@ -3794,8 +3786,7 @@
 			break;
 		}
 
-		current->state = TASK_INTERRUPTIBLE;
-		schedule_timeout(1);
+		msleep_interruptible(10);
 	}
 	if (i < 10)
 		return 0;
@@ -4478,8 +4469,7 @@
 		bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
 		spin_unlock_irq(&bp->phy_lock);
 
-		current->state = TASK_UNINTERRUPTIBLE;
-		schedule_timeout(HZ / 50);
+		msleep(20);
 
 		spin_lock_irq(&bp->phy_lock);
 		if (CHIP_NUM(bp) == CHIP_NUM_5706) {
@@ -4869,12 +4859,9 @@
 		}
 
 		/* wait for link up */
-		current->state = TASK_INTERRUPTIBLE;
-		schedule_timeout(3 * HZ);
-		if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG)) {
-			current->state = TASK_INTERRUPTIBLE;
-			schedule_timeout(4 * HZ);
-		}
+		msleep_interruptible(3000);
+		if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
+			msleep_interruptible(4000);
 	}
 
 	if (bnx2_test_nvram(bp) != 0) {
@@ -4975,8 +4962,7 @@
 				BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
 				BNX2_EMAC_LED_TRAFFIC);
 		}
-		current->state = TASK_INTERRUPTIBLE;
-		schedule_timeout(HZ / 2);
+		msleep_interruptible(500);
 		if (signal_pending(current))
 			break;
 	}