From: "Michael Chan" <mchan@broadcom.com>
To: "Francois Romieu" <romieu@fr.zoreil.com>
Cc: "Ayaz Abdulla" <AAbdulla@nvidia.com>,
"Stephen Hemminger" <shemminger@osdl.org>,
"Jeff Garzik" <jgarzik@pobox.com>,
"Manfred Spraul" <manfred@colorfullife.com>,
"Netdev" <netdev@oss.sgi.com>
Subject: Re: [PATCH 2/2] forcedeth: scatter gather and segmentation offload support
Date: Tue, 25 Oct 2005 15:05:19 -0700 [thread overview]
Message-ID: <1130277919.6236.7.camel@rh4> (raw)
In-Reply-To: <20051025232248.GB17794@electric-eye.fr.zoreil.com>
On Wed, 2005-10-26 at 01:22 +0200, Francois Romieu wrote:
> Michael Chan <mchan@broadcom.com> :
> > Please explain what did you mean by bogus?
>
> When the CPU sets the entries of a multi-descriptor packet, the first
> descriptor is marked read while the next ones are still unset.
>
Not sure you you meant by "marked read", but none of the new tx
descriptors will be DMA'ed by the chip until we write the producer index
and the byte seq. number.
> If any of BNX2_L2CTX_TX_HOST_{BIDX/BSEQ} prevents the asic to read
> beyond 'prod' (or b(yte)seq ?), the ordering does not matter. Right ?
>
Right, the chip will only DMA the tx descriptors up to the (prod - 1)
index. tg3 works in a similar way.
next prev parent reply other threads:[~2005-10-25 22:05 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-10-25 21:15 [PATCH 2/2] forcedeth: scatter gather and segmentation offload support Ayaz Abdulla
2005-10-25 21:59 ` Francois Romieu
2005-10-25 20:30 ` Michael Chan
2005-10-25 23:22 ` Francois Romieu
2005-10-25 22:05 ` Michael Chan [this message]
-- strict thread matches above, loose matches on Subject: below --
2005-10-26 6:17 Ayaz Abdulla
2005-09-18 14:01 Manfred Spraul
2005-10-21 21:23 ` Jeff Garzik
2005-10-24 16:48 ` Ayaz Abdulla
2005-10-24 18:00 ` Stephen Hemminger
2005-10-24 17:05 ` Ayaz Abdulla
2005-10-26 4:53 ` Jeff Garzik
2005-10-24 21:21 ` Stephen Hemminger
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