Re: tw32_f() in tg3_write_mem()

Re: tw32_f() in tg3_write_mem()

[Michael Chan]

David S. Miller wrote:

> At least for the TG3PCI_MEM_WIN_DATA register, I don't know how safe
> it is to use tw32_f() there.  Reads from a location can have side
> effects, so doing a forced readback after a write could be dangerous.
> 
> And it isn't needed, as the tw32_f() done as we set the
> TG3PCI_MEM_WIN_BASE_ADDR back to zero will flush all posted
> writes.
> 
> Agreed?
> 
> 

The TG3PCI_MEM_WIN_BASE_ADDR and DATA registers are very tricky. If you
do not read back the address register before you read or write the data
register, you may not read or write to the proper address.

Reading back the data register is a safe thing to do. This guarantees
that
the data is written before we change the address register to the zero
value. Without the read, there is a danger of the value being written to
SRAM address 0 instead of the desired address.

No additional reads are required if we use config. cycles on these
registers.

Re: tw32_f() in tg3_write_mem()

[David S. Miller]

From: "Michael Chan" <mchan@broadcom.com>
Date: Sun, 30 Apr 2006 22:05:40 -0700

> Reading back the data register is a safe thing to do. This
> guarantees that the data is written before we change the address
> register to the zero value. Without the read, there is a danger of
> the value being written to SRAM address 0 instead of the desired
> address.

Writes can be posted, but they cannot be reordered can they?

Re: tw32_f() in tg3_write_mem()

[Michael Chan]

On Sun, 2006-04-30 at 23:07 -0700, David S. Miller wrote:
> From: "Michael Chan" <mchan@broadcom.com>
> Date: Sun, 30 Apr 2006 22:05:40 -0700
> 
> > Reading back the data register is a safe thing to do. This
> > guarantees that the data is written before we change the address
> > register to the zero value. Without the read, there is a danger of
> > the value being written to SRAM address 0 instead of the desired
> > address.
> 
> Writes can be posted, but they cannot be reordered can they?
> 

Right, reordering is not allowed unless the relaxed ordering attribute
is set. The read back here is not to guarantee ordering. Those SRAM
address and data registers require "set-up" times for the SRAM writes
and reads to work correctly. The "set-up" times are met either with
config. cycles or with a read when using MMIO cycles. No udelays are
needed, just a read will do.

tw32_f() in tg3_write_mem()

[David S. Miller]

At least for the TG3PCI_MEM_WIN_DATA register, I don't know how safe
it is to use tw32_f() there.  Reads from a location can have side
effects, so doing a forced readback after a write could be dangerous.

And it isn't needed, as the tw32_f() done as we set the
TG3PCI_MEM_WIN_BASE_ADDR back to zero will flush all posted
writes.

Agreed?