From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Arjan van de Ven" <arjan@infradead.org>
Subject: Re: [PATCH v3 1/7] AMSO1100 Low Level Driver.
Date: Fri, 23 Jun 2006 15:48:52 +0200
Message-ID: <1151070532.3204.10.camel@laptopd505.fenrus.org>
References: <20060620203050.31536.5341.stgit@stevo-desktop>
 <20060620203055.31536.15131.stgit@stevo-desktop>
 <1150836226.2891.231.camel@laptopd505.fenrus.org>
 <1151070290.7808.33.camel@stevo-desktop>
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Cc: rdreier@cisco.com,
	linux-kernel@vger.kernel.org,
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To: "Steve Wise" <swise@opengridcomputing.com>
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> > > +	/* Tell HW to xmit */
> > > +	__raw_writeq(cpu_to_be64(mapaddr), elem->hw_desc + C2_TXP_ADDR);
> > > +	__raw_writew(cpu_to_be16(maplen), elem->hw_desc + C2_TXP_LEN);
> > > +	__raw_writew(cpu_to_be16(TXP_HTXD_READY), elem->hw_desc + C2_TXP_FLAGS);
> > 
> > or here
> > 
> 
> No need here.  This logic submits the packet for transmission.  We don't
> assume it is transmitted until we (after a completion interrupt usually)
> read back the HTXD entry and see the TXP_HTXD_DONE bit set (see
> c2_tx_interrupt()). 

... but will that interrupt happen at all if these 3 writes never hit
the hardware?