From: "Michael Chan" <mchan@broadcom.com>
To: netdev@vger.kernel.org
Subject: [PATCH 3/17][BNX2]: Add bnx2_5706_serdes_timer().
Date: Thu, 16 Nov 2006 19:20:28 -0800 [thread overview]
Message-ID: <1163733628.6658.52.camel@rh4> (raw)
In-Reply-To: <1163731443.6658.8.camel@rh4>
[BNX2]: Add bnx2_5706_serdes_timer().
Separate the 5706S SerDes handling code in bnx2_timer() and put it
in a new function.
Signed-off-by: Michael Chan <mchan@broadcom.com>
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 9b391cf..7897481 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -4173,81 +4173,80 @@ bnx2_test_intr(struct bnx2 *bp)
}
static void
-bnx2_timer(unsigned long data)
+bnx2_5706_serdes_timer(struct bnx2 *bp)
{
- struct bnx2 *bp = (struct bnx2 *) data;
- u32 msg;
+ spin_lock(&bp->phy_lock);
+ if (bp->serdes_an_pending)
+ bp->serdes_an_pending--;
+ else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
+ u32 bmcr;
- if (!netif_running(bp->dev))
- return;
+ bp->current_interval = bp->timer_interval;
- if (atomic_read(&bp->intr_sem) != 0)
- goto bnx2_restart_timer;
+ bnx2_read_phy(bp, MII_BMCR, &bmcr);
- msg = (u32) ++bp->fw_drv_pulse_wr_seq;
- REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
+ if (bmcr & BMCR_ANENABLE) {
+ u32 phy1, phy2;
- bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
+ bnx2_write_phy(bp, 0x1c, 0x7c00);
+ bnx2_read_phy(bp, 0x1c, &phy1);
- if ((bp->phy_flags & PHY_SERDES_FLAG) &&
- (CHIP_NUM(bp) == CHIP_NUM_5706)) {
+ bnx2_write_phy(bp, 0x17, 0x0f01);
+ bnx2_read_phy(bp, 0x15, &phy2);
+ bnx2_write_phy(bp, 0x17, 0x0f01);
+ bnx2_read_phy(bp, 0x15, &phy2);
- spin_lock(&bp->phy_lock);
- if (bp->serdes_an_pending) {
- bp->serdes_an_pending--;
+ if ((phy1 & 0x10) && /* SIGNAL DETECT */
+ !(phy2 & 0x20)) { /* no CONFIG */
+
+ bmcr &= ~BMCR_ANENABLE;
+ bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
+ bnx2_write_phy(bp, MII_BMCR, bmcr);
+ bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG;
+ }
}
- else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
- u32 bmcr;
+ }
+ else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
+ (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
+ u32 phy2;
- bp->current_interval = bp->timer_interval;
+ bnx2_write_phy(bp, 0x17, 0x0f01);
+ bnx2_read_phy(bp, 0x15, &phy2);
+ if (phy2 & 0x20) {
+ u32 bmcr;
bnx2_read_phy(bp, MII_BMCR, &bmcr);
+ bmcr |= BMCR_ANENABLE;
+ bnx2_write_phy(bp, MII_BMCR, bmcr);
- if (bmcr & BMCR_ANENABLE) {
- u32 phy1, phy2;
-
- bnx2_write_phy(bp, 0x1c, 0x7c00);
- bnx2_read_phy(bp, 0x1c, &phy1);
-
- bnx2_write_phy(bp, 0x17, 0x0f01);
- bnx2_read_phy(bp, 0x15, &phy2);
- bnx2_write_phy(bp, 0x17, 0x0f01);
- bnx2_read_phy(bp, 0x15, &phy2);
+ bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
+ }
+ } else
+ bp->current_interval = bp->timer_interval;
- if ((phy1 & 0x10) && /* SIGNAL DETECT */
- !(phy2 & 0x20)) { /* no CONFIG */
+ spin_unlock(&bp->phy_lock);
+}
- bmcr &= ~BMCR_ANENABLE;
- bmcr |= BMCR_SPEED1000 |
- BMCR_FULLDPLX;
- bnx2_write_phy(bp, MII_BMCR, bmcr);
- bp->phy_flags |=
- PHY_PARALLEL_DETECT_FLAG;
- }
- }
- }
- else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
- (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
- u32 phy2;
+static void
+bnx2_timer(unsigned long data)
+{
+ struct bnx2 *bp = (struct bnx2 *) data;
+ u32 msg;
- bnx2_write_phy(bp, 0x17, 0x0f01);
- bnx2_read_phy(bp, 0x15, &phy2);
- if (phy2 & 0x20) {
- u32 bmcr;
+ if (!netif_running(bp->dev))
+ return;
- bnx2_read_phy(bp, MII_BMCR, &bmcr);
- bmcr |= BMCR_ANENABLE;
- bnx2_write_phy(bp, MII_BMCR, bmcr);
+ if (atomic_read(&bp->intr_sem) != 0)
+ goto bnx2_restart_timer;
- bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
+ msg = (u32) ++bp->fw_drv_pulse_wr_seq;
+ REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
- }
- }
- else
- bp->current_interval = bp->timer_interval;
+ bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
- spin_unlock(&bp->phy_lock);
- }
+ if ((bp->phy_flags & PHY_SERDES_FLAG) &&
+ (CHIP_NUM(bp) == CHIP_NUM_5706))
+ bnx2_5706_serdes_timer(bp);
bnx2_restart_timer:
mod_timer(&bp->timer, jiffies + bp->current_interval);
prev parent reply other threads:[~2006-11-17 2:28 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1163731443.6658.8.camel@rh4>
2006-11-17 2:58 ` [PATCH 2.6.20 0/17][BNX2]: patches Michael Chan
2006-11-17 2:55 ` Jeff Garzik
2006-11-19 22:15 ` David Miller
2006-11-17 2:59 ` [PATCH 1/17][BNX2]: Fix Xen problem Michael Chan
2006-11-17 2:59 ` [PATCH 2/17][BNX2]: Improve SerDes handling Michael Chan
2006-11-17 2:59 ` [PATCH 4/17][BNX2]: Add 5708S parallel detection Michael Chan
2006-11-17 2:59 ` [PATCH 5/17][BNX2]: Remove udelay() in copper PHY code Michael Chan
2006-11-17 3:00 ` [PATCH 6/17][BNX2]: Re-organize firmware structures Michael Chan
2006-11-17 3:03 ` [PATCH 7/17][BNX2]: Add new 5709 registers (part 1) Michael Chan
2006-11-17 3:03 ` [PATCH 8/17][BNX2]: Add new 5709 registers (part 2) Michael Chan
2006-11-17 3:05 ` [PATCH 9/17][BNX2]: Add 5709 init code Michael Chan
2006-11-17 3:05 ` [PATCH 10/17][BNX2]: Add 5709 reset and runtime code Michael Chan
2006-11-17 3:07 ` [PATCH 11/17][BNX2]: New firmware to support 5709 (part 1) Michael Chan
2006-11-17 3:11 ` [PATCH 12/17][BNX2]: New firmware to support 5709 (part 2) Michael Chan
2006-11-17 3:11 ` [PATCH 13/17][BNX2]: New firmware to support 5709 (part 3) Michael Chan
2006-11-17 3:11 ` [PATCH 14/17][BNX2]: New firmware to support 5709 (part 4) Michael Chan
2006-11-17 3:14 ` [PATCH 15/17][BNX2]: Download 5709 firmware Michael Chan
2006-11-17 3:14 ` [PATCH 16/17][BNX2]: Add 5709 PCI ID Michael Chan
2006-11-17 3:15 ` [PATCH 17/17][BNX2]: Update version and rel date Michael Chan
2006-11-17 3:20 ` Michael Chan [this message]
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