[GIT *] Solos PCI ADSL driver update

[David Woodhouse <dwmw2@infradead.org>]

I'm sorry, I suck. I forgot I had anything outstanding to be pushed
upstream, and should have done this a while ago.

In later versions of the card's FPGA code, the RAM layout for
card<->host communication has changed -- and the new FPGA code is in the
devices which are being shipped now, so it would be really useful if we
could sneak this into 2.6.32. Sorry it's so late.

Please pull from git://git.infradead.org/users/dwmw2/solos-2.6.git

David Woodhouse (1):
      solos: Add some margin-related parameters

Nathan Williams (2):
      solos: support new FPGA RAM layout
      solos: Check for rogue received packets

Simon Farnsworth (1):
      solos: Show Interleaving details for ADSL2 and 2+

 drivers/atm/solos-attrlist.c |   11 ++++++
 drivers/atm/solos-pci.c      |   75 +++++++++++++++++++++++++++++++++++++-----
 2 files changed, 77 insertions(+), 9 deletions(-)

-- 
David Woodhouse                            Open Source Technology Centre
David.Woodhouse@intel.com                              Intel Corporation