From mboxrd@z Thu Jan  1 00:00:00 1970
From: Eric Dumazet <eric.dumazet@gmail.com>
Subject: Re: hackbench regression due to commit 9dfc6e68bfe6e
Date: Thu, 08 Apr 2010 06:59:34 +0200
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Cc: Christoph Lameter <cl@linux-foundation.org>,
	Pekka Enberg <penberg@cs.helsinki.fi>,
	netdev <netdev@vger.kernel.org>, Tejun Heo <tj@kernel.org>,
	alex.shi@intel.com,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"Ma, Ling" <ling.ma@intel.com>,
	"Chen, Tim C" <tim.c.chen@intel.com>,
	Andrew Morton <akpm@linux-foundation.org>
To: "Zhang, Yanmin" <yanmin_zhang@linux.intel.com>
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Le jeudi 08 avril 2010 =C3=A0 09:05 +0800, Zhang, Yanmin a =C3=A9crit :

> > Do we have a user program to check actual L1 cache size of a machin=
e ?
> If there is no, it's easy to write it as kernel exports the cache sta=
t by
> /sys/devices/system/cpu/cpuXXX/cache/indexXXX/

Yes, this is what advertizes my L1 cache having 64bytes lines, but I
would like to check that in practice, this is not 128bytes...

=2E/index0/type:Data
=2E/index0/level:1
=2E/index0/coherency_line_size:64
=2E/index0/physical_line_partition:1
=2E/index0/ways_of_associativity:8
=2E/index0/number_of_sets:64
=2E/index0/size:32K
=2E/index0/shared_cpu_map:00000101
=2E/index0/shared_cpu_list:0,8
=2E/index1/type:Instruction
=2E/index1/level:1
=2E/index1/coherency_line_size:64
=2E/index1/physical_line_partition:1
=2E/index1/ways_of_associativity:4
=2E/index1/number_of_sets:128
=2E/index1/size:32K
=2E/index1/shared_cpu_map:00000101
=2E/index1/shared_cpu_list:0,8