From: "Michael Chan" <mchan@broadcom.com>
To: "Krzysztof Olędzki" <ole@ans.pl>
Cc: "netdev@vger.kernel.org" <netdev@vger.kernel.org>
Subject: Re: bnx2/BCM5709: why 5 interrupts on a 4 core system (2.6.33.3)
Date: Mon, 17 May 2010 19:11:58 -0700 [thread overview]
Message-ID: <1274148718.7893.14.camel@HP1> (raw)
In-Reply-To: <4BF2B3BE.60209@ans.pl>
On Tue, 2010-05-18 at 08:35 -0700, Krzysztof Olędzki wrote:
> On 2010-05-16 20:51, Michael Chan wrote:
> > Krzysztof Oledzki wrote:
> >
> >>
> >> Why the driver registers 5 interrupts instead of 4? How to
> >> limit it to 4?
> >>
> >
> > The first vector (eth0-0) handles link interrupt and other slow
> > path events. It also has an RX ring for non-IP packets that are
> > not hashed by the RSS hash. The majority of the rx packets should
> > be hashed to the rx rings eth0-1 - eth0-4, so I would assign these
> > vectors to different CPUs.
>
> Did some more test on a two 4 core CPUs (8 CPUs reported to the system)
> and on a two 4 core CPUs with HT (16 CPUs reported to the system) and in
> both cases there are 8 instead of 9 vectors: eth0-0 .. eth0-7 (irqs 61
> .. 68). However, dmesg shows that 9 interrupts are allocated:
>
> bnx2 0000:01:00.0: irq 61 for MSI/MSI-X
> bnx2 0000:01:00.0: irq 62 for MSI/MSI-X
> bnx2 0000:01:00.0: irq 63 for MSI/MSI-X
> bnx2 0000:01:00.0: irq 64 for MSI/MSI-X
> bnx2 0000:01:00.0: irq 65 for MSI/MSI-X
> bnx2 0000:01:00.0: irq 66 for MSI/MSI-X
> bnx2 0000:01:00.0: irq 67 for MSI/MSI-X
> bnx2 0000:01:00.0: irq 68 for MSI/MSI-X
> bnx2 0000:01:00.0: irq 69 for MSI/MSI-X
>
> It such case, which ring will be used for slow path and non-IP packets
> and why there is no additional queue like in a 4CPU case?
>
eth0-0 is always the one handling slow path, rx ring 0 (non-IP), and tx
ring 0. The last vector is not used by bnx2. It is reserved for iSCSI
which is handled by the cnic and bnx2i drivers.
next prev parent reply other threads:[~2010-05-18 16:24 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-05-16 13:33 bnx2/BCM5709: why 5 interrupts on a 4 core system (2.6.33.3) Krzysztof Oledzki
2010-05-16 18:51 ` Michael Chan
2010-05-16 19:24 ` Krzysztof Olędzki
2010-05-16 19:49 ` Krzysztof Olędzki
2010-05-16 20:00 ` Michael Chan
2010-05-16 20:15 ` Eric Dumazet
2010-05-16 20:24 ` Michael Chan
2010-05-16 20:34 ` Krzysztof Olędzki
2010-05-16 20:47 ` Eric Dumazet
2010-05-16 21:06 ` George B.
2010-05-16 21:12 ` Krzysztof Olędzki
2010-05-16 21:26 ` Eric Dumazet
2010-05-18 14:22 ` Krzysztof Olędzki
2010-05-18 14:26 ` Eric Dumazet
2010-05-18 14:55 ` Krzysztof Olędzki
2010-05-18 15:35 ` Krzysztof Olędzki
2010-05-18 2:11 ` Michael Chan [this message]
2010-05-18 16:28 ` Krzysztof Olędzki
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