[PATCH] ks8842: Fix TX cache flush issue

[PATCH] ks8842: Fix TX cache flush issue

[Richard Röjfors]

This patch fixes a cache sync issue found in MeeGo 1.1.

It was found that bytes after the first 64 of the TX buffer was not
flushed from the cache correctly.

The patch switches out kmalloc/dma_map_single/dma_sync_single_for_device
to dma_alloc_coherent.

Signed-off-by: Richard Röjfors <richard.rojfors@pelagicore.com>
---
diff --git a/drivers/net/ks8842.c b/drivers/net/ks8842.c
index 928b2b8..55a11ba 100644
--- a/drivers/net/ks8842.c
+++ b/drivers/net/ks8842.c
@@ -449,10 +449,6 @@ static int ks8842_tx_frame_dma(struct sk_buff *skb, struct net_device *netdev)
 	*buf++ = (skb->len >> 8) & 0xff;
 	skb_copy_from_linear_data(skb, buf, skb->len);
 
-	dma_sync_single_range_for_device(adapter->dev,
-		sg_dma_address(&ctl->sg), 0, sg_dma_len(&ctl->sg),
-		DMA_TO_DEVICE);
-
 	/* make sure the length is a multiple of 4 */
 	if (sg_dma_len(&ctl->sg) % 4)
 		sg_dma_len(&ctl->sg) += 4 - sg_dma_len(&ctl->sg) % 4;
@@ -908,12 +904,10 @@ static void ks8842_dealloc_dma_bufs(struct ks8842_adapter *adapter)
 
 	tasklet_kill(&rx_ctl->tasklet);
 
-	if (sg_dma_address(&tx_ctl->sg))
-		dma_unmap_single(adapter->dev, sg_dma_address(&tx_ctl->sg),
-			DMA_BUFFER_SIZE, DMA_TO_DEVICE);
+	if (tx_ctl->buf)
+		dma_free_coherent(adapter->dev, DMA_BUFFER_SIZE,
+			tx_ctl->buf, sg_dma_address(&tx_ctl->sg));
 	sg_dma_address(&tx_ctl->sg) = 0;
-
-	kfree(tx_ctl->buf);
 	tx_ctl->buf = NULL;
 }
 
@@ -945,21 +939,13 @@ static int ks8842_alloc_dma_bufs(struct net_device *netdev)
 	}
 
 	/* allocate DMA buffer */
-	tx_ctl->buf = kmalloc(DMA_BUFFER_SIZE, GFP_KERNEL);
+	tx_ctl->buf = dma_alloc_coherent(adapter->dev, DMA_BUFFER_SIZE,
+		&sg_dma_address(&tx_ctl->sg), GFP_KERNEL);
 	if (!tx_ctl->buf) {
 		err = -ENOMEM;
 		goto err;
 	}
 
-	sg_dma_address(&tx_ctl->sg) = dma_map_single(adapter->dev,
-		tx_ctl->buf, DMA_BUFFER_SIZE, DMA_TO_DEVICE);
-	err = dma_mapping_error(adapter->dev,
-		sg_dma_address(&tx_ctl->sg));
-	if (err) {
-		sg_dma_address(&tx_ctl->sg) = 0;
-		goto err;
-	}
-
 	rx_ctl->chan = dma_request_channel(mask, ks8842_dma_filter_fn,
 					   (void *)(long)rx_ctl->channel);
 	if (!rx_ctl->chan) {

Re: [PATCH] ks8842: Fix TX cache flush issue

[David Miller]

From: Richard Röjfors <richard.rojfors@pelagicore.com>
Date: Mon, 22 Nov 2010 13:50:57 +0100

> This patch fixes a cache sync issue found in MeeGo 1.1.
> 
> It was found that bytes after the first 64 of the TX buffer was not
> flushed from the cache correctly.
> 
> The patch switches out kmalloc/dma_map_single/dma_sync_single_for_device
> to dma_alloc_coherent.
> 
> Signed-off-by: Richard Röjfors <richard.rojfors@pelagicore.com>

Why is dma_sync_single_*() not working properly?

Maybe the length arguments are not correct?  Maybe the cache flush
implementation accidently misses the last cache line when the buffer
length ends in the middle of a cache line.

Did you even check to see what the actual cause of the problem is?

I'm not applying this patch, not enough justification or explanation
in the commit message exists yet.  For all we know there could be
a bug elsewhere, and that would effect other drivers too not just
ks8842.