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[46.193.119.166]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488c5dd1c81sm17369545e9.33.2026.04.08.04.51.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Apr 2026 04:51:05 -0700 (PDT) Message-ID: <1296ca80-f783-4584-b953-f92f6594c39f@gmail.com> Date: Wed, 8 Apr 2026 13:50:54 +0200 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] net: dsa: microchip: implement KSZ87xx Module 3 low-loss cable errata To: Andrew Lunn Cc: Woojung Huh , UNGLinuxDriver@microchip.com, Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Vasut , Maxime Chevallier , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fidelio Lawson References: <20260326-ksz87xx_errata_low_loss_connections-v1-0-79a698f43626@exotec.com> <20260326-ksz87xx_errata_low_loss_connections-v1-3-79a698f43626@exotec.com> Content-Language: en-US From: Fidelio LAWSON In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 4/4/26 16:45, Andrew Lunn wrote: > On Fri, Apr 03, 2026 at 11:43:24AM +0200, Fidelio LAWSON wrote: >> On 3/26/26 13:18, Andrew Lunn wrote: >>>> + mutex_lock(&dev->alu_mutex); >>>> + >>>> + ret = ksz_write8(dev, regs[REG_IND_CTRL_0], 0xA0); >>>> + >>>> + if (!ret) >>>> + ret = ksz_write8(dev, 0x6F, indir_reg); >>>> + >>>> + if (!ret) >>>> + ret = ksz_write8(dev, regs[REG_IND_BYTE], indir_val); >>>> + >>>> + mutex_unlock(&dev->alu_mutex); >>> >>> What address space are these registers in? Normally workarounds for a >>> PHY would be in the PHY driver. But that assumes the registers are >>> accessible from the PHY driver. >>> >>> Andrew >> >> Hi Andrew, >> These registers belong to the KSZ87xx switch address space, accessed through >> the switch’s indirect access mechanism. In particular, the offsets used here >> correspond to entries within the TABLE_LINK_MD_V indirect table of the >> KSZ8-family switches. > > So this errata is for ksz87xx only? > > For this PHY, do all PHY register reads and writes go through > > https://elixir.bootlin.com/linux/v6.19.11/source/drivers/net/dsa/microchip/ksz8.c#L957 > ksz8_r_phy() > > and > > https://elixir.bootlin.com/linux/v6.19.11/source/drivers/net/dsa/microchip/ksz8.c#L1221 > ksz8_w_phy()? > > We already have some "interesting" things going on in these > functions. PHY_REG_LINK_MD and PHY_REG_PHY_CTRL are not standard C22 > PHY registers. They take the values 0x1d and 0x1f. The 802.3 standard > defines 0x10-0x1f as vendor specific, so this is O.K. > > So you could define 2 bits in say register 0x1c to indicate the errata > mode. You can have a PHY tunable which does reads/writes to these two > bits, and ksz8_w_phy/ksz8_r_phy which translates them to indirect > register accesses? > > It is not even really violating the layering. > > Andrew Hi Andrew, Thanks a lot for the feedback, it was very helpful. Yes, the erratum affects KSZ87xx devices only, and all accesses to the embedded PHYs indeed go through ksz8_r_phy() / ksz8_w_phy(), as you pointed out. I followed your suggestion and reworked the implementation accordingly: the errata selection is now modeled as a vendor‑specific Clause 22 PHY register (0x1c), handled entirely in ksz8_r_phy() / ksz8_w_phy(), which translate reads and writes into the appropriate indirect TABLE_LINK_MD_V accesses. This keeps the PHY‑facing API clean without breaking the layering. I’ve dropped the DT approach and adjusted the implementation based on the review comments. I’m sending a v2 with these changes shortly. Thanks again for the guidance. Best regards, Fidelio