* [PATCH v2 1/2] r8169: Correct settings of rtl8102e @ 2011-02-18 8:34 Hayes Wang 2011-02-18 8:34 ` [PATCH v2 2/2] r8169: Support RTL8105E Hayes Wang 0 siblings, 1 reply; 4+ messages in thread From: Hayes Wang @ 2011-02-18 8:34 UTC (permalink / raw) To: romieu; +Cc: netdev, linux-kernel, Hayes Wang Adjust and remove certain settings of RTL8102E which are for previous chips. Signed-off-by: Hayes Wang <hayeswang@realtek.com> --- drivers/net/r8169.c | 20 ++++++-------------- 1 files changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index 59ccf0c..9eaf78f 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c @@ -3042,7 +3042,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) goto err_out_mwi_2; } - tp->cp_cmd = PCIMulRW | RxChkSum; + tp->cp_cmd = RxChkSum; if ((sizeof(dma_addr_t) > 4) && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { @@ -3845,8 +3845,7 @@ static void rtl_hw_start_8168(struct net_device *dev) Cxpl_dbg_sel | \ ASF | \ PktCntrDisable | \ - PCIDAC | \ - PCIMulRW) + Mac_dbgo_sel) static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) { @@ -3876,8 +3875,6 @@ static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) RTL_W8(Config1, cfg1 & ~LEDS0); - RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); - rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); } @@ -3889,8 +3886,6 @@ static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); - - RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); } static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) @@ -3916,6 +3911,8 @@ static void rtl_hw_start_8101(struct net_device *dev) } } + RTL_W8(Cfg9346, Cfg9346_Unlock); + switch (tp->mac_version) { case RTL_GIGA_MAC_VER_07: rtl_hw_start_8102e_1(ioaddr, pdev); @@ -3930,14 +3927,13 @@ static void rtl_hw_start_8101(struct net_device *dev) break; } - RTL_W8(Cfg9346, Cfg9346_Unlock); + RTL_W8(Cfg9346, Cfg9346_Lock); RTL_W8(MaxTxPacketSize, TxPacketMax); rtl_set_rx_max_size(ioaddr, rx_buf_sz); - tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; - + tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK; RTL_W16(CPlusCmd, tp->cp_cmd); RTL_W16(IntrMitigate, 0x0000); @@ -3947,14 +3943,10 @@ static void rtl_hw_start_8101(struct net_device *dev) RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); rtl_set_rx_tx_config_registers(tp); - RTL_W8(Cfg9346, Cfg9346_Lock); - RTL_R8(IntrMask); rtl_set_rx_mode(dev); - RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); - RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); RTL_W16(IntrMask, tp->intr_event); -- 1.7.3.2 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 2/2] r8169: Support RTL8105E 2011-02-18 8:34 [PATCH v2 1/2] r8169: Correct settings of rtl8102e Hayes Wang @ 2011-02-18 8:34 ` Hayes Wang 2011-02-21 7:33 ` Francois Romieu 0 siblings, 1 reply; 4+ messages in thread From: Hayes Wang @ 2011-02-18 8:34 UTC (permalink / raw) To: romieu; +Cc: netdev, linux-kernel, Hayes Wang Support the new chips for RTL8105E Signed-off-by: Hayes Wang <hayeswang@realtek.com> --- drivers/net/r8169.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 90 insertions(+), 2 deletions(-) diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index 9eaf78f..ffe6b00 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c @@ -36,6 +36,7 @@ #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" +#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" #ifdef RTL8169_DEBUG #define assert(expr) \ @@ -123,6 +124,8 @@ enum mac_version { RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP + RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E + RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E }; #define _R(NAME,MAC,MASK) \ @@ -160,7 +163,9 @@ static const struct { _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E - _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880) // PCI-E + _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E + _R("RTL8105e", RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E + _R("RTL8105e", RTL_GIGA_MAC_VER_30, 0xff7e1880) // PCI-E }; #undef _R @@ -267,6 +272,12 @@ enum rtl8168_8101_registers { #define EPHYAR_REG_MASK 0x1f #define EPHYAR_REG_SHIFT 16 #define EPHYAR_DATA_MASK 0xffff + DLLPR = 0xd0, +#define PM_SWITCH (1 << 6) + TWSI = 0xd2, + MCU = 0xd3, +#define EN_NDP (1 << 3) +#define EN_OOB_RESET (1 << 2) DBG_REG = 0xd1, #define FIX_NAK_1 (1 << 4) #define FIX_NAK_2 (1 << 3) @@ -568,6 +579,7 @@ MODULE_LICENSE("GPL"); MODULE_VERSION(RTL8169_VERSION); MODULE_FIRMWARE(FIRMWARE_8168D_1); MODULE_FIRMWARE(FIRMWARE_8168D_2); +MODULE_FIRMWARE(FIRMWARE_8105E_1); static int rtl8169_open(struct net_device *dev); static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, @@ -1143,7 +1155,9 @@ static int rtl8169_set_speed_xmii(struct net_device *dev, (tp->mac_version != RTL_GIGA_MAC_VER_13) && (tp->mac_version != RTL_GIGA_MAC_VER_14) && (tp->mac_version != RTL_GIGA_MAC_VER_15) && - (tp->mac_version != RTL_GIGA_MAC_VER_16)) { + (tp->mac_version != RTL_GIGA_MAC_VER_16) && + (tp->mac_version != RTL_GIGA_MAC_VER_29) && + (tp->mac_version != RTL_GIGA_MAC_VER_30)) { giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; } else { netif_info(tp, link, dev, @@ -1559,6 +1573,9 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp, { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, /* 8101 family. */ + { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, + { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, + { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, @@ -2435,6 +2452,33 @@ static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); } +static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) +{ + static const struct phy_reg phy_reg_init[] = { + {0x1f, 0x0005}, + {0x1a, 0x0000}, + {0x1f, 0x0000}, + + {0x1f, 0x0004}, + {0x1c, 0x0000}, + {0x1f, 0x0000}, + + {0x1f, 0x0001}, + {0x15, 0x7701}, + {0x1f, 0x0000} + }; + + /* Diable ALDPS before ram code */ + rtl_writephy(tp, 0x1f, 0x0000); + rtl_writephy(tp, 0x18, 0x0310); + msleep(100); + + if (rtl_apply_firmware(tp, FIRMWARE_8105E_1) < 0) + netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n"); + + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); +} + static void rtl_hw_phy_config(struct net_device *dev) { struct rtl8169_private *tp = netdev_priv(dev); @@ -2502,6 +2546,10 @@ static void rtl_hw_phy_config(struct net_device *dev) case RTL_GIGA_MAC_VER_28: rtl8168d_4_hw_phy_config(tp); break; + case RTL_GIGA_MAC_VER_29: + case RTL_GIGA_MAC_VER_30: + rtl8105e_hw_phy_config(tp); + break; default: break; @@ -2940,6 +2988,8 @@ static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) case RTL_GIGA_MAC_VER_09: case RTL_GIGA_MAC_VER_10: case RTL_GIGA_MAC_VER_16: + case RTL_GIGA_MAC_VER_29: + case RTL_GIGA_MAC_VER_30: ops->down = r810x_pll_power_down; ops->up = r810x_pll_power_up; break; @@ -3895,6 +3945,37 @@ static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) rtl_ephy_write(ioaddr, 0x03, 0xc2f9); } +static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev) +{ + static const struct ephy_info e_info_8105e_1[] = { + { 0x07, 0, 0x4000 }, + { 0x19, 0, 0x0200 }, + { 0x19, 0, 0x0020 }, + { 0x1e, 0, 0x2000 }, + { 0x03, 0, 0x0001 }, + { 0x19, 0, 0x0100 }, + { 0x19, 0, 0x0004 }, + { 0x0a, 0, 0x0020 } + }; + + /* Force LAN exit from ASPM if Rx/Tx are not idel */ + RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); + + /* disable Early Tally Counter */ + RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); + + RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); + RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH); + + rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); +} + +static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev) +{ + rtl_hw_start_8105e_1(ioaddr, pdev); + rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000); +} + static void rtl_hw_start_8101(struct net_device *dev) { struct rtl8169_private *tp = netdev_priv(dev); @@ -3925,6 +4006,13 @@ static void rtl_hw_start_8101(struct net_device *dev) case RTL_GIGA_MAC_VER_09: rtl_hw_start_8102e_2(ioaddr, pdev); break; + + case RTL_GIGA_MAC_VER_29: + rtl_hw_start_8105e_1(ioaddr, pdev); + break; + case RTL_GIGA_MAC_VER_30: + rtl_hw_start_8105e_2(ioaddr, pdev); + break; } RTL_W8(Cfg9346, Cfg9346_Lock); -- 1.7.3.2 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2 2/2] r8169: Support RTL8105E 2011-02-18 8:34 ` [PATCH v2 2/2] r8169: Support RTL8105E Hayes Wang @ 2011-02-21 7:33 ` Francois Romieu 2011-02-21 9:17 ` hayeswang 0 siblings, 1 reply; 4+ messages in thread From: Francois Romieu @ 2011-02-21 7:33 UTC (permalink / raw) To: Hayes Wang; +Cc: netdev, linux-kernel Hayes Wang <hayeswang@realtek.com> : > Support the new chips for RTL8105E > > Signed-off-by: Hayes Wang <hayeswang@realtek.com> > --- > drivers/net/r8169.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++++- > 1 files changed, 90 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c > index 9eaf78f..ffe6b00 100644 > --- a/drivers/net/r8169.c > +++ b/drivers/net/r8169.c [...] > @@ -267,6 +272,12 @@ enum rtl8168_8101_registers { > #define EPHYAR_REG_MASK 0x1f > #define EPHYAR_REG_SHIFT 16 > #define EPHYAR_DATA_MASK 0xffff > + DLLPR = 0xd0, > +#define PM_SWITCH (1 << 6) > + TWSI = 0xd2, > + MCU = 0xd3, > +#define EN_NDP (1 << 3) > +#define EN_OOB_RESET (1 << 2) > DBG_REG = 0xd1, > #define FIX_NAK_1 (1 << 4) > #define FIX_NAK_2 (1 << 3) Please pack them in increasing order and it will be perfect (i.e. 0xd0, 0xd1, 0xd2, 0xd3 instead of current 0xd0, 0xd2 (?), 0xd3, 0xd1). [...] > @@ -2435,6 +2452,33 @@ static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) > rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); > } > > +static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) > +{ > + static const struct phy_reg phy_reg_init[] = { > + {0x1f, 0x0005}, > + {0x1a, 0x0000}, > + {0x1f, 0x0000}, > + > + {0x1f, 0x0004}, > + {0x1c, 0x0000}, > + {0x1f, 0x0000}, > + > + {0x1f, 0x0001}, > + {0x15, 0x7701}, > + {0x1f, 0x0000} ^^ ^^ Minor nit: please insert spaces (as in similar declarations). > + }; > + > + /* Diable ALDPS before ram code */ ^^ Missing "b". > + rtl_writephy(tp, 0x1f, 0x0000); > + rtl_writephy(tp, 0x18, 0x0310); > + msleep(100); > + > + if (rtl_apply_firmware(tp, FIRMWARE_8105E_1) < 0) > + netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n"); > + > + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); > +} The "if (RTL_R8(0xef) & 0x08)" and "if (RTL_R8(0xef) & 0x010)" conditionals from the previous iteration have been removed. If it is done on purpose, a short explanation or notification in the description of the patch is always welcome. -- Ueimor ^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH v2 2/2] r8169: Support RTL8105E 2011-02-21 7:33 ` Francois Romieu @ 2011-02-21 9:17 ` hayeswang 0 siblings, 0 replies; 4+ messages in thread From: hayeswang @ 2011-02-21 9:17 UTC (permalink / raw) To: 'Francois Romieu'; +Cc: netdev, linux-kernel > -----Original Message----- > From: Francois Romieu [mailto:romieu@fr.zoreil.com] > Sent: Monday, February 21, 2011 3:33 PM > To: Hayeswang > Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v2 2/2] r8169: Support RTL8105E > > > @@ -267,6 +272,12 @@ enum rtl8168_8101_registers { > > #define EPHYAR_REG_MASK 0x1f > > #define EPHYAR_REG_SHIFT 16 > > #define EPHYAR_DATA_MASK 0xffff > > + DLLPR = 0xd0, > > +#define PM_SWITCH (1 << 6) > > + TWSI = 0xd2, > > + MCU = 0xd3, > > +#define EN_NDP (1 << 3) > > +#define EN_OOB_RESET (1 << 2) > > DBG_REG = 0xd1, > > #define FIX_NAK_1 (1 << 4) > > #define FIX_NAK_2 (1 << 3) > > Please pack them in increasing order and it will be perfect > (i.e. 0xd0, 0xd1, 0xd2, 0xd3 instead of current 0xd0, 0xd2 > (?), 0xd3, 0xd1). It's my mistake. I would fix that. > > > + rtl_writephy(tp, 0x1f, 0x0000); > > + rtl_writephy(tp, 0x18, 0x0310); > > + msleep(100); > > + > > + if (rtl_apply_firmware(tp, FIRMWARE_8105E_1) < 0) > > + netif_warn(tp, probe, tp->dev, "unable to apply > firmware patch\n"); > > + > > + rtl_writephy_batch(tp, phy_reg_init, > ARRAY_SIZE(phy_reg_init)); } > > The "if (RTL_R8(0xef) & 0x08)" and "if (RTL_R8(0xef) & > 0x010)" conditionals from the previous iteration have been > removed. If it is done on purpose, a short explanation or > notification in the description of the patch is always welcome. > These two conditions are using for customization. I remove them and use the default settings. Best Regards, Hayes ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2011-02-21 9:17 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2011-02-18 8:34 [PATCH v2 1/2] r8169: Correct settings of rtl8102e Hayes Wang 2011-02-18 8:34 ` [PATCH v2 2/2] r8169: Support RTL8105E Hayes Wang 2011-02-21 7:33 ` Francois Romieu 2011-02-21 9:17 ` hayeswang
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