From mboxrd@z Thu Jan 1 00:00:00 1970 From: Giuseppe CAVALLARO Subject: [PATCH 02/10] stmmac: Define CSUM offload engine Types Date: Fri, 23 Mar 2012 10:08:33 +0100 Message-ID: <1332493721-28309-3-git-send-email-peppe.cavallaro@st.com> References: <1332493721-28309-1-git-send-email-peppe.cavallaro@st.com> Cc: davem@davemloft.net, srinivas.kandagatla@st.com, deepak.sikri@st.com, spear-devel@list.st.com, shiraz.hashim@st.com, viresh.kumar@st.com, bhutchings@solarflare.com To: netdev@vger.kernel.org Return-path: Received: from eu1sys200aog103.obsmtp.com ([207.126.144.115]:49950 "EHLO eu1sys200aog103.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757854Ab2CWJJ0 (ORCPT ); Fri, 23 Mar 2012 05:09:26 -0400 In-Reply-To: <1332493721-28309-1-git-send-email-peppe.cavallaro@st.com> Sender: netdev-owner@vger.kernel.org List-ID: From: Deepak SIKRI This patch explicitly defines the CSUM offload engine type which need (not mandatory) to be passed from the platform code. STMMAC core supports two check sum offload engine types- Type-1 & Type-2. Also, there are STMMAC cores that do not have the check sum offload capabilities. The behaviour of Type-1 & Type-2 cores related to provision of checksum increases the packet length for Type-1 cores by 2, as the checksum is appended at the end of data packet and the same is made accountable in the DMA status. The STMMAC cores beyond Version-3.5 provide HW interface registers which allows the user to read the HW capabilities, while to support the previous cores the information related to HW capabilities has to be provided from the platform code. The Type-1 cores which do not have the HW register interface need this information. This patch also updates the driver's doc. Signed-off-by: Deepak Sikri Hacked-by: Giuseppe Cavallaro --- Documentation/networking/stmmac.txt | 3 +++ include/linux/stmmac.h | 5 +++++ 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/Documentation/networking/stmmac.txt b/Documentation/networking/stmmac.txt index d0aeead..61f40a3 100644 --- a/Documentation/networking/stmmac.txt +++ b/Documentation/networking/stmmac.txt @@ -116,6 +116,7 @@ and detailed below as well: int has_gmac; int enh_desc; int tx_coe; + int rx_coe; int bugged_jumbo; int pmt; int force_sf_dma_mode; @@ -140,6 +141,8 @@ Where: o has_gmac: uses the GMAC core. o enh_desc: if sets the MAC will use the enhanced descriptor structure. o tx_coe: core is able to perform the tx csum in HW. + o rx_coe: the supports three check sum offloading engine types: + type_1, type_2 (full csum) and no RX coe. o bugged_jumbo: some HWs are not able to perform the csum in HW for over-sized frames due to limited buffer sizes. Setting this flag the csum will be done in SW on diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 172b5e1..a9b4d6c 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -28,6 +28,10 @@ #include +#define STMMAC_RX_COE_NONE 0 +#define STMMAC_RX_COE_TYPE1 1 +#define STMMAC_RX_COE_TYPE2 2 + /* Platfrom data for platform device structure's platform_data field */ struct stmmac_mdio_bus_data { @@ -49,6 +53,7 @@ struct plat_stmmacenet_data { int has_gmac; int enh_desc; int tx_coe; + int rx_coe; int bugged_jumbo; int pmt; int force_sf_dma_mode; -- 1.7.4.4