From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eric Dumazet Subject: Re: [PATCH] virtio-net: fix a race on 32bit arches Date: Wed, 06 Jun 2012 10:45:41 +0200 Message-ID: <1338972341.2760.3944.camel@edumazet-glaptop> References: <1338971724.2760.3913.camel@edumazet-glaptop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: mst@redhat.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, virtualization@lists.linux-foundation.org, Stephen Hemminger To: Jason Wang Return-path: In-Reply-To: <1338971724.2760.3913.camel@edumazet-glaptop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: virtualization-bounces@lists.linux-foundation.org Errors-To: virtualization-bounces@lists.linux-foundation.org List-Id: netdev.vger.kernel.org On Wed, 2012-06-06 at 10:35 +0200, Eric Dumazet wrote: > From: Eric Dumazet > > commit 3fa2a1df909 (virtio-net: per cpu 64 bit stats (v2)) added a race > on 32bit arches. > > We must use separate syncp for rx and tx path as they can be run at the > same time on different cpus. Thus one sequence increment can be lost and > readers spin forever. > > Signed-off-by: Eric Dumazet > Cc: Stephen Hemminger > Cc: Michael S. Tsirkin > Cc: Jason Wang > --- Just to make clear : even using percpu stats/syncp, we have no guarantee that write_seqcount_begin() is done with one instruction. [1] It is OK on x86 if "incl" instruction is generated by the compiler, but on a RISC cpu, the "load memory,%reg ; inc %reg ; store %reg,memory" can be interrupted. So if you are 100% sure all paths are safe against preemption/BH, then this patch is not needed, but a big comment in the code would avoid adding possible races in the future. [1] If done with one instruction, we still have a race, since a reader might see an even sequence and conclude no writer is inside the critical section. So read values could be wrong.