[PATCH v2 0/3] net/macb: fixes to use core on Zynq SoCs

[PATCH v2 0/3] net/macb: fixes to use core on Zynq SoCs

[Steffen Trumtrar]

Hi!

The Cadence GEM is also licensed for the Xilinx Zynq7000 SoCs.
As Xilinx uses other reset defaults, some fixes are necessary to have it
working there. And as the Zynq is dualcore, the clk_enables/disables now need
to be atomic.

Changes in v2:
	- only 3/3 was changed to correctly use the atomic clk_[en|dis]able

Regards,
Steffen

Steffen Trumtrar (3):
  net/macb: clear tx/rx completion flags in ISR
  net/macb: force endian_swp_pkt_en to off
  net/macb: make clk_enable atomic

 drivers/net/ethernet/cadence/macb.c | 24 ++++++++++++++----------
 drivers/net/ethernet/cadence/macb.h |  2 ++
 2 files changed, 16 insertions(+), 10 deletions(-)

-- 
1.8.2.rc2

[PATCH v2 1/3] net/macb: clear tx/rx completion flags in ISR

[Steffen Trumtrar]

At least in the cadence IP core on the Xilinx Zynq SoC the TCOMP/RCOMP flags
are not auto-cleaned. As these flags are evaluated, they need to be cleaned.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 drivers/net/ethernet/cadence/macb.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 7903943..817835e 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -485,6 +485,8 @@ static void macb_tx_interrupt(struct macb *bp)
 	status = macb_readl(bp, TSR);
 	macb_writel(bp, TSR, status);
 
+	macb_writel(bp, ISR, MACB_BIT(TCOMP));
+
 	netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
 		(unsigned long)status);
 
@@ -736,6 +738,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
 			 * now.
 			 */
 			macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
+			macb_writel(bp, ISR, MACB_BIT(RCOMP));
 
 			if (napi_schedule_prep(&bp->napi)) {
 				netdev_vdbg(bp->dev, "scheduling RX softirq\n");
-- 
1.8.2.rc2

[PATCH v2 2/3] net/macb: force endian_swp_pkt_en to off

[Steffen Trumtrar]

The core has a bit for swapping packet data endianism.
Reset default from Cadence is off. Xilinx however, who uses this core on the
Zynq SoCs, opted for on.
Force it to off. This shouldn't change the behaviour for current users of the
macb, but enables usage on Zynq devices.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 drivers/net/ethernet/cadence/macb.c | 1 +
 drivers/net/ethernet/cadence/macb.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 817835e..71e766b 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1057,6 +1057,7 @@ static void macb_configure_dma(struct macb *bp)
 		dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64);
 		dmacfg |= GEM_BF(FBLDO, 16);
 		dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
+		dmacfg &= ~GEM_BIT(ENDIA);
 		gem_writel(bp, DMACFG, dmacfg);
 	}
 }
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 570908b..993d703 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -173,6 +173,8 @@
 /* Bitfields in DMACFG. */
 #define GEM_FBLDO_OFFSET			0
 #define GEM_FBLDO_SIZE				5
+#define GEM_ENDIA_OFFSET			7
+#define GEM_ENDIA_SIZE				1
 #define GEM_RXBMS_OFFSET			8
 #define GEM_RXBMS_SIZE				2
 #define GEM_TXPBMS_OFFSET			10
-- 
1.8.2.rc2

[PATCH v2 3/3] net/macb: make clk_enable atomic

[Steffen Trumtrar]

Use clk_prepare_enable/clk_disable_unprepare to be safe on SMP systems.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Fabio Estevam <festevam@gmail.com>
---

Changes in v2:
	- use clk_disable_unprepare() (reported by Fabio Estevam)
	- use clk_prepare_enable() in resume function

 drivers/net/ethernet/cadence/macb.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 71e766b..4378d63 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1561,14 +1561,14 @@ static int __init macb_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "failed to get macb_clk\n");
 		goto err_out_free_dev;
 	}
-	clk_enable(bp->pclk);
+	clk_prepare_enable(bp->pclk);
 
 	bp->hclk = clk_get(&pdev->dev, "hclk");
 	if (IS_ERR(bp->hclk)) {
 		dev_err(&pdev->dev, "failed to get hclk\n");
 		goto err_out_put_pclk;
 	}
-	clk_enable(bp->hclk);
+	clk_prepare_enable(bp->hclk);
 
 	bp->regs = ioremap(regs->start, resource_size(regs));
 	if (!bp->regs) {
@@ -1658,9 +1658,9 @@ err_out_free_irq:
 err_out_iounmap:
 	iounmap(bp->regs);
 err_out_disable_clocks:
-	clk_disable(bp->hclk);
+	clk_disable_unprepare(bp->hclk);
 	clk_put(bp->hclk);
-	clk_disable(bp->pclk);
+	clk_disable_unprepare(bp->pclk);
 err_out_put_pclk:
 	clk_put(bp->pclk);
 err_out_free_dev:
@@ -1687,9 +1687,9 @@ static int __exit macb_remove(struct platform_device *pdev)
 		unregister_netdev(dev);
 		free_irq(dev->irq, dev);
 		iounmap(bp->regs);
-		clk_disable(bp->hclk);
+		clk_disable_unprepare(bp->hclk);
 		clk_put(bp->hclk);
-		clk_disable(bp->pclk);
+		clk_disable_unprepare(bp->pclk);
 		clk_put(bp->pclk);
 		free_netdev(dev);
 		platform_set_drvdata(pdev, NULL);
@@ -1707,8 +1707,8 @@ static int macb_suspend(struct platform_device *pdev, pm_message_t state)
 	netif_carrier_off(netdev);
 	netif_device_detach(netdev);
 
-	clk_disable(bp->hclk);
-	clk_disable(bp->pclk);
+	clk_disable_unprepare(bp->hclk);
+	clk_disable_unprepare(bp->pclk);
 
 	return 0;
 }
@@ -1718,8 +1718,8 @@ static int macb_resume(struct platform_device *pdev)
 	struct net_device *netdev = platform_get_drvdata(pdev);
 	struct macb *bp = netdev_priv(netdev);
 
-	clk_enable(bp->pclk);
-	clk_enable(bp->hclk);
+	clk_prepare_enable(bp->pclk);
+	clk_prepare_enable(bp->hclk);
 
 	netif_device_attach(netdev);
 
-- 
1.8.2.rc2

Re: [PATCH v2 0/3] net/macb: fixes to use core on Zynq SoCs

[Nicolas Ferre]

On 03/28/2013 10:07 AM, Steffen Trumtrar :
> Hi!
> 
> The Cadence GEM is also licensed for the Xilinx Zynq7000 SoCs.
> As Xilinx uses other reset defaults, some fixes are necessary to have it
> working there. And as the Zynq is dualcore, the clk_enables/disables now need
> to be atomic.
> 
> Changes in v2:
> 	- only 3/3 was changed to correctly use the atomic clk_[en|dis]able
> 
> Regards,
> Steffen

On the whole series:

Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Thanks, best regards.

> Steffen Trumtrar (3):
>   net/macb: clear tx/rx completion flags in ISR
>   net/macb: force endian_swp_pkt_en to off
>   net/macb: make clk_enable atomic
> 
>  drivers/net/ethernet/cadence/macb.c | 24 ++++++++++++++----------
>  drivers/net/ethernet/cadence/macb.h |  2 ++
>  2 files changed, 16 insertions(+), 10 deletions(-)
> 


-- 
Nicolas Ferre

Re: [PATCH v2 0/3] net/macb: fixes to use core on Zynq SoCs

[Steffen Trumtrar]

On Thu, Mar 28, 2013 at 12:10:41PM +0100, Nicolas Ferre wrote:
> On 03/28/2013 10:07 AM, Steffen Trumtrar :
> > Hi!
> > 
> > The Cadence GEM is also licensed for the Xilinx Zynq7000 SoCs.
> > As Xilinx uses other reset defaults, some fixes are necessary to have it
> > working there. And as the Zynq is dualcore, the clk_enables/disables now need
> > to be atomic.
> > 
> > Changes in v2:
> > 	- only 3/3 was changed to correctly use the atomic clk_[en|dis]able
> > 
> > Regards,
> > Steffen
> 
> On the whole series:
> 
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> 
> Thanks, best regards.
> 

Thanks,
Steffen

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Re: [PATCH v2 0/3] net/macb: fixes to use core on Zynq SoCs

[David Miller]

From: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Date: Thu, 28 Mar 2013 10:07:04 +0100

> The Cadence GEM is also licensed for the Xilinx Zynq7000 SoCs.
> As Xilinx uses other reset defaults, some fixes are necessary to have it
> working there. And as the Zynq is dualcore, the clk_enables/disables now need
> to be atomic.
> 
> Changes in v2:
> 	- only 3/3 was changed to correctly use the atomic clk_[en|dis]able

Series applied, thanks.