From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Subject: Re: [PATCH net-next 3/4] igb: do not clobber the TSAUXC bits on
 reset.
Date: Mon, 27 May 2013 17:44:49 -0700
Message-ID: <1369701889.2116.137.camel@jtkirshe-mobl>
References: <cover.1369645944.git.richardcochran@gmail.com>
	 <0c838f7cd866c88eb85bb8d2aaaef21048a7d0e9.1369645944.git.richardcochran@gmail.com>
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Cc: netdev@vger.kernel.org, David Miller <davem@davemloft.net>,
	e1000-devel@lists.sourceforge.net,
	Jacob Keller <jacob.e.keller@intel.com>,
	Matthew Vick <matthew.vick@intel.com>
To: Richard Cochran <richardcochran@gmail.com>
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On Mon, 2013-05-27 at 11:21 +0200, Richard Cochran wrote:
> The TSAUXC register has a number of different bits, one of which
> disables
> the main clock function. Previously, the clock was re-enabled by
> clearing
> the entire register. This patch changes the code to preserve the
> values
> of the other bits in that register.
>=20
> Signed-off-by: Richard Cochran <richardcochran@gmail.com>
> ---
>  drivers/net/ethernet/intel/igb/igb_ptp.c |    8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)=20

Thanks Richard, I will add this to my queue.

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