* [PATCH] cxgb4: Decode PCIe Gen3 link speed
@ 2014-04-29 0:36 Roland Dreier
2014-04-30 20:14 ` David Miller
0 siblings, 1 reply; 2+ messages in thread
From: Roland Dreier @ 2014-04-29 0:36 UTC (permalink / raw)
To: Dimitris Michailidis; +Cc: David S. Miller, netdev, Roland Dreier
From: Roland Dreier <roland@purestorage.com>
Add handling for " 8 GT/s" in print_port_info().
Signed-off-by: Roland Dreier <roland@purestorage.com>
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 6fe58913403a..24e16e3301e0 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -5870,6 +5870,8 @@ static void print_port_info(const struct net_device *dev)
spd = " 2.5 GT/s";
else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
spd = " 5 GT/s";
+ else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
+ spd = " 8 GT/s";
if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
bufp += sprintf(bufp, "100/");
--
1.9.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] cxgb4: Decode PCIe Gen3 link speed
2014-04-29 0:36 [PATCH] cxgb4: Decode PCIe Gen3 link speed Roland Dreier
@ 2014-04-30 20:14 ` David Miller
0 siblings, 0 replies; 2+ messages in thread
From: David Miller @ 2014-04-30 20:14 UTC (permalink / raw)
To: roland; +Cc: dm, netdev, roland
From: Roland Dreier <roland@kernel.org>
Date: Mon, 28 Apr 2014 17:36:20 -0700
> From: Roland Dreier <roland@purestorage.com>
>
> Add handling for " 8 GT/s" in print_port_info().
>
> Signed-off-by: Roland Dreier <roland@purestorage.com>
Applied.
^ permalink raw reply [flat|nested] 2+ messages in thread
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2014-04-30 20:14 ` David Miller
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