[PATCH net 0/4] bnx2x: Bug fixes patch series

[PATCH net 0/4] bnx2x: Bug fixes patch series

[Yuval Mintz]

Hi Dave,

This patch series contains various bug fixes - 2 link related fixes,
one sriov-related issue and an additional fix for a theoretical bug
on new boards.

Please consider applying these patches to `net'.

Thanks,
Yuval Mintz

[PATCH net 1/4] bnx2x: Fix link for KR with swapped polarity lane

[Yuval Mintz]

From: Yaniv Rosner <yaniv.rosner@qlogic.com>

This avoids clearing the RX polarity setting in KR mode when polarity lane
is swapped, as otherwise this will result in failed link.

Signed-off-by: Yaniv Rosner <yaniv.rosner@qlogic.com>
Signed-off-by: Yuval Mintz <yuval.mintz@qlogic.com>
Signed-off-by: Ariel Elior <ariel.elior@qlogic.com>
---
 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | 25 ++++++++++++++++++------
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index 9b6b3d7..b052f56 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -3703,7 +3703,8 @@ static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
 					struct link_params *params,
 					struct link_vars *vars) {
-	u16 lane, i, cl72_ctrl, an_adv = 0;
+	u16 lane, i, cl72_ctrl, an_adv = 0, val;
+	u32 wc_lane_config;
 	struct bnx2x *bp = params->bp;
 	static struct bnx2x_reg_set reg_set[] = {
 		{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
@@ -3822,15 +3823,27 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
 		/* Enable Auto-Detect to support 1G over CL37 as well */
 		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
 				 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
-
+		wc_lane_config = REG_RD(bp, params->shmem_base +
+					offsetof(struct shmem_region, dev_info.
+					shared_hw_config.wc_lane_config));
+		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
+				MDIO_WC_REG_RX0_PCI_CTRL + (0x10 * lane), &val);
 		/* Force cl48 sync_status LOW to avoid getting stuck in CL73
 		 * parallel-detect loop when CL73 and CL37 are enabled.
 		 */
-		CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
-				  MDIO_AER_BLOCK_AER_REG, 0);
+		val |= (1<<11);
+
+		/* Restore Polarity settings in case it was run over by
+		 * previous link owner
+		 */
+		if (wc_lane_config &
+		    (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
+			val |= (3<<2);
+		else
+			val &= ~(3<<2);
 		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
-				 MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI, 0x0800);
-		bnx2x_set_aer_mmd(params, phy);
+				 MDIO_WC_REG_RX0_PCI_CTRL + (0x10 * lane),
+				 val);
 
 		bnx2x_disable_kr2(params, vars, phy);
 	}
-- 
1.8.1.4

Re: [PATCH net 1/4] bnx2x: Fix link for KR with swapped polarity lane

[Sergei Shtylyov]

On 06/11/2014 05:27 PM, Yuval Mintz wrote:

> From: Yaniv Rosner <yaniv.rosner@qlogic.com>

> This avoids clearing the RX polarity setting in KR mode when polarity lane
> is swapped, as otherwise this will result in failed link.

> Signed-off-by: Yaniv Rosner <yaniv.rosner@qlogic.com>
> Signed-off-by: Yuval Mintz <yuval.mintz@qlogic.com>
> Signed-off-by: Ariel Elior <ariel.elior@qlogic.com>
> ---
>   drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | 25 ++++++++++++++++++------
>   1 file changed, 19 insertions(+), 6 deletions(-)

> diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
> index 9b6b3d7..b052f56 100644
> --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
> +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
[...]
> @@ -3822,15 +3823,27 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
>   		/* Enable Auto-Detect to support 1G over CL37 as well */
>   		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
>   				 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
> -
> +		wc_lane_config = REG_RD(bp, params->shmem_base +
> +					offsetof(struct shmem_region, dev_info.
> +					shared_hw_config.wc_lane_config));
> +		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
> +				MDIO_WC_REG_RX0_PCI_CTRL + (0x10 * lane), &val);

    () around * not needed. You could also replace it by (lane << 4).

>   		/* Force cl48 sync_status LOW to avoid getting stuck in CL73
>   		 * parallel-detect loop when CL73 and CL37 are enabled.
>   		 */
> -		CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
> -				  MDIO_AER_BLOCK_AER_REG, 0);
> +		val |= (1<<11);

    () not needed here. And could you please enclose << with spaces for 
consistency?

> +
> +		/* Restore Polarity settings in case it was run over by
> +		 * previous link owner
> +		 */
> +		if (wc_lane_config &
> +		    (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
> +			val |= (3<<2);
> +		else
> +			val &= ~(3<<2);

    Same comments here (2nd case needs parens though).

WBR, Sergei

RE: [PATCH net 1/4] bnx2x: Fix link for KR with swapped polarity lane

[Yuval Mintz]

>> +                             MDIO_WC_REG_RX0_PCI_CTRL + (0x10 * lane), &val);

>    () around * not needed. You could also replace it by (lane << 4).

Hi,

bnx2x_link.c is full of format inconsistencies, as well as many cases of
unnecessary parenthesis.
It might be reasonable to send a semantic script to `net-next' in order
to fix all those issues, but I'm not sure we should re-spin this series
only because of such `common' inconsistencies.

Dave - whichever you prefer; If you want me to re-spin it, I will.

Cheers,
Yuval

________________________________

This message and any attached documents contain information from QLogic Corporation or its wholly-owned subsidiaries that may be confidential. If you are not the intended recipient, you may not read, copy, distribute, or use this information. If you have received this transmission in error, please notify the sender immediately by reply e-mail and then delete this message.

Re: [PATCH net 1/4] bnx2x: Fix link for KR with swapped polarity lane

[David Miller]

From: Yuval Mintz <Yuval.Mintz@qlogic.com>
Date: Wed, 11 Jun 2014 18:40:35 +0000

>>> +                             MDIO_WC_REG_RX0_PCI_CTRL + (0x10 * lane), &val);
> 
>>    () around * not needed. You could also replace it by (lane << 4).
> 
> Hi,
> 
> bnx2x_link.c is full of format inconsistencies, as well as many cases of
> unnecessary parenthesis.
> It might be reasonable to send a semantic script to `net-next' in order
> to fix all those issues, but I'm not sure we should re-spin this series
> only because of such `common' inconsistencies.
> 
> Dave - whichever you prefer; If you want me to re-spin it, I will.

Please respin.

[PATCH net 2/4] bnx2x: Fix 1G-baseT link

[Yuval Mintz]

From: Yaniv Rosner <yaniv.rosner@qlogic.com>

Set the phy access mode even in case of link-flap avoidance.

Signed-off-by: Yaniv Rosner <yaniv.rosner@qlogic.com>
Signed-off-by: Yuval Mintz <yuval.mintz@qlogic.com>
Signed-off-by: Ariel Elior <ariel.elior@qlogic.com>
---
 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index b052f56..3141660 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -12474,6 +12474,7 @@ static int bnx2x_avoid_link_flap(struct link_params *params,
 	u32 dont_clear_stat, lfa_sts;
 	struct bnx2x *bp = params->bp;
 
+	bnx2x_set_mdio_emac_per_phy(bp, params);
 	/* Sync the link parameters */
 	bnx2x_link_status_update(params, vars);
 
-- 
1.8.1.4

[PATCH net 3/4] bnx2x: Check for UNDI in uncommon branch

[Yuval Mintz]

If L2FW utilized by the UNDI driver has the same version number as that
of the regular FW, a driver loading after UNDI and receiving an uncommon
answer from management will mistakenly assume the loaded FW matches its
own requirement and try to exist the flow via FLR.

Signed-off-by: Yuval Mintz <yuval.mintz@qlogic.com>
Signed-off-by: Ariel Elior <ariel.elior@qlogic.com>
---
 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 43 +++++++++++++++++-------
 1 file changed, 30 insertions(+), 13 deletions(-)

diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index ff2bdd8..8ea644b 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -10053,6 +10053,24 @@ static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
 #define BCM_5710_UNDI_FW_MF_VERS	(0x05)
 #define BNX2X_PREV_UNDI_MF_PORT(p) (BAR_TSTRORM_INTMEM + 0x150c + ((p) << 4))
 #define BNX2X_PREV_UNDI_MF_FUNC(f) (BAR_TSTRORM_INTMEM + 0x184c + ((f) << 4))
+
+static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
+{
+	/* UNDI marks its presence in DORQ -
+	 * it initializes CID offset for normal bell to 0x7
+	 */
+	if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
+	    MISC_REGISTERS_RESET_REG_1_RST_DORQ))
+		return false;
+
+	if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
+		BNX2X_DEV_INFO("UNDI previously loaded\n");
+		return true;
+	}
+
+	return false;
+}
+
 static bool bnx2x_prev_unload_undi_fw_supports_mf(struct bnx2x *bp)
 {
 	u8 major, minor, version;
@@ -10302,6 +10320,10 @@ static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
 
 	BNX2X_DEV_INFO("Path is unmarked\n");
 
+	/* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
+	if (bnx2x_prev_is_after_undi(bp))
+		goto out;
+
 	/* If function has FLR capabilities, and existing FW version matches
 	 * the one required, then FLR will be sufficient to clean any residue
 	 * left by previous driver
@@ -10322,6 +10344,7 @@ static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
 
 	BNX2X_DEV_INFO("Could not FLR\n");
 
+out:
 	/* Close the MCP request, return failure*/
 	rc = bnx2x_prev_mcp_done(bp);
 	if (!rc)
@@ -10360,19 +10383,13 @@ static int bnx2x_prev_unload_common(struct bnx2x *bp)
 		/* close LLH filters towards the BRB */
 		bnx2x_set_rx_filter(&bp->link_params, 0);
 
-		/* Check if the UNDI driver was previously loaded
-		 * UNDI driver initializes CID offset for normal bell to 0x7
-		 */
-		if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
-			tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
-			if (tmp_reg == 0x7) {
-				BNX2X_DEV_INFO("UNDI previously loaded\n");
-				prev_undi = true;
-				/* clear the UNDI indication */
-				REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
-				/* clear possible idle check errors */
-				REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
-			}
+		/* Check if the UNDI driver was previously loaded */
+		if (bnx2x_prev_is_after_undi(bp)) {
+			prev_undi = true;
+			/* clear the UNDI indication */
+			REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
+			/* clear possible idle check errors */
+			REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
 		}
 		if (!CHIP_IS_E1x(bp))
 			/* block FW from writing to host */
-- 
1.8.1.4

[PATCH net 4/4] bnx2x: Enlarge the dorq threshold for VFs

[Yuval Mintz]

From: Ariel Elior <ariel.elior@qlogic.com>

A malicious VF might try to starve the other VFs & PF by creating
contineous doorbell floods. In order to negate this, HW has a threshold of
doorbells per client, which will stop the client doorbells from arriving
if crossed.

The threshold currently configured for VFs is too low - under extreme traffic
scenarios, it's possible for a VF to reach the threshold and thus for its
fastpath to stop working.

Signed-off-by: Ariel Elior <ariel.elior@qlogic.com>
Signed-off-by: Yuval Mintz <yuval.mintz@qlogic.com>
---
 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
index a93c7af..f7edb42 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
@@ -1071,8 +1071,10 @@ void bnx2x_iov_init_dq(struct bnx2x *bp)
 	REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0);
 	REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff);
 
-	/* set the VF doorbell threshold */
-	REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 4);
+	/* set the VF doorbell threshold. This threshold represents the amount
+	 * of doorbells allowed in the main DORQ fifo for a specific VF.
+	 */
+	REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 64);
 }
 
 void bnx2x_iov_init_dmae(struct bnx2x *bp)
-- 
1.8.1.4

[PATCH net 0/4] bnx2x: Bug fixes patch series

[Yuval Mintz]

Hi Dave,

This series contains several fixes, relating either to SR-IOV flows
or to critical sections protected by the rtnl lock.

Please consider applying these patches to `net'.

Thanks,
Yuval Mintz

Re: [PATCH net 0/4] bnx2x: Bug fixes patch series

[David Miller]

From: "Yuval Mintz" <yuvalmin@broadcom.com>
Date: Sun, 17 Nov 2013 08:59:25 +0200

> This series contains several fixes, relating either to SR-IOV flows
> or to critical sections protected by the rtnl lock.
> 
> Please consider applying these patches to `net'.

Series applied, thanks Yuval.