From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chunhao Lin Subject: [PATCH net-next v2 3/8] r8169:correct the way of setting rtl8168dp pcie ephy parameters Date: Fri, 9 Jan 2015 23:26:01 +0800 Message-ID: <1420817166-9868-4-git-send-email-hau@realtek.com> References: <1420817166-9868-1-git-send-email-hau@realtek.com> Mime-Version: 1.0 Content-Type: text/plain Cc: , , Chunhao Lin To: Return-path: In-Reply-To: <1420817166-9868-1-git-send-email-hau@realtek.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: netdev.vger.kernel.org The original way is wrong, it always sets the ephy reg 0x03. Correct it in this patch. Signed-off-by: Chunhao Lin --- drivers/net/ethernet/realtek/r8169.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c index 991bda5..540a6b8 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169.c @@ -5731,11 +5731,10 @@ static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) void __iomem *ioaddr = tp->mmio_addr; struct pci_dev *pdev = tp->pci_dev; static const struct ephy_info e_info_8168d_4[] = { - { 0x0b, ~0, 0x48 }, - { 0x19, 0x20, 0x50 }, - { 0x0c, ~0, 0x20 } + { 0x0b, 0x0000, 0x0048 }, + { 0x19, 0x0020, 0x0050 }, + { 0x0c, 0x0100, 0x0020 } }; - int i; rtl_csi_access_enable_1(tp); @@ -5744,13 +5743,7 @@ static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) RTL_W8(MaxTxPacketSize, TxPacketMax); - for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { - const struct ephy_info *e = e_info_8168d_4 + i; - u16 w; - - w = rtl_ephy_read(tp, e->offset); - rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits); - } + rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4)); rtl_enable_clock_request(pdev); } -- 1.9.1