[PATCH 1/2] net/phy: micrel: Comment MMD address of extended registers

[PATCH 1/2] net/phy: micrel: Comment MMD address of extended registers

[Jaeden Amero]

There are some defines for a few pad skew related extended registers.
Specify for which MMD Address (dev_addr) they are for.

Signed-off-by: Jaeden Amero <jaeden.amero@ni.com>
---
 drivers/net/phy/micrel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index ebdc357..41a2e02 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -365,6 +365,7 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG		60
 
 /* Extended registers */
+/* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW	4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW	5
 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW	6
-- 
2.1.4

[PATCH 2/2] net/phy: micrel: Center FLP timing at 16ms

[Jaeden Amero]

Link failures have been observed when using the KSZ9031 with HP 1810-8G
and HP 1910-8G network switches. Center the FLP timing at 16ms to help
avoid intermittent link failures.

From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
"Auto-Negotiation Timing":
	The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
	transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
	Standard specifies this timing to be 16ms +/-8ms. Some PHY link
	partners need to receive the FLP with 16ms centered timing;
	otherwise, there can be intermittent link failures and long
	link-up times.

	After KSZ9031[RNX or MNX] power-up/reset, program the following
	register sequence to set the FLP timing to 16ms

	Write Register Dh = 0x0000 // Set up register address for MMD – Device Address 0h
	Write Register Eh = 0x0004 // Select Register 4h of MMD – Device Address 0h
	Write Register Dh = 0x4000 // Select register data for MMD – Device Address 0h, Register 4h
	Write Register Eh = 0x0006 // Write value 0x0006 to MMD – Device Address 0h, Register 4h
	Write Register Dh = 0x0000 // Set up register address for MMD – Device Address 0h
	Write Register Eh = 0x0003 // Select Register 3h of MMD – Device Address 0h
	Write Register Dh = 0x4000 // Select register data for MMD – Device Address 0h, Register 3h
	Write Register Eh = 0x1A80 // Write value 0x1A80 to MMD – Device Address 0h, Register 3h
	Write Register 0h, Bit [9] = 1 // Restart Auto-Negotiation

Signed-off-by: Jaeden Amero <jaeden.amero@ni.com>
---
 drivers/net/phy/micrel.c | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 41a2e02..47eb5df 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -365,6 +365,10 @@ static int ksz9021_config_init(struct phy_device *phydev)
 #define KSZ9031_PS_TO_REG		60
 
 /* Extended registers */
+/* MMD Address 0x0 */
+#define MII_KSZ9031RN_FLP_BURST_TX_LO	3
+#define MII_KSZ9031RN_FLP_BURST_TX_HI	4
+
 /* MMD Address 0x2 */
 #define MII_KSZ9031RN_CONTROL_PAD_SKEW	4
 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW	5
@@ -426,8 +430,25 @@ static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 	return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 }
 
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+	int result = 0;
+
+	/* Center KSZ9031RNX FLP timing at 16ms. */
+	result = ksz9031_extended_write(phydev, OP_DATA, 0,
+					MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
+	result = ksz9031_extended_write(phydev, OP_DATA, 0,
+					MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
+
+	if (result)
+		return result;
+
+	return genphy_restart_aneg(phydev);
+}
+
 static int ksz9031_config_init(struct phy_device *phydev)
 {
+	int result;
 	struct device *dev = &phydev->dev;
 	struct device_node *of_node = dev->of_node;
 	char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
@@ -461,7 +482,10 @@ static int ksz9031_config_init(struct phy_device *phydev)
 				MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
 				tx_data_skews, 4);
 	}
-	return 0;
+
+	result = ksz9031_center_flp_timing(phydev);
+
+	return result;
 }
 
 #define KSZ8873MLL_GLOBAL_CONTROL_4	0x06
-- 
2.1.4

Re: [PATCH 2/2] net/phy: micrel: Center FLP timing at 16ms

[Jaeden Amero]

Please disregard this patch set. I'll post a second version.

Cheers,
Jaeden