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* [PATCH net-next 1/2] net/mlx4_core: Capping number of requested MSIXs to MAX_MSIX
@ 2015-08-27 19:43 clsoto
  2015-08-27 19:43 ` [PATCH net-next 2/2] net/mlx4_core: Fix unintialized variable used in error path clsoto
  2015-08-27 23:40 ` [PATCH net-next 1/2] net/mlx4_core: Capping number of requested MSIXs to MAX_MSIX David Miller
  0 siblings, 2 replies; 4+ messages in thread
From: clsoto @ 2015-08-27 19:43 UTC (permalink / raw)
  To: davem; +Cc: netdev, ogerlitz, brking, Carol L Soto, Matan Barak

From: Carol L Soto <clsoto@linux.vnet.ibm.com>

We currently manage IRQs in pool_bm which is a bit field
of MAX_MSIX bits. Thus, allocating more than MAX_MSIX
interrupts can't be managed in pool_bm.
Fixing this by capping number of requested MSIXs to
MAX_MSIX.

Signed-off-by: Matan Barak <matanb@mellanox.com>
Signed-off-by: Carol L Soto <clsoto@linux.vnet.ibm.com>
---
 drivers/net/ethernet/mellanox/mlx4/main.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlx4/main.c b/drivers/net/ethernet/mellanox/mlx4/main.c
index 121c579..006757f 100644
--- a/drivers/net/ethernet/mellanox/mlx4/main.c
+++ b/drivers/net/ethernet/mellanox/mlx4/main.c
@@ -2669,9 +2669,14 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev)
 
 	if (msi_x) {
 		int nreq = dev->caps.num_ports * num_online_cpus() + 1;
+		bool shared_ports = false;
 
 		nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
 			     nreq);
+		if (nreq > MAX_MSIX) {
+			nreq = MAX_MSIX;
+			shared_ports = true;
+		}
 
 		entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
 		if (!entries)
@@ -2694,6 +2699,9 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev)
 		bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
 			    dev->caps.num_ports);
 
+		if (MLX4_IS_LEGACY_EQ_MODE(dev->caps))
+			shared_ports = true;
+
 		for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
 			if (i == MLX4_EQ_ASYNC)
 				continue;
@@ -2701,7 +2709,7 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev)
 			priv->eq_table.eq[i].irq =
 				entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
 
-			if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
+			if (shared_ports) {
 				bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
 					    dev->caps.num_ports);
 				/* We don't set affinity hint when there
-- 
1.8.3.1

^ permalink raw reply related	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2015-08-27 23:40 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-08-27 19:43 [PATCH net-next 1/2] net/mlx4_core: Capping number of requested MSIXs to MAX_MSIX clsoto
2015-08-27 19:43 ` [PATCH net-next 2/2] net/mlx4_core: Fix unintialized variable used in error path clsoto
2015-08-27 23:40   ` David Miller
2015-08-27 23:40 ` [PATCH net-next 1/2] net/mlx4_core: Capping number of requested MSIXs to MAX_MSIX David Miller

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