* [PATCH] ARM: net: bpf: fix zero right shift
@ 2016-01-05 17:34 Rabin Vincent
2016-01-05 17:50 ` Alexei Starovoitov
2016-01-06 6:32 ` David Miller
0 siblings, 2 replies; 3+ messages in thread
From: Rabin Vincent @ 2016-01-05 17:34 UTC (permalink / raw)
To: davem; +Cc: netdev, linux, linux-arm-kernel, Rabin Vincent
The LSR instruction cannot be used to perform a zero right shift since a
0 as the immediate value (imm5) in the LSR instruction encoding means
that a shift of 32 is perfomed. See DecodeIMMShift() in the ARM ARM.
Make the JIT skip generation of the LSR if a zero-shift is requested.
This was found using american fuzzy lop.
Signed-off-by: Rabin Vincent <rabin@rab.in>
---
arch/arm/net/bpf_jit_32.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index e153eb065fe4..93d0b6d0b63e 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -756,7 +756,8 @@ load_ind:
case BPF_ALU | BPF_RSH | BPF_K:
if (unlikely(k > 31))
return -1;
- emit(ARM_LSR_I(r_A, r_A, k), ctx);
+ if (k)
+ emit(ARM_LSR_I(r_A, r_A, k), ctx);
break;
case BPF_ALU | BPF_RSH | BPF_X:
update_on_xread(ctx);
--
2.6.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] ARM: net: bpf: fix zero right shift
2016-01-05 17:34 [PATCH] ARM: net: bpf: fix zero right shift Rabin Vincent
@ 2016-01-05 17:50 ` Alexei Starovoitov
2016-01-06 6:32 ` David Miller
1 sibling, 0 replies; 3+ messages in thread
From: Alexei Starovoitov @ 2016-01-05 17:50 UTC (permalink / raw)
To: Rabin Vincent; +Cc: davem, netdev, linux, linux-arm-kernel
On Tue, Jan 05, 2016 at 06:34:04PM +0100, Rabin Vincent wrote:
> The LSR instruction cannot be used to perform a zero right shift since a
> 0 as the immediate value (imm5) in the LSR instruction encoding means
> that a shift of 32 is perfomed. See DecodeIMMShift() in the ARM ARM.
>
> Make the JIT skip generation of the LSR if a zero-shift is requested.
>
> This was found using american fuzzy lop.
>
> Signed-off-by: Rabin Vincent <rabin@rab.in>
Looks good as a fix for classic jit. For eBPF we would want to check
this in verifier.
Acked-by: Alexei Starovoitov <ast@kernel.org>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] ARM: net: bpf: fix zero right shift
2016-01-05 17:34 [PATCH] ARM: net: bpf: fix zero right shift Rabin Vincent
2016-01-05 17:50 ` Alexei Starovoitov
@ 2016-01-06 6:32 ` David Miller
1 sibling, 0 replies; 3+ messages in thread
From: David Miller @ 2016-01-06 6:32 UTC (permalink / raw)
To: rabin; +Cc: netdev, linux, linux-arm-kernel
From: Rabin Vincent <rabin@rab.in>
Date: Tue, 5 Jan 2016 18:34:04 +0100
> The LSR instruction cannot be used to perform a zero right shift since a
> 0 as the immediate value (imm5) in the LSR instruction encoding means
> that a shift of 32 is perfomed. See DecodeIMMShift() in the ARM ARM.
>
> Make the JIT skip generation of the LSR if a zero-shift is requested.
>
> This was found using american fuzzy lop.
>
> Signed-off-by: Rabin Vincent <rabin@rab.in>
Applied, thanks.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2016-01-05 17:34 [PATCH] ARM: net: bpf: fix zero right shift Rabin Vincent
2016-01-05 17:50 ` Alexei Starovoitov
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