From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DC6DC169C4 for ; Wed, 6 Feb 2019 22:29:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1B9F1218B0 for ; Wed, 6 Feb 2019 22:29:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TXxHTVQi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726171AbfBFW3c (ORCPT ); Wed, 6 Feb 2019 17:29:32 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:40172 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725928AbfBFW3b (ORCPT ); Wed, 6 Feb 2019 17:29:31 -0500 Received: by mail-pl1-f196.google.com with SMTP id u18so3791607plq.7 for ; Wed, 06 Feb 2019 14:29:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:cc:references:from:openpgp:autocrypt:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=ttStf4p04gLYgH0nCKP5Jm4j7fwzfW6KQwfdjvHim4M=; b=TXxHTVQiOfTuvvETtpicktfLHWqVC0wo4X0uCnAlOcjb/fOvmSYIQTHok2Tkvv7DFe yoIrfRbz8OOXdM/3GtWsBVwzZ4dh9S/Uvq9B/Ky7t/TXQt06tW0bQ1QrAUuzgKG4kYUc winS38SadEeiiQ1DMb+0aaywdVvrPXlAXQ6whj/aKIAh9kY7liS0yJIUCw61QAdbTlD3 VVJzyJxurFTs3LTM5D4+hnwcNyQmUfSJ5Y/Y9HppRGPjnjDV+GdmSiez+KUsQ1YmF2ud UgHq5gXCGUTG+lwF4CBmAPr3aLVyiGCX1C22WEbW5ZQ4rWM54Be4b6L2KwaFzYdgtfph dIbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:openpgp:autocrypt :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=ttStf4p04gLYgH0nCKP5Jm4j7fwzfW6KQwfdjvHim4M=; b=kUrKYQWFE311x729HeML+yx092oKODhOvHfWYiGURgs8p4dWLE0Txma/Ca6hKVCFHn Mz4k6MqOMSnIu/XouRA3pHFSvC0VSWAA3RBSwmRLJAZT/h18UHoxIfnLiUnhf0XT+81C /5syG2+BvrkyC/BLcAOvp2HIM79NcYOwANL65g4sBBRjQm3wzmceH1qFLDhycGxR0Ljd 0DrLN/ZWqr8NzqD+n4IdKgaTvDkz7YnhZIAdjf6ey/1R7EMRmb03oxx1DRKUJ0ZvAkuW +JVC7JYfKGQQ6p9jh1m6RU+3H8TYv8GMgAg4foypUtsmFrmdmOazF51H/+z85vIXD/S6 h/AA== X-Gm-Message-State: AHQUAubVwQthTAivLTTzTu7uwNnc/9RiKeuWv26ELSkg0VuTil8kHOKy sQg3j0hawa7aPnvEfjS4mCM= X-Google-Smtp-Source: AHgI3IZ+0qdY4y72aDuEgqL2VHVNEocO+7a03TexULs704dlGNNv1zIp0hzvs5zboN0BKUy+ORqCtw== X-Received: by 2002:a17:902:8c8a:: with SMTP id t10mr10965352plo.39.1549492170673; Wed, 06 Feb 2019 14:29:30 -0800 (PST) Received: from [10.67.48.231] ([192.19.223.250]) by smtp.googlemail.com with ESMTPSA id d25sm10500528pfe.40.2019.02.06.14.29.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Feb 2019 14:29:29 -0800 (PST) Subject: Re: [PATCH v1] net: dsa: qca8k: implement DT-based ports <-> phy translation To: Christian Lamparter Cc: Andrew Lunn , netdev@vger.kernel.org, Vivien Didelot References: <20190204213555.26054-1-chunkeey@gmail.com> <2061891.QOleSDBFsG@debian64> <699dfb8a-11d4-b27a-e762-ff4fdff1a3d7@gmail.com> <3897570.9hORRSCDvi@debian64> From: Florian Fainelli Openpgp: preference=signencrypt Autocrypt: addr=f.fainelli@gmail.com; prefer-encrypt=mutual; keydata= mQGiBEjPuBIRBACW9MxSJU9fvEOCTnRNqG/13rAGsj+vJqontvoDSNxRgmafP8d3nesnqPyR xGlkaOSDuu09rxuW+69Y2f1TzjFuGpBk4ysWOR85O2Nx8AJ6fYGCoeTbovrNlGT1M9obSFGQ X3IzRnWoqlfudjTO5TKoqkbOgpYqIo5n1QbEjCCwCwCg3DOH/4ug2AUUlcIT9/l3pGvoRJ0E AICDzi3l7pmC5IWn2n1mvP5247urtHFs/uusE827DDj3K8Upn2vYiOFMBhGsxAk6YKV6IP0d ZdWX6fqkJJlu9cSDvWtO1hXeHIfQIE/xcqvlRH783KrihLcsmnBqOiS6rJDO2x1eAgC8meAX SAgsrBhcgGl2Rl5gh/jkeA5ykwbxA/9u1eEuL70Qzt5APJmqVXR+kWvrqdBVPoUNy/tQ8mYc nzJJ63ng3tHhnwHXZOu8hL4nqwlYHRa9eeglXYhBqja4ZvIvCEqSmEukfivk+DlIgVoOAJbh qIWgvr3SIEuR6ayY3f5j0f2ejUMYlYYnKdiHXFlF9uXm1ELrb0YX4GMHz7QnRmxvcmlhbiBG YWluZWxsaSA8Zi5mYWluZWxsaUBnbWFpbC5jb20+iGYEExECACYCGyMGCwkIBwMCBBUCCAME FgIDAQIeAQIXgAUCVF/S8QUJHlwd3wAKCRBhV5kVtWN2DvCVAJ4u4/bPF4P3jxb4qEY8I2gS 6hG0gACffNWlqJ2T4wSSn+3o7CCZNd7SLSC5BA0ESM+4EhAQAL/o09boR9D3Vk1Tt7+gpYr3 WQ6hgYVON905q2ndEoA2J0dQxJNRw3snabHDDzQBAcqOvdi7YidfBVdKi0wxHhSuRBfuOppu pdXkb7zxuPQuSveCLqqZWRQ+Cc2QgF7SBqgznbe6Ngout5qXY5Dcagk9LqFNGhJQzUGHAsIs hap1f0B1PoUyUNeEInV98D8Xd/edM3mhO9nRpUXRK9Bvt4iEZUXGuVtZLT52nK6Wv2EZ1TiT OiqZlf1P+vxYLBx9eKmabPdm3yjalhY8yr1S1vL0gSA/C6W1o/TowdieF1rWN/MYHlkpyj9c Rpc281gAO0AP3V1G00YzBEdYyi0gaJbCEQnq8Vz1vDXFxHzyhgGz7umBsVKmYwZgA8DrrB0M oaP35wuGR3RJcaG30AnJpEDkBYHznI2apxdcuTPOHZyEilIRrBGzDwGtAhldzlBoBwE3Z3MY 31TOpACu1ZpNOMysZ6xiE35pWkwc0KYm4hJA5GFfmWSN6DniimW3pmdDIiw4Ifcx8b3mFrRO BbDIW13E51j9RjbO/nAaK9ndZ5LRO1B/8Fwat7bLzmsCiEXOJY7NNpIEpkoNoEUfCcZwmLrU +eOTPzaF6drw6ayewEi5yzPg3TAT6FV3oBsNg3xlwU0gPK3v6gYPX5w9+ovPZ1/qqNfOrbsE FRuiSVsZQ5s3AAMFD/9XjlnnVDh9GX/r/6hjmr4U9tEsM+VQXaVXqZuHKaSmojOLUCP/YVQo 7IiYaNssCS4FCPe4yrL4FJJfJAsbeyDykMN7wAnBcOkbZ9BPJPNCbqU6dowLOiy8AuTYQ48m vIyQ4Ijnb6GTrtxIUDQeOBNuQC/gyyx3nbL/lVlHbxr4tb6YkhkO6shjXhQh7nQb33FjGO4P WU11Nr9i/qoV8QCo12MQEo244RRA6VMud06y/E449rWZFSTwGqb0FS0seTcYNvxt8PB2izX+ HZA8SL54j479ubxhfuoTu5nXdtFYFj5Lj5x34LKPx7MpgAmj0H7SDhpFWF2FzcC1bjiW9mjW HaKaX23Awt97AqQZXegbfkJwX2Y53ufq8Np3e1542lh3/mpiGSilCsaTahEGrHK+lIusl6mz Joil+u3k01ofvJMK0ZdzGUZ/aPMZ16LofjFA+MNxWrZFrkYmiGdv+LG45zSlZyIvzSiG2lKy kuVag+IijCIom78P9jRtB1q1Q5lwZp2TLAJlz92DmFwBg1hyFzwDADjZ2nrDxKUiybXIgZp9 aU2d++ptEGCVJOfEW4qpWCCLPbOT7XBr+g/4H3qWbs3j/cDDq7LuVYIe+wchy/iXEJaQVeTC y5arMQorqTFWlEOgRA8OP47L9knl9i4xuR0euV6DChDrguup2aJVU4hPBBgRAgAPAhsMBQJU X9LxBQkeXB3fAAoJEGFXmRW1Y3YOj4UAn3nrFLPZekMeqX5aD/aq/dsbXSfyAKC45Go0YyxV HGuUuzv+GKZ6nsysJ7kCDQRXG8fwARAA6q/pqBi5PjHcOAUgk2/2LR5LjjesK50bCaD4JuNc YDhFR7Vs108diBtsho3w8WRd9viOqDrhLJTroVckkk74OY8r+3t1E0Dd4wHWHQZsAeUvOwDM PQMqTUBFuMi6ydzTZpFA2wBR9x6ofl8Ax+zaGBcFrRlQnhsuXLnM1uuvS39+pmzIjasZBP2H UPk5ifigXcpelKmj6iskP3c8QN6x6GjUSmYx+xUfs/GNVSU1XOZn61wgPDbgINJd/THGdqiO iJxCLuTMqlSsmh1+E1dSdfYkCb93R/0ZHvMKWlAx7MnaFgBfsG8FqNtZu3PCLfizyVYYjXbV WO1A23riZKqwrSJAATo5iTS65BuYxrFsFNPrf7TitM8E76BEBZk0OZBvZxMuOs6Z1qI8YKVK UrHVGFq3NbuPWCdRul9SX3VfOunr9Gv0GABnJ0ET+K7nspax0xqq7zgnM71QEaiaH17IFYGS sG34V7Wo3vyQzsk7qLf9Ajno0DhJ+VX43g8+AjxOMNVrGCt9RNXSBVpyv2AMTlWCdJ5KI6V4 KEzWM4HJm7QlNKE6RPoBxJVbSQLPd9St3h7mxLcne4l7NK9eNgNnneT7QZL8fL//s9K8Ns1W t60uQNYvbhKDG7+/yLcmJgjF74XkGvxCmTA1rW2bsUriM533nG9gAOUFQjURkwI8jvMAEQEA AYkCaAQYEQIACQUCVxvH8AIbAgIpCRBhV5kVtWN2DsFdIAQZAQIABgUCVxvH8AAKCRCH0Jac RAcHBIkHD/9nmfog7X2ZXMzL9ktT++7x+W/QBrSTCTmq8PK+69+INN1ZDOrY8uz6htfTLV9+ e2W6G8/7zIvODuHk7r+yQ585XbplgP0V5Xc8iBHdBgXbqnY5zBrcH+Q/oQ2STalEvaGHqNoD UGyLQ/fiKoLZTPMur57Fy1c9rTuKiSdMgnT0FPfWVDfpR2Ds0gpqWePlRuRGOoCln5GnREA/ 2MW2rWf+CO9kbIR+66j8b4RUJqIK3dWn9xbENh/aqxfonGTCZQ2zC4sLd25DQA4w1itPo+f5 V/SQxuhnlQkTOCdJ7b/mby/pNRz1lsLkjnXueLILj7gNjwTabZXYtL16z24qkDTI1x3g98R/ xunb3/fQwR8FY5/zRvXJq5us/nLvIvOmVwZFkwXc+AF+LSIajqQz9XbXeIP/BDjlBNXRZNdo dVuSU51ENcMcilPr2EUnqEAqeczsCGpnvRCLfVQeSZr2L9N4svNhhfPOEscYhhpHTh0VPyxI pPBNKq+byuYPMyk3nj814NKhImK0O4gTyCK9b+gZAVvQcYAXvSouCnTZeJRrNHJFTgTgu6E0 caxTGgc5zzQHeX67eMzrGomG3ZnIxmd1sAbgvJUDaD2GrYlulfwGWwWyTNbWRvMighVdPkSF 6XFgQaosWxkV0OELLy2N485YrTr2Uq64VKyxpncLh50e2RnyAJ9Za0Dx0yyp44iD1OvHtkEI M5kY0ACeNhCZJvZ5g4C2Lc9fcTHu8jxmEkI= Message-ID: <14f73250-4255-6f4e-336a-9bf289539b75@gmail.com> Date: Wed, 6 Feb 2019 14:29:18 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <3897570.9hORRSCDvi@debian64> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On 2/6/19 1:57 PM, Christian Lamparter wrote: > On Tuesday, February 5, 2019 11:29:36 PM CET Florian Fainelli wrote: >> On 2/5/19 2:12 PM, Christian Lamparter wrote: >>> On Tuesday, February 5, 2019 10:29:34 PM CET Andrew Lunn wrote: >>>>> For now, I added the DT binding update to the patch as well. >>>>> But if this is indeed the way to go, it'll get a separate patch. >>>> >>>> Hi Christian >>>> >>>> You need to be careful with the DT binding. You need to keep backwards >>>> compatible with it. An old DT blob needs to keep working. I don't >>>> think this is true with this change. >>> >>> Do you mean because of the >>> >>> - switch0@0 { >>> + switch@10 { >>> compatible = "qca,qca8337"; >>> #address-cells = <1>; >>> #size-cells = <0>; >>> >>> - reg = <0>; >>> + reg = <0x10>; >>> >>> change? >>> >>> or because I removed the phy-handles?> >>> The reg = <0x10>; will be necessary regardless. Because this >>> is really a bug in the existing binding example and if it is >>> copied it will prevent the qca8k driver from loading. >>> This is due to a resource conflict, because there will be >>> already a "phy_port1: phy@0" registered at reg = <0>; >>> So this never worked would have worked. >> >> That part is fine, it is the removal of the phy-handle properties that >> is possibly a problem, but in hindsight, I do not believe it will be a >> compatibility issue. Lack of "phy-handle" property within the core DSA >> layer means: utilize the switch's internal MDIO bus (ds->slave_mii_bus) >> instance, which you are not removing, you are just changing how the PHYs >> map to port numbers. >> > Ok, thanks. > > I think I'm almost ready for v2. I have fully addressed the compatibility > issue by forking off the qca8k_switch_ops depending on whenever a phy-handle > property on one of the ports was found or not. If there was no phy-handle the > driver adds the slave-bus accessors to the ops which tells DSA to allocate > the slave bus and allows the phys can be enumerated. If the phy-handles are > found the driver will not have the accessors and DSA will not setup a > redundant/fake bus and this prevents the second/double/duplicated discovery > and enumeration of the same PHYs again. The logic you have sounds a little too broad since it stops as soon as one port is found with a 'phy-handle' property and assumes that the parent MDIO bus from which qca8k itself is a child device, is the MDIO bus to be used. There are possibly 3 cases: 1) All ports using internal/build-in PHYs. In that case, you can either not specify a 'phy-handle' property and DSA assumes that they are part of the switch's internal MDIO bus. You can also specify a 'phy-handle' property that references the internal MDIO bus, although then we also expect qca8k to register its internal MDIO bus (ala mv88e6xxx) 2) Some ports using internal PHYs, some using external PHYs. Similar situation again, ports may, or may not specify a 'phy-handle' property, so without a 'phy-handle' property that means the port connects to an internal PHY, with a 'phy-handle' it could connect to either internal PHY or external PHY 3) All ports using external PHYs, in that case, we must have a 'phy-handle' for each port to specify where and how they connect to their external PHYs. With respect to your patch, what I would do is register QCA8k's internal MDIO bus as a proper mdio bus and use ds->slave_mii_bus as a storage for that bus, such that tell the DSA layer: look, here is the internal MDIO bus, would you ever find a port that needs to use a PHY in there. Then you can still scan each enabled port device, and for each of them, populate ds->phys_mii_mask, thus telling DSA exacly which ports are using an internal PHY because that would be the ports that do not have a 'phy-handle' property. Ports that have a 'phy-handle' property. Hope this helps and is clear, if not, I can try to cook a patch for you to try, though I don't have you hardware. Tangential, since you are working on qca8k, it would be great to give this driver some TLC and make sure that: - bridge w/ and w/o VLAN filtering enabled works - multicast snooping works etc. Cheers > > Cheers, > Christian > > Attached is a preview: > > --- > commit 96bc70b4d6e290c450b9af728d9ca0f6db877f13 > Author: Christian Lamparter > Date: Fri Feb 1 22:54:32 2019 +0100 > > net: dsa: qca8k: extend slave-bus implementations > > This patch implements accessors for the QCA8337 MDIO access > through the MDIO_MASTER register, which makes it possible to > access the PHYs on slave-bus through the switch. In cases > where the switch ports are already mapped via external > "phy-phandles", the internal mdio-bus is disabled in order to > prevent a duplicated discovery and enumeration of the same > PHYs. > > Signed-off-by: Christian Lamparter > --- > > Changes from v2: > - Make it compatible with existing configurations > > Changes from v1: > - drop DT port <-> phy mapping > - added register definitions for the MDIO control register > - implemented new slave-mdio bus accessors > - DT-binding: fix switch's PSEUDO_PHY address. It's 0x10 not 0. > > diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c > index a4b6cda38016..2f1b4b0a3507 100644 > --- a/drivers/net/dsa/qca8k.c > +++ b/drivers/net/dsa/qca8k.c > @@ -613,19 +613,61 @@ qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy) > } > > static int > -qca8k_phy_read(struct dsa_switch *ds, int phy, int regnum) > +qca8k_port_to_phy(int port) > +{ > + if (port < 1 || port > QCA8K_MDIO_MASTER_MAX_PORTS) > + return -EINVAL; > + > + return port - 1; > +} > + > +static int > +qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data) > { > struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; > + u32 val, phy; > + > + phy = qca8k_port_to_phy(port); > + if (phy < 0 || (regnum < 0 || regnum >= QCA8K_MDIO_MASTER_MAX_REG)) > + return -EINVAL; > + > + val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | > + QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | > + QCA8K_MDIO_MASTER_REG_ADDR(regnum) | > + QCA8K_MDIO_MASTER_DATA(data); > > - return mdiobus_read(priv->bus, phy, regnum); > + qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); > + > + return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, > + QCA8K_MDIO_MASTER_BUSY); > } > > + > static int > -qca8k_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val) > +qca8k_phy_read(struct dsa_switch *ds, int port, int regnum) > { > struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; > + u32 val, phy; > + > + phy = qca8k_port_to_phy(port); > + if (phy < 0 || (regnum < 0 || regnum >= QCA8K_MDIO_MASTER_MAX_REG)) > + return 0xffff; > + > + val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | > + QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | > + QCA8K_MDIO_MASTER_REG_ADDR(regnum); > + > + qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); > > - return mdiobus_write(priv->bus, phy, regnum, val); > + if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, > + QCA8K_MDIO_MASTER_BUSY)) { > + return 0xffff; > + } > + > + val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) & > + QCA8K_MDIO_MASTER_DATA_MASK); > + > + return val; > } > > static void > @@ -868,8 +910,6 @@ static const struct dsa_switch_ops qca8k_switch_ops = { > .setup = qca8k_setup, > .adjust_link = qca8k_adjust_link, > .get_strings = qca8k_get_strings, > - .phy_read = qca8k_phy_read, > - .phy_write = qca8k_phy_write, > .get_ethtool_stats = qca8k_get_ethtool_stats, > .get_sset_count = qca8k_get_sset_count, > .get_mac_eee = qca8k_get_mac_eee, > @@ -884,6 +924,38 @@ static const struct dsa_switch_ops qca8k_switch_ops = { > .port_fdb_dump = qca8k_port_fdb_dump, > }; > > +/* Special code to detect DeviceTrees that use the phy-handle > + * to map external PHYs to the ports. Only if no phy-handle is > + * detected the slave bus accessors are getting enabled. > + */ > +static int qca8k_detect_slave_bus(struct qca8k_priv *priv) > +{ > + struct device_node *ports, *port; > + bool found = false; > + > + ports = of_get_child_by_name(priv->dev->of_node, "ports"); > + if (!ports) { > + dev_err(priv->dev, "no ports child node found.\n"); > + return -EINVAL; > + } > + > + for_each_available_child_of_node(ports, port) { > + if (of_property_read_bool(port, "phy-handle")) { > + found = true; > + break; > + } > + } > + > + if (found) { > + dev_info(priv->dev, "uses external mdio-bus.\n"); > + } else { > + priv->ops.phy_read = qca8k_phy_read; > + priv->ops.phy_write = qca8k_phy_write; > + } > + > + return 0; > +} > + > static int > qca8k_sw_probe(struct mdio_device *mdiodev) > { > @@ -912,7 +984,12 @@ qca8k_sw_probe(struct mdio_device *mdiodev) > return -ENOMEM; > > priv->ds->priv = priv; > - priv->ds->ops = &qca8k_switch_ops; > + priv->ops = qca8k_switch_ops; > + if (qca8k_detect_slave_bus(priv)) > + return -EINVAL; > + > + priv->ds->ops = &priv->ops; > + > mutex_init(&priv->reg_mutex); > dev_set_drvdata(&mdiodev->dev, priv); > > diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h > index 613fe5c50236..38d06661f0a8 100644 > --- a/drivers/net/dsa/qca8k.h > +++ b/drivers/net/dsa/qca8k.h > @@ -48,6 +48,18 @@ > #define QCA8K_MIB_FLUSH BIT(24) > #define QCA8K_MIB_CPU_KEEP BIT(20) > #define QCA8K_MIB_BUSY BIT(17) > +#define QCA8K_MDIO_MASTER_CTRL 0x3c > +#define QCA8K_MDIO_MASTER_BUSY BIT(31) > +#define QCA8K_MDIO_MASTER_EN BIT(30) > +#define QCA8K_MDIO_MASTER_READ BIT(27) > +#define QCA8K_MDIO_MASTER_WRITE 0 > +#define QCA8K_MDIO_MASTER_SUP_PRE BIT(26) > +#define QCA8K_MDIO_MASTER_PHY_ADDR(x) ((x) << 21) > +#define QCA8K_MDIO_MASTER_REG_ADDR(x) ((x) << 16) > +#define QCA8K_MDIO_MASTER_DATA(x) (x) > +#define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0) > +#define QCA8K_MDIO_MASTER_MAX_PORTS 5 > +#define QCA8K_MDIO_MASTER_MAX_REG 32 > #define QCA8K_GOL_MAC_ADDR0 0x60 > #define QCA8K_GOL_MAC_ADDR1 0x64 > #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) > @@ -168,6 +180,7 @@ struct qca8k_priv { > struct dsa_switch *ds; > struct mutex reg_mutex; > struct device *dev; > + struct dsa_switch_ops ops; > }; > > struct qca8k_mib_desc { > > > > > -- Florian