* [PATCH] net: stmmac: socfgpa: Ensure emac bit set in sys manager for MII/GMII/SGMII.
@ 2017-08-18 6:55 Stephan Gatzka
2017-08-18 9:58 ` Sergei Shtylyov
0 siblings, 1 reply; 2+ messages in thread
From: Stephan Gatzka @ 2017-08-18 6:55 UTC (permalink / raw)
To: peppe.cavallaro, alexandre.torgue, netdev, linux-kernel; +Cc: Stephan Gatzka
When using MII/GMII/SGMII in the Altera SoC, the phy needs to be
wired through the FPGA. To ensure correct behavior, the appropriate
bit in the System Manager FPGA Interface Group register needs to be
set.
Signed-off-by: Stephan Gatzka <stephan.gatzka@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 17d4bba..d7c231b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -269,7 +269,10 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
ctrl |= val << reg_shift;
- if (dwmac->f2h_ptp_ref_clk) {
+ if ((dwmac->f2h_ptp_ref_clk) ||
+ (phymode == PHY_INTERFACE_MODE_MII) ||
+ (phymode == PHY_INTERFACE_MODE_GMII) ||
+ (phymode == PHY_INTERFACE_MODE_SGMII)) {
ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
&module);
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] net: stmmac: socfgpa: Ensure emac bit set in sys manager for MII/GMII/SGMII.
2017-08-18 6:55 [PATCH] net: stmmac: socfgpa: Ensure emac bit set in sys manager for MII/GMII/SGMII Stephan Gatzka
@ 2017-08-18 9:58 ` Sergei Shtylyov
0 siblings, 0 replies; 2+ messages in thread
From: Sergei Shtylyov @ 2017-08-18 9:58 UTC (permalink / raw)
To: Stephan Gatzka, peppe.cavallaro, alexandre.torgue, netdev,
linux-kernel
Hello!
On 8/18/2017 9:55 AM, Stephan Gatzka wrote:
> When using MII/GMII/SGMII in the Altera SoC, the phy needs to be
> wired through the FPGA. To ensure correct behavior, the appropriate
> bit in the System Manager FPGA Interface Group register needs to be
> set.
>
> Signed-off-by: Stephan Gatzka <stephan.gatzka@gmail.com>
> ---
> drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> index 17d4bba..d7c231b 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> @@ -269,7 +269,10 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
> ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
> ctrl |= val << reg_shift;
>
> - if (dwmac->f2h_ptp_ref_clk) {
> + if ((dwmac->f2h_ptp_ref_clk) ||
> + (phymode == PHY_INTERFACE_MODE_MII) ||
> + (phymode == PHY_INTERFACE_MODE_GMII) ||
> + (phymode == PHY_INTERFACE_MODE_SGMII)) {
Inner parens not needed at all (especially the first pair).
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2017-08-18 9:58 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-08-18 6:55 [PATCH] net: stmmac: socfgpa: Ensure emac bit set in sys manager for MII/GMII/SGMII Stephan Gatzka
2017-08-18 9:58 ` Sergei Shtylyov
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).