* [PATCH v2] net: stmmac: socfgpa: Ensure emac bit set in sys manager for MII/GMII/SGMII.
@ 2017-08-22 12:25 Stephan Gatzka
2017-08-24 3:27 ` David Miller
0 siblings, 1 reply; 2+ messages in thread
From: Stephan Gatzka @ 2017-08-22 12:25 UTC (permalink / raw)
To: peppe.cavallaro, alexandre.torgue, netdev, linux-kernel; +Cc: Stephan Gatzka
When using MII/GMII/SGMII in the Altera SoC, the phy needs to be
wired through the FPGA. To ensure correct behavior, the appropriate
bit in the System Manager FPGA Interface Group register needs to be
set.
Signed-off-by: Stephan Gatzka <stephan.gatzka@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 17d4bba..6e35957 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -269,7 +269,10 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
ctrl |= val << reg_shift;
- if (dwmac->f2h_ptp_ref_clk) {
+ if (dwmac->f2h_ptp_ref_clk ||
+ phymode == PHY_INTERFACE_MODE_MII ||
+ phymode == PHY_INTERFACE_MODE_GMII ||
+ phymode == PHY_INTERFACE_MODE_SGMII) {
ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
&module);
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v2] net: stmmac: socfgpa: Ensure emac bit set in sys manager for MII/GMII/SGMII.
2017-08-22 12:25 [PATCH v2] net: stmmac: socfgpa: Ensure emac bit set in sys manager for MII/GMII/SGMII Stephan Gatzka
@ 2017-08-24 3:27 ` David Miller
0 siblings, 0 replies; 2+ messages in thread
From: David Miller @ 2017-08-24 3:27 UTC (permalink / raw)
To: stephan.gatzka; +Cc: peppe.cavallaro, alexandre.torgue, netdev, linux-kernel
From: Stephan Gatzka <stephan.gatzka@gmail.com>
Date: Tue, 22 Aug 2017 14:25:07 +0200
> When using MII/GMII/SGMII in the Altera SoC, the phy needs to be
> wired through the FPGA. To ensure correct behavior, the appropriate
> bit in the System Manager FPGA Interface Group register needs to be
> set.
>
> Signed-off-by: Stephan Gatzka <stephan.gatzka@gmail.com>
Applied, thanks.
^ permalink raw reply [flat|nested] 2+ messages in thread
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