From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerome Brunet Subject: Re: [PATCH] net: phy: realtek: fix RTL8211F interrupt mode Date: Sun, 12 Nov 2017 19:36:48 +0100 Message-ID: <1510511808.3550.182.camel@baylibre.com> References: <66991733-9d1a-dbd2-9857-bba1ffca1cf8@gmail.com> <20171112182521.GH30830@lunn.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Cc: "David S. Miller" , Florian Fainelli , "netdev@vger.kernel.org" , "open list:ARM/Amlogic Meson..." , Shengzhou Liu To: Andrew Lunn , Heiner Kallweit Return-path: Received: from mail-wr0-f170.google.com ([209.85.128.170]:53929 "EHLO mail-wr0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750802AbdKLSgv (ORCPT ); Sun, 12 Nov 2017 13:36:51 -0500 Received: by mail-wr0-f170.google.com with SMTP id u40so12557597wrf.10 for ; Sun, 12 Nov 2017 10:36:51 -0800 (PST) In-Reply-To: <20171112182521.GH30830@lunn.ch> Sender: netdev-owner@vger.kernel.org List-ID: On Sun, 2017-11-12 at 19:25 +0100, Andrew Lunn wrote: > On Sun, Nov 12, 2017 at 04:16:04PM +0100, Heiner Kallweit wrote: > > After commit b94d22d94ad22 "ARM64: dts: meson-gx: add external PHY > > interrupt on some platforms" ethernet stopped working on my Odroid-C2 > > which has a RTL8211F phy. > > Hi Jerome > > Please could you test this. I Just want to be sure we don't introduce > a regression by breaking the boards you tested on. Sure I'll try it tomorrow. When I tested this, I was more focused on the SoC side of it (the interrupt controller itself) and whether the interrupt worked or not. The board (p200) I tested on used a micrel PHY and worked well ... I did not really expect that a problem would come from the phy side. This was clearly a mistake. > > Thanks > Andrew