From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerome Brunet Subject: Re: [PATCH] net: phy: realtek: fix RTL8211F interrupt mode Date: Mon, 13 Nov 2017 17:36:02 +0100 Message-ID: <1510590962.3607.1.camel@baylibre.com> References: <66991733-9d1a-dbd2-9857-bba1ffca1cf8@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Cc: "netdev@vger.kernel.org" , "open list:ARM/Amlogic Meson..." , Shengzhou Liu To: Heiner Kallweit , "David S. Miller" , Andrew Lunn , Florian Fainelli Return-path: Received: from mail-wr0-f195.google.com ([209.85.128.195]:57298 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753664AbdKMQgF (ORCPT ); Mon, 13 Nov 2017 11:36:05 -0500 Received: by mail-wr0-f195.google.com with SMTP id q66so14938512wrb.13 for ; Mon, 13 Nov 2017 08:36:04 -0800 (PST) In-Reply-To: <66991733-9d1a-dbd2-9857-bba1ffca1cf8@gmail.com> Sender: netdev-owner@vger.kernel.org List-ID: On Sun, 2017-11-12 at 16:16 +0100, Heiner Kallweit wrote: > After commit b94d22d94ad22 "ARM64: dts: meson-gx: add external PHY > interrupt on some platforms" ethernet stopped working on my Odroid-C2 > which has a RTL8211F phy. > > It turned out that no interrupts were triggered. Further analysis > showed the register INER can't be altered on page 0. > Because register INSR needs to be accessed via page 0xa43 I assumed > that register INER needs to be accessed via some page too. > Some brute force check resulted in page 0xa42 being the right one. > > With this patch the phy is working properly in interrupt mode. > > Signed-off-by: Heiner Kallweit Tested-by: Jerome Brunet