[PATCH 1/1] phy: Add 2.5G SGMII interface mode

[PATCH 1/1] phy: Add 2.5G SGMII interface mode

[Bhaskar Upadhaya]

Add 2.5G SGMII interface mode(PHY_INTERFACE_MODE_2500SGMII)
in existing phy_interface list.As auto-negotiation is not
supported for 2.5G SGMII, we need to add a new type
PHY_INTERFACE_MODE_2500SGMII to differentiate
SGMII-1G and SGMII-2.5G with different setting for
auto-negotiation.

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 include/linux/phy.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/linux/phy.h b/include/linux/phy.h
index dc82a07..158a5a5 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -87,6 +87,7 @@
 	PHY_INTERFACE_MODE_XAUI,
 	/* 10GBASE-KR, XFI, SFI - single lane 10G Serdes */
 	PHY_INTERFACE_MODE_10GKR,
+	PHY_INTERFACE_MODE_2500SGMII,
 	PHY_INTERFACE_MODE_MAX,
 } phy_interface_t;
 
@@ -159,6 +160,8 @@ static inline const char *phy_modes(phy_interface_t interface)
 		return "xaui";
 	case PHY_INTERFACE_MODE_10GKR:
 		return "10gbase-kr";
+	case PHY_INTERFACE_MODE_2500SGMII:
+		return "sgmii-2500";
 	default:
 		return "unknown";
 	}
-- 
1.9.1

Re: [PATCH 1/1] phy: Add 2.5G SGMII interface mode

[Andrew Lunn]

On Thu, Nov 30, 2017 at 10:00:35AM +0530, Bhaskar Upadhaya wrote:
> Add 2.5G SGMII interface mode(PHY_INTERFACE_MODE_2500SGMII)
> in existing phy_interface list.As auto-negotiation is not
> supported for 2.5G SGMII

Hi Bhaskar

I've been thinking about this some more...

Is auto negotiation not supported in 2.5G SGMII in general, or just in
the system you are using? Is it the PHY or the MAC which does not
support it. Are we going to get into trouble if we find an 2.5G SGMII
link which does negotiate?

My understanding is that one of the main differences between SGMII and
1000BASE-X is the negotiation.

	   Andrew

RE: [PATCH 1/1] phy: Add 2.5G SGMII interface mode

[Bhaskar Upadhaya]

Hi Andrew,
	Please find answer in lined.
Regards
--Bhaskar
	

-----Original Message-----
From: Andrew Lunn [mailto:andrew@lunn.ch] 
Sent: Thursday, November 30, 2017 9:21 PM
To: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
Cc: netdev@vger.kernel.org; davem@davemloft.net; linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/1] phy: Add 2.5G SGMII interface mode

On Thu, Nov 30, 2017 at 10:00:35AM +0530, Bhaskar Upadhaya wrote:
> Add 2.5G SGMII interface mode(PHY_INTERFACE_MODE_2500SGMII)
> in existing phy_interface list.As auto-negotiation is not supported 
> for 2.5G SGMII

Hi Bhaskar

I've been thinking about this some more...

Is auto negotiation not supported in 2.5G SGMII in general, or just in the system you are using? Is it the PHY or the MAC which does not support it.
[bhaskar] 2.5G in general needs to operate with auto negotiation in disabled mode. Its 2.5G requirement and not specific to our system.
 Are we going to get into trouble if we find an 2.5G SGMII link which does negotiate?

My understanding is that one of the main differences between SGMII and 1000BASE-X is the negotiation.
[Bhaskar] which of SGMII and 1000BASE-X support negotiation ?

	   Andrew

Re: [PATCH 1/1] phy: Add 2.5G SGMII interface mode

[Russell King - ARM Linux]

On Thu, Nov 30, 2017 at 04:50:50PM +0100, Andrew Lunn wrote:
> On Thu, Nov 30, 2017 at 10:00:35AM +0530, Bhaskar Upadhaya wrote:
> > Add 2.5G SGMII interface mode(PHY_INTERFACE_MODE_2500SGMII)
> > in existing phy_interface list.As auto-negotiation is not
> > supported for 2.5G SGMII
> 
> Hi Bhaskar
> 
> I've been thinking about this some more...
> 
> Is auto negotiation not supported in 2.5G SGMII in general, or just in
> the system you are using? Is it the PHY or the MAC which does not
> support it. Are we going to get into trouble if we find an 2.5G SGMII
> link which does negotiate?

I've been doing some research on this 2.5G SGMII "thing", and what
I've found so far (from Xilinx, I haven't been able to look through
anything else yet) is that at least Xilinx do the same thing.

There's a Xilinx document (pg047-gig-eth-pcs-pma.pdf) which says
throughout that the speed bits are not applicable for 2.5G SGMII.

Speeds > 1G appear to be defined only for full duplex (since the
latency through the PHY is too great for CDMA half-duplex to work.)
So, the duplex bits in SGMII would be meaningless for >1G.  Many
MACs, incidentally, do not support half-duplex at 1G speeds either.

That just leaves pause mode in the SGMII word.

> My understanding is that one of the main differences between SGMII and
> 1000BASE-X is the negotiation.

True.  1000BASE-X is an 802.3 standard, with the configuration word
defined by IEEE.  SGMII is derived from that by Cisco, but with the
configuration word replaced by a system whereby the PHY can inform
the MAC about the results of negotiation.

SGMII has a handshake so the PHY knows that the MAC has configured
itself, and some PHYs will not pass data until that handshake has
completed.

I suspect for 2.5G SGMII, I would expect that the handshake also has
to complete, so the PHY knows that the pause modes have been properly
received by the MAC.

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
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Re: [PATCH 1/1] phy: Add 2.5G SGMII interface mode

[David Miller]

From: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
Date: Thu, 30 Nov 2017 17:16:48 +0000

> Hi Andrew,
> 	Please find answer in lined.
...
> Is auto negotiation not supported in 2.5G SGMII in general, or just in the system you are using? Is it the PHY or the MAC which does not support it.
> [bhaskar] 2.5G in general needs to operate with auto negotiation in disabled mode. Its 2.5G requirement and not specific to our system.
>  Are we going to get into trouble if we find an 2.5G SGMII link which does negotiate?

This is completely unreadable.  Please do not respond to quoted
material this way, you are making more work for the people trying to
help you.

Proper quoting looks like this:

====================
> Quoted material.
> More quoted material.

Things you are saying in response.
====================

Thank you.

Re: [PATCH 1/1] phy: Add 2.5G SGMII interface mode

[Andrew Lunn]

> [bhaskar] 2.5G in general needs to operate with auto negotiation in
> disabled mode. Its 2.5G requirement and not specific to our system.

> My understanding is that one of the main differences between SGMII and 1000BASE-X is the negotiation.
> [Bhaskar] which of SGMII and 1000BASE-X support negotiation ?

SGMII supports passing auto-negotiation results from the PHY to the
MAC. 1000BASE-X does not.

SGMII supports the PHY running at 10, 100, and 1000 Mbps. But to
support this, the MAC needs to replicate the bits 100, or 10 times
when the PHY is running in 10 or 100Mbps mode.

So with your 2.5G SGMII, you need to replicate the bits 250, 25, or
2.5 times if they PHY is running at lower speeds. This last one is
interesting.

	Andrew

Re: [PATCH 1/1] phy: Add 2.5G SGMII interface mode

[Russell King - ARM Linux]

On Thu, Nov 30, 2017 at 06:41:27PM +0100, Andrew Lunn wrote:
> SGMII supports passing auto-negotiation results from the PHY to the
> MAC. 1000BASE-X does not.
> 
> SGMII supports the PHY running at 10, 100, and 1000 Mbps. But to
> support this, the MAC needs to replicate the bits 100, or 10 times
> when the PHY is running in 10 or 100Mbps mode.
> 
> So with your 2.5G SGMII, you need to replicate the bits 250, 25, or
> 2.5 times if they PHY is running at lower speeds. This last one is
> interesting.

That's not what I've read so far - but I don't know about the PHY
in this exact case because the docs are only available under NDA
(which makes it incredibly difficult to have this discussion.)

However, from what I can ascertain from a Xilinx document, 2.5G is
1G SGMII clocked 2.5x faster.  When in 2.5G mode, the other modes
are unavailable.  There's also no 250M or 25M as the speed bits
are not relevant.

The Xilinx doc does talk about a "2.5G SGMII standard" but I haven't
been able to locate such a thing - maybe someone can provide some
pointers?

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up

Re: [PATCH 1/1] phy: Add 2.5G SGMII interface mode

[Andrew Lunn]

On Thu, Nov 30, 2017 at 06:15:20PM +0000, Russell King - ARM Linux wrote:
> On Thu, Nov 30, 2017 at 06:41:27PM +0100, Andrew Lunn wrote:
> > SGMII supports passing auto-negotiation results from the PHY to the
> > MAC. 1000BASE-X does not.
> > 
> > SGMII supports the PHY running at 10, 100, and 1000 Mbps. But to
> > support this, the MAC needs to replicate the bits 100, or 10 times
> > when the PHY is running in 10 or 100Mbps mode.
> > 
> > So with your 2.5G SGMII, you need to replicate the bits 250, 25, or
> > 2.5 times if they PHY is running at lower speeds. This last one is
> > interesting.
> 
> That's not what I've read so far - but I don't know about the PHY
> in this exact case because the docs are only available under NDA
> (which makes it incredibly difficult to have this discussion.)
> 
> However, from what I can ascertain from a Xilinx document, 2.5G is
> 1G SGMII clocked 2.5x faster.  When in 2.5G mode, the other modes
> are unavailable.

Hi Russell

Thanks for looking into the details.

So you need the PHY driver to see what it has negotiated, and when it
calls the adjust_link callback, the MAC needs look at the
phydev->interface and set the MAC to 2.5G SGMII or SGMII.

Same as the Marvell 10G PHY driver flips between
PHY_INTERFACE_MODE_10GKR and PHY_INTERFACE_MODE_SGMII depending on
what it has negotiated.

     Andrew

Re: [PATCH 1/1] phy: Add 2.5G SGMII interface mode

[Russell King - ARM Linux]

On Thu, Nov 30, 2017 at 07:26:21PM +0100, Andrew Lunn wrote:
> On Thu, Nov 30, 2017 at 06:15:20PM +0000, Russell King - ARM Linux wrote:
> > On Thu, Nov 30, 2017 at 06:41:27PM +0100, Andrew Lunn wrote:
> > > SGMII supports passing auto-negotiation results from the PHY to the
> > > MAC. 1000BASE-X does not.
> > > 
> > > SGMII supports the PHY running at 10, 100, and 1000 Mbps. But to
> > > support this, the MAC needs to replicate the bits 100, or 10 times
> > > when the PHY is running in 10 or 100Mbps mode.
> > > 
> > > So with your 2.5G SGMII, you need to replicate the bits 250, 25, or
> > > 2.5 times if they PHY is running at lower speeds. This last one is
> > > interesting.
> > 
> > That's not what I've read so far - but I don't know about the PHY
> > in this exact case because the docs are only available under NDA
> > (which makes it incredibly difficult to have this discussion.)
> > 
> > However, from what I can ascertain from a Xilinx document, 2.5G is
> > 1G SGMII clocked 2.5x faster.  When in 2.5G mode, the other modes
> > are unavailable.
> 
> Hi Russell
> 
> Thanks for looking into the details.
> 
> So you need the PHY driver to see what it has negotiated, and when it
> calls the adjust_link callback, the MAC needs look at the
> phydev->interface and set the MAC to 2.5G SGMII or SGMII.

Yes, it /looks/ that way from what I've read so far.  I'd like to do
a more comprehensive look around at what various manufacturers are
doing before saying that definitively.  Even better would be to find
a specification for 2.5G SGMII!

> Same as the Marvell 10G PHY driver flips between
> PHY_INTERFACE_MODE_10GKR and PHY_INTERFACE_MODE_SGMII depending on
> what it has negotiated.

Having played extensively with the Marvell 88x3310 and thoroughly
inspected its registers and analysed its behaviour, I'd be hessitant
to compare other PHYs with it.  The 3310 PHY seems to be multiple PHY
blocks (from two vendors) in a single package, and it dynamically
switches in the appropriate hardware blocks according to the negotiated
link modes.

However, given that 1G SGMII is clocked at a different rate from 2.5G
SGMII, both ends would need to be configured the same.

For example, both mvneta and mvpp2.2 support 2.5G modes merely by
reconfiguring the comphy block, and all that does is increase the
serdes clock.  That's used for 2500BASE-X (which I have had working
locally through a devmem2 pokes on Clearfog and the older Marvell
pp2x driver on Macchiatobin) but it's more difficult to find 2.5G
copper SFP modules to test with - which would presumably talk 2.5G
SGMII.

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up

RE: [PATCH 1/1] phy: Add 2.5G SGMII interface mode

[Bhaskar Upadhaya]

>-----Original Message-----
>From: Russell King - ARM Linux [mailto:linux@armlinux.org.uk]
>Sent: Friday, December 01, 2017 12:23 AM
>To: Andrew Lunn <andrew@lunn.ch>
>Cc: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>; netdev@vger.kernel.org;
>davem@davemloft.net; linux-arm-kernel@lists.infradead.org
>Subject: Re: [PATCH 1/1] phy: Add 2.5G SGMII interface mode
>
>On Thu, Nov 30, 2017 at 07:26:21PM +0100, Andrew Lunn wrote:
>> On Thu, Nov 30, 2017 at 06:15:20PM +0000, Russell King - ARM Linux wrote:
>> > On Thu, Nov 30, 2017 at 06:41:27PM +0100, Andrew Lunn wrote:
>> > > SGMII supports passing auto-negotiation results from the PHY to
>> > > the MAC. 1000BASE-X does not.
>> > >
>> > > SGMII supports the PHY running at 10, 100, and 1000 Mbps. But to
>> > > support this, the MAC needs to replicate the bits 100, or 10 times
>> > > when the PHY is running in 10 or 100Mbps mode.
>> > >
>> > > So with your 2.5G SGMII, you need to replicate the bits 250, 25,
>> > > or
>> > > 2.5 times if they PHY is running at lower speeds. This last one is
>> > > interesting.
>> >
>> > That's not what I've read so far - but I don't know about the PHY in
>> > this exact case because the docs are only available under NDA (which
>> > makes it incredibly difficult to have this discussion.)
>> >
>> > However, from what I can ascertain from a Xilinx document, 2.5G is
>> > 1G SGMII clocked 2.5x faster.  When in 2.5G mode, the other modes
>> > are unavailable.
>>
>> Hi Russell
>>
>> Thanks for looking into the details.
>>
>> So you need the PHY driver to see what it has negotiated, and when it
>> calls the adjust_link callback, the MAC needs look at the
>> phydev->interface and set the MAC to 2.5G SGMII or SGMII.
>
>Yes, it /looks/ that way from what I've read so far.  I'd like to do a more
>comprehensive look around at what various manufacturers are doing before
>saying that definitively.  Even better would be to find a specification for 2.5G
>SGMII!
>
>> Same as the Marvell 10G PHY driver flips between
>> PHY_INTERFACE_MODE_10GKR and PHY_INTERFACE_MODE_SGMII depending
>on
>> what it has negotiated.
>
>Having played extensively with the Marvell 88x3310 and thoroughly inspected its
>registers and analysed its behaviour, I'd be hessitant to compare other PHYs with
>it.  The 3310 PHY seems to be multiple PHY blocks (from two vendors) in a single
>package, and it dynamically switches in the appropriate hardware blocks
>according to the negotiated link modes.
>
>However, given that 1G SGMII is clocked at a different rate from 2.5G SGMII,
>both ends would need to be configured the same.
>
>For example, both mvneta and mvpp2.2 support 2.5G modes merely by
>reconfiguring the comphy block, and all that does is increase the serdes clock.
>That's used for 2500BASE-X (which I have had working locally through a devmem2
>pokes on Clearfog and the older Marvell pp2x driver on Macchiatobin) but it's
>more difficult to find 2.5G copper SFP modules to test with - which would
>presumably talk 2.5G SGMII.

So do we need to introduce a new interface type PHY_INTERFACE_MODE_2500SGMII or is there a way to deal with 2.5G SGMII ?

>
>--
>RMK's Patch system:
>https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.ar
>mlinux.org.uk%2Fdeveloper%2Fpatches%2F&data=02%7C01%7Cbhaskar.upadha
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>FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
>According to speedtest.net: 8.21Mbps down 510kbps up

Re: [PATCH 1/1] phy: Add 2.5G SGMII interface mode

[Florian Fainelli]

On 12/01/2017 10:40 AM, Bhaskar Upadhaya wrote:
> 
>> -----Original Message-----
>> From: Russell King - ARM Linux [mailto:linux@armlinux.org.uk]
>> Sent: Friday, December 01, 2017 12:23 AM
>> To: Andrew Lunn <andrew@lunn.ch>
>> Cc: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>; netdev@vger.kernel.org;
>> davem@davemloft.net; linux-arm-kernel@lists.infradead.org
>> Subject: Re: [PATCH 1/1] phy: Add 2.5G SGMII interface mode
>>
>> On Thu, Nov 30, 2017 at 07:26:21PM +0100, Andrew Lunn wrote:
>>> On Thu, Nov 30, 2017 at 06:15:20PM +0000, Russell King - ARM Linux wrote:
>>>> On Thu, Nov 30, 2017 at 06:41:27PM +0100, Andrew Lunn wrote:
>>>>> SGMII supports passing auto-negotiation results from the PHY to
>>>>> the MAC. 1000BASE-X does not.
>>>>>
>>>>> SGMII supports the PHY running at 10, 100, and 1000 Mbps. But to
>>>>> support this, the MAC needs to replicate the bits 100, or 10 times
>>>>> when the PHY is running in 10 or 100Mbps mode.
>>>>>
>>>>> So with your 2.5G SGMII, you need to replicate the bits 250, 25,
>>>>> or
>>>>> 2.5 times if they PHY is running at lower speeds. This last one is
>>>>> interesting.
>>>>
>>>> That's not what I've read so far - but I don't know about the PHY in
>>>> this exact case because the docs are only available under NDA (which
>>>> makes it incredibly difficult to have this discussion.)
>>>>
>>>> However, from what I can ascertain from a Xilinx document, 2.5G is
>>>> 1G SGMII clocked 2.5x faster.  When in 2.5G mode, the other modes
>>>> are unavailable.
>>>
>>> Hi Russell
>>>
>>> Thanks for looking into the details.
>>>
>>> So you need the PHY driver to see what it has negotiated, and when it
>>> calls the adjust_link callback, the MAC needs look at the
>>> phydev->interface and set the MAC to 2.5G SGMII or SGMII.
>>
>> Yes, it /looks/ that way from what I've read so far.  I'd like to do a more
>> comprehensive look around at what various manufacturers are doing before
>> saying that definitively.  Even better would be to find a specification for 2.5G
>> SGMII!
>>
>>> Same as the Marvell 10G PHY driver flips between
>>> PHY_INTERFACE_MODE_10GKR and PHY_INTERFACE_MODE_SGMII depending
>> on
>>> what it has negotiated.
>>
>> Having played extensively with the Marvell 88x3310 and thoroughly inspected its
>> registers and analysed its behaviour, I'd be hessitant to compare other PHYs with
>> it.  The 3310 PHY seems to be multiple PHY blocks (from two vendors) in a single
>> package, and it dynamically switches in the appropriate hardware blocks
>> according to the negotiated link modes.
>>
>> However, given that 1G SGMII is clocked at a different rate from 2.5G SGMII,
>> both ends would need to be configured the same.
>>
>> For example, both mvneta and mvpp2.2 support 2.5G modes merely by
>> reconfiguring the comphy block, and all that does is increase the serdes clock.
>> That's used for 2500BASE-X (which I have had working locally through a devmem2
>> pokes on Clearfog and the older Marvell pp2x driver on Macchiatobin) but it's
>> more difficult to find 2.5G copper SFP modules to test with - which would
>> presumably talk 2.5G SGMII.
> 
> So do we need to introduce a new interface type PHY_INTERFACE_MODE_2500SGMII or is there a way to deal with 2.5G SGMII ?

Well, because you are proposing this change, we were sort of hoping you
could explain the rationale, and point us to the 2.5 SGMII standard
document so we can understand what this is about....
-- 
Florian

Re: [PATCH 1/1] phy: Add 2.5G SGMII interface mode

[Andrew Lunn]

> So do we need to introduce a new interface type
> PHY_INTERFACE_MODE_2500SGMII or is there a way to deal with 2.5G
> SGMII ?

And just adding to what Florian said, you don't just add a new define
like this, you also need to add a user of it. Posting your MAC and PHY
driver making use of this symbol will make it a lot clearer why it is
needed and how it should be used.

       Andrew