From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Steven J. Hill" Subject: [PATCH net-next v9 1/4] MIPS: Octeon: Enable LMTDMA/LMTST operations. Date: Thu, 26 Apr 2018 18:30:11 -0500 Message-ID: <1524785414-19236-2-git-send-email-steven.hill@cavium.com> References: <1524785414-19236-1-git-send-email-steven.hill@cavium.com> Mime-Version: 1.0 Content-Type: text/plain Cc: Carlos Munoz , "Steven J. Hill" , David Daney To: netdev@vger.kernel.org Return-path: Received: from mail-by2nam01on0056.outbound.protection.outlook.com ([104.47.34.56]:12128 "EHLO NAM01-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751314AbeDZXvP (ORCPT ); Thu, 26 Apr 2018 19:51:15 -0400 In-Reply-To: <1524785414-19236-1-git-send-email-steven.hill@cavium.com> Sender: netdev-owner@vger.kernel.org List-ID: From: Carlos Munoz LMTDMA/LMTST operations move data between cores and I/O devices: * LMTST operations can send an address and a variable length (up to 128 bytes) of data to an I/O device. * LMTDMA operations can send an address and a variable length (up to 128) of data to the I/O device and then return a variable length (up to 128 bytes) response from the I/O device. For both LMTST and LMTDMA, the data sent to the device is first stored in the CVMSEG core local memory cache line indexed by CVMMEMCTL[LMTLINE], the data is then atomically transmitted to the device with a store to the CVMSEG LMTDMA trigger location. Reviewed-by: James Hogan Signed-off-by: Carlos Munoz Signed-off-by: Steven J. Hill Signed-off-by: David Daney --- arch/mips/cavium-octeon/setup.c | 6 ++++++ arch/mips/include/asm/octeon/octeon.h | 12 ++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index a8034d0..99e6a68 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -609,6 +609,12 @@ void octeon_user_io_init(void) #else cvmmemctl.s.cvmsegenak = 0; #endif + if (OCTEON_IS_OCTEON3()) { + /* Enable LMTDMA */ + cvmmemctl.s.lmtena = 1; + /* Scratch line to use for LMT operation */ + cvmmemctl.s.lmtline = 2; + } /* R/W If set, CVMSEG is available for loads/stores in * supervisor mode. */ cvmmemctl.s.cvmsegenas = 0; diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index c99c4b6..92a17d6 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -179,7 +179,15 @@ union octeon_cvmemctl { /* RO 1 = BIST fail, 0 = BIST pass */ __BITFIELD_FIELD(uint64_t wbfbist:1, /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved:17, + __BITFIELD_FIELD(uint64_t reserved_52_57:6, + /* When set, LMTDMA/LMTST operations are permitted */ + __BITFIELD_FIELD(uint64_t lmtena:1, + /* Selects the CVMSEG LM cacheline used by LMTDMA + * LMTST and wide atomic store operations. + */ + __BITFIELD_FIELD(uint64_t lmtline:6, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_41_44:4, /* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU. * This field selects between the TLB replacement policies: * bitmask LRU or NLU. Bitmask LRU maintains a mask of @@ -275,7 +283,7 @@ union octeon_cvmemctl { /* R/W Size of local memory in cache blocks, 54 (6912 * bytes) is max legal value. */ __BITFIELD_FIELD(uint64_t lmemsz:6, - ;))))))))))))))))))))))))))))))))) + ;)))))))))))))))))))))))))))))))))))) } s; }; -- 2.1.4