From: sunil.kovvuri@gmail.com
To: netdev@vger.kernel.org, davem@davemloft.net
Cc: arnd@arndb.de, linux-soc@vger.kernel.org,
Sunil Goutham <sgoutham@marvell.com>
Subject: [PATCH 11/15] octeontx2-af: Add Marvell OcteonTX2 CGX driver
Date: Fri, 28 Sep 2018 11:37:48 +0530 [thread overview]
Message-ID: <1538114872-10820-12-git-send-email-sunil.kovvuri@gmail.com> (raw)
In-Reply-To: <1538114872-10820-1-git-send-email-sunil.kovvuri@gmail.com>
From: Sunil Goutham <sgoutham@marvell.com>
This patch adds basic template for Marvell OcteonTX2's
CGX ethernet interface driver. Just the probe.
RVU AF driver will use APIs exported by this driver
for various things like PF to physical interface mapping,
loopback mode, interface stats etc. Hence marged both
drivers into a single module.
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
---
drivers/net/ethernet/marvell/octeontx2/af/Makefile | 2 +-
drivers/net/ethernet/marvell/octeontx2/af/cgx.c | 100 +++++++++++++++++++++
drivers/net/ethernet/marvell/octeontx2/af/cgx.h | 22 +++++
drivers/net/ethernet/marvell/octeontx2/af/rvu.c | 14 ++-
4 files changed, 136 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/cgx.c
create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/cgx.h
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/Makefile b/drivers/net/ethernet/marvell/octeontx2/af/Makefile
index ac17cb9..8646421 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/Makefile
+++ b/drivers/net/ethernet/marvell/octeontx2/af/Makefile
@@ -7,4 +7,4 @@ obj-$(CONFIG_OCTEONTX2_MBOX) += octeontx2_mbox.o
obj-$(CONFIG_OCTEONTX2_AF) += octeontx2_af.o
octeontx2_mbox-y := mbox.o
-octeontx2_af-y := rvu.o
+octeontx2_af-y := cgx.o rvu.o
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
new file mode 100644
index 0000000..cfd80d2
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Marvell OcteonTx2 CGX driver
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/acpi.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/phy.h>
+#include <linux/of.h>
+#include <linux/of_mdio.h>
+#include <linux/of_net.h>
+
+#include "cgx.h"
+
+#define DRV_NAME "octeontx2-cgx"
+#define DRV_STRING "Marvell OcteonTX2 CGX/MAC Driver"
+
+struct cgx {
+ void __iomem *reg_base;
+ struct pci_dev *pdev;
+ u8 cgx_id;
+};
+
+/* Supported devices */
+static const struct pci_device_id cgx_id_table[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) },
+ { 0, } /* end of table */
+};
+
+MODULE_AUTHOR("Marvell International Ltd.");
+MODULE_DESCRIPTION(DRV_STRING);
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(pci, cgx_id_table);
+
+static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ int err;
+ struct device *dev = &pdev->dev;
+ struct cgx *cgx;
+
+ cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL);
+ if (!cgx)
+ return -ENOMEM;
+ cgx->pdev = pdev;
+
+ pci_set_drvdata(pdev, cgx);
+
+ err = pci_enable_device(pdev);
+ if (err) {
+ dev_err(dev, "Failed to enable PCI device\n");
+ pci_set_drvdata(pdev, NULL);
+ return err;
+ }
+
+ err = pci_request_regions(pdev, DRV_NAME);
+ if (err) {
+ dev_err(dev, "PCI request regions failed 0x%x\n", err);
+ goto err_disable_device;
+ }
+
+ /* MAP configuration registers */
+ cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
+ if (!cgx->reg_base) {
+ dev_err(dev, "CGX: Cannot map CSR memory space, aborting\n");
+ err = -ENOMEM;
+ goto err_release_regions;
+ }
+
+ return 0;
+
+err_release_regions:
+ pci_release_regions(pdev);
+err_disable_device:
+ pci_disable_device(pdev);
+ pci_set_drvdata(pdev, NULL);
+ return err;
+}
+
+static void cgx_remove(struct pci_dev *pdev)
+{
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ pci_set_drvdata(pdev, NULL);
+}
+
+struct pci_driver cgx_driver = {
+ .name = DRV_NAME,
+ .id_table = cgx_id_table,
+ .probe = cgx_probe,
+ .remove = cgx_remove,
+};
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
new file mode 100644
index 0000000..a7d4b39
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * Marvell OcteonTx2 CGX driver
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef CGX_H
+#define CGX_H
+
+ /* PCI device IDs */
+#define PCI_DEVID_OCTEONTX2_CGX 0xA059
+
+/* PCI BAR nos */
+#define PCI_CFG_REG_BAR_NUM 0
+
+extern struct pci_driver cgx_driver;
+
+#endif /* CGX_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
index 2a9d2b7..2e9b252 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
@@ -15,6 +15,7 @@
#include <linux/pci.h>
#include <linux/sysfs.h>
+#include "cgx.h"
#include "rvu.h"
#include "rvu_reg.h"
@@ -1605,14 +1606,25 @@ static struct pci_driver rvu_driver = {
static int __init rvu_init_module(void)
{
+ int err;
+
pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
- return pci_register_driver(&rvu_driver);
+ err = pci_register_driver(&cgx_driver);
+ if (err < 0)
+ return err;
+
+ err = pci_register_driver(&rvu_driver);
+ if (err < 0)
+ pci_unregister_driver(&cgx_driver);
+
+ return err;
}
static void __exit rvu_cleanup_module(void)
{
pci_unregister_driver(&rvu_driver);
+ pci_unregister_driver(&cgx_driver);
}
module_init(rvu_init_module);
--
2.7.4
next prev parent reply other threads:[~2018-09-28 12:31 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-28 6:07 [PATCH 00/15] octeontx2-af: Add RVU Admin Function driver sunil.kovvuri
2018-09-28 6:07 ` [PATCH 01/15] octeontx2-af: Add Marvell OcteonTX2 RVU AF driver sunil.kovvuri
2018-09-28 6:07 ` [PATCH 02/15] octeontx2-af: Reset all RVU blocks sunil.kovvuri
2018-09-28 6:07 ` [PATCH 03/15] octeontx2-af: Gather RVU blocks HW info sunil.kovvuri
2018-09-28 6:07 ` [PATCH 04/15] octeontx2-af: Add mailbox support infra sunil.kovvuri
2018-09-28 6:07 ` [PATCH 05/15] octeontx2-af: Add mailbox IRQ and msg handlers sunil.kovvuri
2018-09-28 6:07 ` [PATCH 06/15] octeontx2-af: Convert mbox msg id check to a macro sunil.kovvuri
2018-09-28 6:07 ` [PATCH 07/15] octeontx2-af: Scan blocks for LFs provisioned to PF/VF sunil.kovvuri
2018-09-28 6:07 ` [PATCH 08/15] octeontx2-af: Add RVU block LF provisioning support sunil.kovvuri
2018-09-28 6:07 ` [PATCH 09/15] octeontx2-af: Configure block LF's MSIX vector offset sunil.kovvuri
2018-09-28 6:07 ` [PATCH 10/15] octeontx2-af: Reconfig MSIX base with IOVA sunil.kovvuri
2018-09-28 6:07 ` sunil.kovvuri [this message]
2018-09-28 8:14 ` [PATCH 11/15] octeontx2-af: Add Marvell OcteonTX2 CGX driver Arnd Bergmann
2018-09-28 9:19 ` Sunil Kovvuri
2018-09-28 6:07 ` [PATCH 12/15] octeontx2-af: Set RVU PFs to CGX LMACs mapping sunil.kovvuri
2018-09-28 6:07 ` [PATCH 13/15] octeontx2-af: Add support for CGX link management sunil.kovvuri
2018-09-28 8:19 ` Arnd Bergmann
2018-09-28 9:31 ` Sunil Kovvuri
2018-09-28 10:00 ` Arnd Bergmann
2018-09-28 6:07 ` [PATCH 14/15] octeontx2-af: Register for CGX lmac events sunil.kovvuri
2018-09-28 6:07 ` [PATCH 15/15] MAINTAINERS: Add entry for Marvell OcteonTX2 Admin Function driver sunil.kovvuri
2018-09-28 8:27 ` [PATCH 00/15] octeontx2-af: Add RVU " Arnd Bergmann
2018-09-28 9:35 ` Sunil Kovvuri
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