From: Michael Chan <michael.chan@broadcom.com>
To: davem@davemloft.net
Cc: netdev@vger.kernel.org
Subject: [PATCH net-next 15/23] bnxt_en: Modify bnxt_ring_alloc_send_msg() to support 57500 chips.
Date: Sun, 14 Oct 2018 07:02:51 -0400 [thread overview]
Message-ID: <1539514979-2859-16-git-send-email-michael.chan@broadcom.com> (raw)
In-Reply-To: <1539514979-2859-1-git-send-email-michael.chan@broadcom.com>
Firmware ring allocation semantics are slightly different for most
ring types on 57500 chips. Allocation/deallocation for NQ rings are
also added for the new chips.
A CP ring handle is also added so that from the NQ interrupt event,
we can locate the CP ring.
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
---
drivers/net/ethernet/broadcom/bnxt/bnxt.c | 61 ++++++++++++++++++++++++++++---
drivers/net/ethernet/broadcom/bnxt/bnxt.h | 1 +
2 files changed, 56 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
index 99af288..db1dbad 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
@@ -4543,14 +4543,53 @@ static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
case HWRM_RING_ALLOC_RX:
req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
req.length = cpu_to_le32(bp->rx_ring_mask + 1);
+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
+ u16 flags = 0;
+
+ /* Association of rx ring with stats context */
+ grp_info = &bp->grp_info[ring->grp_idx];
+ req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
+ req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
+ req.enables |= cpu_to_le32(
+ RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
+ if (NET_IP_ALIGN == 2)
+ flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
+ req.flags = cpu_to_le16(flags);
+ }
break;
case HWRM_RING_ALLOC_AGG:
- req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
+ req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
+ /* Association of agg ring with rx ring */
+ grp_info = &bp->grp_info[ring->grp_idx];
+ req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
+ req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
+ req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
+ req.enables |= cpu_to_le32(
+ RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
+ RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
+ } else {
+ req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
+ }
req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
break;
case HWRM_RING_ALLOC_CMPL:
req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
req.length = cpu_to_le32(bp->cp_ring_mask + 1);
+ if (bp->flags & BNXT_FLAG_CHIP_P5) {
+ /* Association of cp ring with nq */
+ grp_info = &bp->grp_info[map_index];
+ req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
+ req.cq_handle = cpu_to_le64(ring->handle);
+ req.enables |= cpu_to_le32(
+ RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
+ } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
+ req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
+ }
+ break;
+ case HWRM_RING_ALLOC_NQ:
+ req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
+ req.length = cpu_to_le32(bp->cp_ring_mask + 1);
if (bp->flags & BNXT_FLAG_USING_MSIX)
req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
break;
@@ -4645,7 +4684,10 @@ static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
int i, rc = 0;
u32 type;
- type = HWRM_RING_ALLOC_CMPL;
+ if (bp->flags & BNXT_FLAG_CHIP_P5)
+ type = HWRM_RING_ALLOC_NQ;
+ else
+ type = HWRM_RING_ALLOC_CMPL;
for (i = 0; i < bp->cp_nr_rings; i++) {
struct bnxt_napi *bnapi = bp->bnapi[i];
struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
@@ -4743,6 +4785,7 @@ static int hwrm_ring_free_send_msg(struct bnxt *bp,
static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
{
+ u32 type;
int i;
if (!bp->bnapi)
@@ -4781,6 +4824,10 @@ static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
}
}
+ if (bp->flags & BNXT_FLAG_CHIP_P5)
+ type = RING_FREE_REQ_RING_TYPE_RX_AGG;
+ else
+ type = RING_FREE_REQ_RING_TYPE_RX;
for (i = 0; i < bp->rx_nr_rings; i++) {
struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
@@ -4789,8 +4836,7 @@ static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
if (ring->fw_ring_id != INVALID_HW_RING_ID) {
- hwrm_ring_free_send_msg(bp, ring,
- RING_FREE_REQ_RING_TYPE_RX,
+ hwrm_ring_free_send_msg(bp, ring, type,
close_path ? cmpl_ring_id :
INVALID_HW_RING_ID);
ring->fw_ring_id = INVALID_HW_RING_ID;
@@ -4805,14 +4851,17 @@ static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
*/
bnxt_disable_int_sync(bp);
+ if (bp->flags & BNXT_FLAG_CHIP_P5)
+ type = RING_FREE_REQ_RING_TYPE_NQ;
+ else
+ type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
for (i = 0; i < bp->cp_nr_rings; i++) {
struct bnxt_napi *bnapi = bp->bnapi[i];
struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
if (ring->fw_ring_id != INVALID_HW_RING_ID) {
- hwrm_ring_free_send_msg(bp, ring,
- RING_FREE_REQ_RING_TYPE_L2_CMPL,
+ hwrm_ring_free_send_msg(bp, ring, type,
INVALID_HW_RING_ID);
ring->fw_ring_id = INVALID_HW_RING_ID;
bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.h b/drivers/net/ethernet/broadcom/bnxt/bnxt.h
index 589b0be..560e8b7 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.h
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.h
@@ -634,6 +634,7 @@ struct bnxt_ring_struct {
u16 grp_idx;
u16 map_idx; /* Used by cmpl rings */
};
+ u32 handle;
u8 queue_id;
};
--
2.5.1
next prev parent reply other threads:[~2018-10-14 18:44 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-14 11:02 [PATCH net-next 00/23] bnxt_en: Add support for new 57500 chips Michael Chan
2018-10-14 11:02 ` [PATCH net-next 01/23] bnxt_en: Update firmware interface spec. to 1.10.0.3 Michael Chan
2018-10-14 11:02 ` [PATCH net-next 02/23] bnxt_en: Add additional extended port statistics Michael Chan
2018-10-14 11:02 ` [PATCH net-next 03/23] bnxt_en: Add maximum extended request length fw message support Michael Chan
2018-10-14 11:02 ` [PATCH net-next 04/23] bnxt_en: Update interrupt coalescing logic Michael Chan
2018-10-14 11:02 ` [PATCH net-next 05/23] bnxt_en: Refactor bnxt_ring_struct Michael Chan
2018-10-14 11:02 ` [PATCH net-next 06/23] bnxt_en: Add new flags to setup new page table PTE bits on newer devices Michael Chan
2018-10-14 11:02 ` [PATCH net-next 07/23] bnxt_en: Check context memory requirements from firmware Michael Chan
2018-10-14 11:02 ` [PATCH net-next 08/23] bnxt_en: Configure context memory on new devices Michael Chan
2018-10-14 11:02 ` [PATCH net-next 09/23] bnxt_en: Add 57500 new chip ID and basic structures Michael Chan
2018-10-14 11:02 ` [PATCH net-next 10/23] bnxt_en: Re-structure doorbells Michael Chan
2018-10-14 11:02 ` [PATCH net-next 11/23] bnxt_en: Adjust MSIX and ring groups for 57500 series chips Michael Chan
2018-10-14 11:02 ` [PATCH net-next 12/23] bnxt_en: Modify the ring reservation functions " Michael Chan
2018-10-14 11:02 ` [PATCH net-next 13/23] bnxt_en: Allocate completion ring structures " Michael Chan
2018-10-14 11:02 ` [PATCH net-next 14/23] bnxt_en: Add helper functions to get firmware CP ring ID Michael Chan
2018-10-14 11:02 ` Michael Chan [this message]
2018-10-14 11:02 ` [PATCH net-next 16/23] bnxt_en: Allocate/Free CP rings for 57500 series chips Michael Chan
2018-10-14 11:02 ` [PATCH net-next 17/23] bnxt_en: Increase RSS context array count and skip ring groups on 57500 chips Michael Chan
2018-10-14 11:02 ` [PATCH net-next 18/23] bnxt_en: Add RSS support for " Michael Chan
2018-10-14 11:02 ` [PATCH net-next 19/23] bnxt_en: Use bnxt_cp_ring_info struct pointer as parameter for RX path Michael Chan
2018-10-14 11:02 ` [PATCH net-next 20/23] bnxt_en: Add coalescing setup for 57500 chips Michael Chan
2018-10-14 11:02 ` [PATCH net-next 21/23] bnxt_en: Refactor bnxt_poll_work() Michael Chan
2018-10-14 11:02 ` [PATCH net-next 22/23] bnxt_en: Add new NAPI poll function for 57500 chips Michael Chan
2018-10-14 11:02 ` [PATCH net-next 23/23] bnxt_en: Add PCI ID for BCM57508 device Michael Chan
2018-10-16 5:47 ` [PATCH net-next 00/23] bnxt_en: Add support for new 57500 chips David Miller
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