From: sunil.kovvuri@gmail.com
To: netdev@vger.kernel.org, davem@davemloft.net
Cc: arnd@arndb.de, linux-soc@vger.kernel.org,
Christina Jacob <cjacob@marvell.com>,
Sunil Goutham <sgoutham@marvell.com>
Subject: [PATCH 03/16] octeontx2-af: Support to retrieve CGX LMAC stats
Date: Tue, 16 Oct 2018 16:57:07 +0530 [thread overview]
Message-ID: <1539689240-11526-4-git-send-email-sunil.kovvuri@gmail.com> (raw)
In-Reply-To: <1539689240-11526-1-git-send-email-sunil.kovvuri@gmail.com>
From: Christina Jacob <cjacob@marvell.com>
This patch adds support for a RVU PF/VF driver to retrieve
it's mapped CGX LMAC Rx and Tx stats from AF via mbox.
New mailbox msg is added is added.
Signed-off-by: Christina Jacob <cjacob@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
---
drivers/net/ethernet/marvell/octeontx2/af/cgx.c | 22 +++++++++++++
drivers/net/ethernet/marvell/octeontx2/af/cgx.h | 4 +++
drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 11 +++++++
drivers/net/ethernet/marvell/octeontx2/af/rvu.h | 2 ++
.../net/ethernet/marvell/octeontx2/af/rvu_cgx.c | 37 ++++++++++++++++++++++
5 files changed, 76 insertions(+)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
index 03a91c6..a7dc6f2 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
@@ -119,6 +119,28 @@ void *cgx_get_pdata(int cgx_id)
}
EXPORT_SYMBOL(cgx_get_pdata);
+int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat)
+{
+ struct cgx *cgx = cgxd;
+
+ if (!cgx || lmac_id >= cgx->lmac_count)
+ return -ENODEV;
+ *rx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx * 8));
+ return 0;
+}
+EXPORT_SYMBOL(cgx_get_rx_stats);
+
+int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat)
+{
+ struct cgx *cgx = cgxd;
+
+ if (!cgx || lmac_id >= cgx->lmac_count)
+ return -ENODEV;
+ *tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx * 8));
+ return 0;
+}
+EXPORT_SYMBOL(cgx_get_tx_stats);
+
int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable)
{
struct cgx *cgx = cgxd;
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
index 9097935..8f596dfb 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
@@ -32,7 +32,9 @@
#define FW_CGX_INT BIT_ULL(1)
#define CGXX_CMRX_INT_ENA_W1S 0x058
#define CGXX_CMRX_RX_ID_MAP 0x060
+#define CGXX_CMRX_RX_STAT0 0x070
#define CGXX_CMRX_RX_LMACS 0x128
+#define CGXX_CMRX_TX_STAT0 0x700
#define CGXX_SCRATCH0_REG 0x1050
#define CGXX_SCRATCH1_REG 0x1058
#define CGX_CONST 0x2000
@@ -66,5 +68,7 @@ int cgx_get_cgx_cnt(void);
int cgx_get_lmac_cnt(void *cgxd);
void *cgx_get_pdata(int cgx_id);
int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
+int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
+int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);
int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);
#endif /* CGX_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index 6b66cf0..03dd04d 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -126,6 +126,7 @@ M(MSIX_OFFSET, 0x004, msg_req, msix_offset_rsp) \
/* CGX mbox IDs (range 0x200 - 0x3FF) */ \
M(CGX_START_RXTX, 0x200, msg_req, msg_rsp) \
M(CGX_STOP_RXTX, 0x201, msg_req, msg_rsp) \
+M(CGX_STATS, 0x202, msg_req, cgx_stats_rsp) \
/* NPA mbox IDs (range 0x400 - 0x5FF) */ \
/* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
/* TIM mbox IDs (range 0x800 - 0x9FF) */ \
@@ -210,4 +211,14 @@ struct msix_offset_rsp {
u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
};
+/* CGX mbox message formats */
+
+struct cgx_stats_rsp {
+ struct mbox_msghdr hdr;
+#define CGX_RX_STATS_COUNT 13
+#define CGX_TX_STATS_COUNT 18
+ u64 rx_stats[CGX_RX_STATS_COUNT];
+ u64 tx_stats[CGX_TX_STATS_COUNT];
+};
+
#endif /* MBOX_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index 4cf2bcb..8ee6663 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -171,4 +171,6 @@ int rvu_mbox_handler_CGX_START_RXTX(struct rvu *rvu, struct msg_req *req,
struct msg_rsp *rsp);
int rvu_mbox_handler_CGX_STOP_RXTX(struct rvu *rvu, struct msg_req *req,
struct msg_rsp *rsp);
+int rvu_mbox_handler_CGX_STATS(struct rvu *rvu, struct msg_req *req,
+ struct cgx_stats_rsp *rsp);
#endif /* RVU_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
index 75a03a8..a4aa1e0 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
@@ -224,3 +224,40 @@ int rvu_mbox_handler_CGX_STOP_RXTX(struct rvu *rvu, struct msg_req *req,
rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, false);
return 0;
}
+
+int rvu_mbox_handler_CGX_STATS(struct rvu *rvu, struct msg_req *req,
+ struct cgx_stats_rsp *rsp)
+{
+ int pf = rvu_get_pf(req->hdr.pcifunc);
+ int stat = 0, err = 0;
+ u64 tx_stat, rx_stat;
+ u8 cgx_idx, lmac;
+ void *cgxd;
+
+ if ((req->hdr.pcifunc & RVU_PFVF_FUNC_MASK) ||
+ !is_pf_cgxmapped(rvu, pf))
+ return -ENODEV;
+
+ rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
+ cgxd = rvu_cgx_pdata(cgx_idx, rvu);
+
+ /* Rx stats */
+ while (stat < CGX_RX_STATS_COUNT) {
+ err = cgx_get_rx_stats(cgxd, lmac, stat, &rx_stat);
+ if (err)
+ return err;
+ rsp->rx_stats[stat] = rx_stat;
+ stat++;
+ }
+
+ /* Tx stats */
+ stat = 0;
+ while (stat < CGX_TX_STATS_COUNT) {
+ err = cgx_get_tx_stats(cgxd, lmac, stat, &tx_stat);
+ if (err)
+ return err;
+ rsp->tx_stats[stat] = tx_stat;
+ stat++;
+ }
+ return 0;
+}
--
2.7.4
next prev parent reply other threads:[~2018-10-16 19:17 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-16 11:27 [PATCH 00/16] octeontx2-af: NPA and NIX blocks initialization sunil.kovvuri
2018-10-16 11:27 ` [PATCH 01/16] octeontx2-af: Improve register polling loop sunil.kovvuri
2018-10-16 11:27 ` [PATCH 02/16] octeontx2-af: CGX Rx/Tx enable/disable mbox handlers sunil.kovvuri
2018-10-16 11:27 ` sunil.kovvuri [this message]
2018-10-16 11:27 ` [PATCH 04/16] octeontx2-af: Support for MAC address filters in CGX sunil.kovvuri
2018-10-16 11:27 ` [PATCH 05/16] octeontx2-af: Forward CGX link notifications to PFs sunil.kovvuri
2018-10-16 11:27 ` [PATCH 06/16] octeontx2-af: Enable or disable CGX internal loopback sunil.kovvuri
2018-10-16 11:27 ` [PATCH 07/16] octeontx2-af: NPA block admin queue init sunil.kovvuri
2018-10-16 11:27 ` [PATCH 08/16] octeontx2-af: NPA block LF initialization sunil.kovvuri
2018-10-16 11:27 ` [PATCH 09/16] octeontx2-af: NPA AQ instruction enqueue support sunil.kovvuri
2018-10-16 11:27 ` [PATCH 10/16] octeontx2-af: Support for disabling NPA Aura/Pool contexts sunil.kovvuri
2018-10-16 11:27 ` [PATCH 11/16] octeontx2-af: NIX block admin queue init sunil.kovvuri
2018-10-16 11:27 ` [PATCH 12/16] octeontx2-af: NIX block LF initialization sunil.kovvuri
2018-10-16 11:27 ` [PATCH 13/16] octeontx2-af: NIX LSO config for TSOv4/v6 offload sunil.kovvuri
2018-10-16 11:27 ` [PATCH 14/16] octeontx2-af: Alloc bitmaps for NIX Tx scheduler queues sunil.kovvuri
2018-10-16 11:27 ` [PATCH 15/16] octeontx2-af: NIX AQ instruction enqueue support sunil.kovvuri
2018-10-16 11:27 ` [PATCH 16/16] octeontx2-af: Support for disabling NIX RQ/SQ/CQ contexts sunil.kovvuri
2018-10-18 4:34 ` [PATCH 00/16] octeontx2-af: NPA and NIX blocks initialization David Miller
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