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From: Tariq Toukan <tariqt@mellanox.com>
To: "David S. Miller" <davem@davemloft.net>
Cc: netdev@vger.kernel.org, Eran Ben Elisha <eranbe@mellanox.com>,
	Eric Dumazet <edumazet@google.com>,
	Tariq Toukan <tariqt@mellanox.com>
Subject: [PATCH net-next] net/mlx4_core: A write memory barrier is sufficient in EQ ci update
Date: Tue, 22 Jan 2019 15:25:50 +0200	[thread overview]
Message-ID: <1548163550-16750-1-git-send-email-tariqt@mellanox.com> (raw)

Soften the memory barrier call of mb() by a sufficient wmb() in the
consumer index update of the event queues.

Suggested-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
---
 drivers/net/ethernet/mellanox/mlx4/eq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlx4/eq.c b/drivers/net/ethernet/mellanox/mlx4/eq.c
index 4953c852c247..56395aa04ca1 100644
--- a/drivers/net/ethernet/mellanox/mlx4/eq.c
+++ b/drivers/net/ethernet/mellanox/mlx4/eq.c
@@ -100,7 +100,7 @@ static void eq_set_ci(struct mlx4_eq *eq, int req_not)
 					       req_not << 31),
 		     eq->doorbell);
 	/* We still want ordering, just not swabbing, so add a barrier */
-	mb();
+	wmb();
 }
 
 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor,
-- 
1.8.3.1


             reply	other threads:[~2019-01-22 13:26 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-22 13:25 Tariq Toukan [this message]
2019-01-25  5:54 ` [PATCH net-next] net/mlx4_core: A write memory barrier is sufficient in EQ ci update David Miller

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