From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6927C43381 for ; Thu, 14 Feb 2019 06:48:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B14112229F for ; Thu, 14 Feb 2019 06:48:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731278AbfBNGrG (ORCPT ); Thu, 14 Feb 2019 01:47:06 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:2155 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726940AbfBNGrF (ORCPT ); Thu, 14 Feb 2019 01:47:05 -0500 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1E6aQLm008418; Thu, 14 Feb 2019 07:46:46 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2qmxr718mb-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 14 Feb 2019 07:46:46 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C551C34; Thu, 14 Feb 2019 06:46:43 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4508F2432; Thu, 14 Feb 2019 06:46:43 +0000 (GMT) Received: from SAFEX1HUBCAS24.st.com (10.75.90.95) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 14 Feb 2019 07:46:43 +0100 Received: from localhost (10.201.23.166) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 14 Feb 2019 07:46:42 +0100 From: Christophe Roullier To: , , , , , , CC: , , , , , , Subject: [PATCH 0/8] stmmac: add some fixes for stm32 Date: Thu, 14 Feb 2019 07:45:55 +0100 Message-ID: <1550126763-22669-1-git-send-email-christophe.roullier@st.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.166] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-02-14_04:,, signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org For common stmmac: - Add support to set CSR Clock range selection in DT For stm32mpu: - Glue codes to support magic packet - Glue codes to support all PHY config : PHY_MODE (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz), PHY wo crystal (50Mhz), No 125Mhz from PHY config For stm32mcu: - Add Ethernet support for stm32h7 - Add syscfg clk support for stm32f4 Christophe Roullier (8): net: ethernet: stmmac: manage Ethernet WoL for stm32mp157c. net: ethernet: stmmac: update to support all PHY config for stm32mp157c. dt-bindings: net: stmmac: add phys config properties net: ethernet: stmmac: add management of clk_csr property net: ethernet: stmmac: update to be compatible with MCU family (stm32f4, stm32h7) dt-bindings: net: stmmac: add syscfg clock property ARM: dts: stm32: Add Ethernet support on stm32h7 SOC and activate it for eval and disco boards ARM: dts: stm32: add syscfg clock support for Ethernet on STM32F429 SoC .../devicetree/bindings/net/stm32-dwmac.txt | 10 +- arch/arm/boot/dts/stm32f429.dtsi | 6 +- arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 15 ++ arch/arm/boot/dts/stm32h743.dtsi | 19 +++ arch/arm/boot/dts/stm32h743i-disco.dts | 17 ++ arch/arm/boot/dts/stm32h743i-eval.dts | 17 ++ drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 179 +++++++++++++++++---- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 + 8 files changed, 230 insertions(+), 36 deletions(-) -- 2.7.4