From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61634C43381 for ; Fri, 22 Feb 2019 08:28:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 390CC20700 for ; Fri, 22 Feb 2019 08:28:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726979AbfBVI2u (ORCPT ); Fri, 22 Feb 2019 03:28:50 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:13356 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726254AbfBVI2t (ORCPT ); Fri, 22 Feb 2019 03:28:49 -0500 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1M8QehG018118; Fri, 22 Feb 2019 09:28:33 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2qpc6xsdjm-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 22 Feb 2019 09:28:33 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1D5383D; Fri, 22 Feb 2019 08:28:32 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E0ED528AB; Fri, 22 Feb 2019 08:28:31 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 22 Feb 2019 09:28:31 +0100 Received: from localhost (10.201.23.166) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 22 Feb 2019 09:28:31 +0100 From: Christophe Roullier To: , , , , , , CC: , , , , , , Subject: [PATCH V2 5/8] net: ethernet: stmmac: update to be compatible with MCU family (stm32f4, stm32h7) Date: Fri, 22 Feb 2019 09:28:06 +0100 Message-ID: <1550824089-19961-6-git-send-email-christophe.roullier@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1550824089-19961-1-git-send-email-christophe.roullier@st.com> References: <1550824089-19961-1-git-send-email-christophe.roullier@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.166] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-02-22_06:,, signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Update glue codes to be compatible with MCU family. Signed-off-by: Christophe Roullier --- drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 51 ++++++++++++++++++----- 1 file changed, 41 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index 8d5150a..66d95c2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -6,7 +6,6 @@ * License terms: GNU General Public License (GPL), version 2 * */ - #include #include #include @@ -119,12 +118,6 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat) struct stm32_dwmac *dwmac = plat_dat->bsp_priv; int ret; - if (dwmac->ops->set_mode) { - ret = dwmac->ops->set_mode(plat_dat); - if (ret) - return ret; - } - ret = clk_prepare_enable(dwmac->clk_tx); if (ret) return ret; @@ -139,13 +132,26 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat) if (dwmac->ops->clk_prepare) { ret = dwmac->ops->clk_prepare(dwmac, true); + if (ret) + goto err_clk_disable; + } + + if (dwmac->ops->set_mode) { + ret = dwmac->ops->set_mode(plat_dat); if (ret) { - clk_disable_unprepare(dwmac->clk_rx); - clk_disable_unprepare(dwmac->clk_tx); + if (dwmac->ops->clk_prepare) + dwmac->ops->clk_prepare(dwmac, false); + goto err_clk_disable; } } return ret; + +err_clk_disable: + clk_disable_unprepare(dwmac->clk_rx); + clk_disable_unprepare(dwmac->clk_tx); + + return ret; } static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare) @@ -243,7 +249,19 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) } return regmap_update_bits(dwmac->regmap, reg, - dwmac->ops->syscfg_eth_mask, val); + dwmac->ops->syscfg_eth_mask, val << 23); +} + +static int stm32mcu_clk_prepare(struct stm32_dwmac *dwmac, bool prepare) +{ + int ret = 0; + + if (prepare) + ret = clk_prepare_enable(dwmac->syscfg_clk); + else + clk_disable_unprepare(dwmac->syscfg_clk); + + return ret; } static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac) @@ -350,6 +368,17 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, return err; } +static int stm32mcu_parse_data(struct stm32_dwmac *dwmac, + struct device *dev) +{ + /* Clock for sysconfig */ + dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk"); + if (IS_ERR(dwmac->syscfg_clk)) + dev_warn(dev, "No syscfg clock provided...\n"); + + return 0; +} + static int stm32_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat_dat; @@ -496,7 +525,9 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops, static struct stm32_ops stm32mcu_dwmac_data = { .set_mode = stm32mcu_set_mode, + .clk_prepare = stm32mcu_clk_prepare, .suspend = stm32mcu_suspend, + .parse_data = stm32mcu_parse_data, .syscfg_eth_mask = SYSCFG_MCU_ETH_MASK }; -- 2.7.4