[PATCH net-next v5 00/20] Xilinx axienet driver updates (v5)

[Robert Hancock <hancock@sedsystems.ca>]

This is a series of enhancements and bug fixes in order to get the mainline
version of this driver into a more generally usable state, including on
x86 or ARM platforms. It also converts the driver to use the phylink API
in order to provide support for SFP modules.

Changes since v4:
-Use reverse christmas tree variable order

Robert Hancock (20):
  net: axienet: Fix casting of pointers to u32
  net: axienet: Use standard IO accessors
  net: axienet: fix MDIO bus naming
  net: axienet: add X86 and ARM as supported platforms
  net: axienet: Use clock framework to get device clock rate
  net: axienet: fix teardown order of MDIO bus
  net: axienet: Re-initialize MDIO registers properly after reset
  net: axienet: Cleanup DMA device reset and halt process
  net: axienet: Make RX/TX ring sizes configurable
  net: axienet: Add DMA registers to ethtool register dump
  net: axienet: Support shared interrupts
  net: axienet: Add optional support for Ethernet core interrupt
  net: axienet: Fix race condition causing TX hang
  net: axienet: Make missing MAC address non-fatal
  net: axienet: stop interface during shutdown
  net: axienet: document device tree mdio child node
  net: axienet: Fix MDIO bus parent node detection
  net: axienet: document axistream-connected attribute
  net: axienet: make use of axistream-connected attribute optional
  net: axienet: convert to phylink API

 .../devicetree/bindings/net/xilinx_axienet.txt     |  29 +-
 drivers/net/ethernet/xilinx/Kconfig                |   6 +-
 drivers/net/ethernet/xilinx/xilinx_axienet.h       |  35 +-
 drivers/net/ethernet/xilinx/xilinx_axienet_main.c  | 677 ++++++++++++++-------
 drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c  | 111 ++--
 5 files changed, 593 insertions(+), 265 deletions(-)

-- 
1.8.3.1